EP1447907B1 - Amplificateur à modulation de largeur d'impulsion - Google Patents

Amplificateur à modulation de largeur d'impulsion Download PDF

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Publication number
EP1447907B1
EP1447907B1 EP03255954A EP03255954A EP1447907B1 EP 1447907 B1 EP1447907 B1 EP 1447907B1 EP 03255954 A EP03255954 A EP 03255954A EP 03255954 A EP03255954 A EP 03255954A EP 1447907 B1 EP1447907 B1 EP 1447907B1
Authority
EP
European Patent Office
Prior art keywords
switching element
switching elements
pulse width
full
bridge circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
EP03255954A
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German (de)
English (en)
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EP1447907A1 (fr
Inventor
Mitsugi Fukushima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
D&M Holdings Inc
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D&M Holdings Inc
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Publication of EP1447907A1 publication Critical patent/EP1447907A1/fr
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Publication of EP1447907B1 publication Critical patent/EP1447907B1/fr
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/351—Pulse width modulation being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/516—Some amplifier stages of an amplifier use supply voltages of different value

Definitions

  • the present invention relates to a pulse width modulation amplifier, in particular, it relates to a pulse width modulation amplifier which is capable of suppressing an output distortion.
  • a Class D amplifier such as PWM (Pulse Width Modulation) amplifier attracts attention from a viewpoint of lower power consumption, since in the Class D amplifier, a loss in an output stage is smaller comparing to a Class A amplifier and a Class B amplifier.
  • PWM Pulse Width Modulation
  • Fig. 6 is a block diagram showing the output stage of a pulse width modulation amplifier according to earlier development.
  • Vcc represents a direct-current power source.
  • Reference numbers 31, 32, 33 and 34 respectively indicate a first switching element, a second switching element, a third switching element and a fourth switching element. These switching elements 31, 32, 33 and 34 constitute a bridge circuit.
  • Reference numbers 5 and 6 indicate low pass filters for filtering a noise, and reference number 7 indicates a loud speaker as a load on the bridge circuit.
  • Fig. 7 is a waveform chart showing operations of each part of the pulse width modulation amplifier as shown in Fig. 6.
  • D indicates a driving signal which is supplied to the first and the fourth switching elements 31 and 34
  • -D inversion signal of "D"
  • Vsp indicates a voltage to be applied to the loud speaker 7
  • isp indicates a loud speaker current.
  • Fig. 8 is an overall block diagram of the pulse width modulation amplifier as shown in Fig. 6.
  • Reference number 21 indicates an input section to which audio data is inputted from a reproducing unit such as a CD (Compact Disc) player, for example.
  • Reference number 22 indicates a digital filter by which the audio data is subjected to a computing process such as tone control, and low-pass filtering.
  • Reference number 23 indicates a PWM generating section which generates the driving signals D and -D for driving the switching elements 31, 32, 33 and 34.
  • Reference number 24 indicates an output stage corresponding to the bridge circuit comprising the first to the fourth switching elements 31, 32, 33 and 34.
  • the PWM generating section 23 compares the audio data and a triangular wave, for example, and generates the driving signals D and -D based on the comparison result.
  • the driving signal D becomes level "H" which is supplied by the PWM generating section 23 to the switching elements 31, 34
  • the switching elements 31, 34 are turned “ON”, and a forward voltage ⁇ is applied to the loud speaker 7 (see Fig. 7) .
  • the driving signal -D becomes level "H” which is supplied by the PWM generating section 23 to the switching elements 32, 33
  • the switching elements 32, 33 are turned “ON”, and a reverse voltage ⁇ is applied to the loud speaker 7. Therefore, as shown in the left portion of the waveform of "vsp" in Fig.
  • the output from the pulse width modulation amplifier is determined by a pulse width of the driving signal and amplitude of the power supply voltage. Therefore, in order to obtain an amplifier output without any distortion, the output stage of the pulse width modulation amplifier needs a supply of driving signals D, -D, each having a precise pulse width, and a power supply voltage with a limited voltage regulation.
  • a distortion in the output from the amplifier due to the regulation in the power supply voltage can be removed, by adding a constant voltage diode within a D class amplifier, since the constant voltage diode is capable of generating a reference voltage which gives a constant voltage function to a transistor as a switching element.
  • a distortion in the output from the amplifier due to a regulation in a power supply voltage can be removed, by correcting a pulse width of a driving signal according to a detected result as to the power supply voltage regulation.
  • the present inventor finds, according to the amplifier disclosed in Japanese patent applications Laid-Open No.552-96854 , when it is required to handle a high-power output, a loss due to the transistor in the output stage is increased, and then efficiency may be deteriorated.
  • the present inventor finds, according to the amplifier disclosed in Japanese patent application Laid-Open No.S61-39708 and No-H03-159409 , the pulse width correcting lags behind the detection of the power supply voltage regulations, the distortion in the output from the amplifier may not be sufficiently removed
  • US 2002/0135419 A1 discloses a class D amplifier which uses a summation of two or more PWM output stages to achieve an increased dynamic range and improved linearity for any given clock operating speed.
  • a preferable object of the present invention is to suppress a distortion in an output from a pulse width modulation amplifier, due to a regulation in a power supply voltage, without deteriorating efficiency.
  • the present invention provides a pulse width modulation amplifier which supplies to a load circuit an amplified output having been subjected to a pulse width modulation, comprising :
  • Fig. 1 is a circuitry diagram of an output stage of a pulse width modulation amplifier relating to the present embodiment.
  • Vcc1 represents a direct-current power source.
  • Reference numbers 1, 2, 3 and 4 respectively indicate four switching elements constituting the first full-bridge circuit, namely, the first switching element 1, the second switching element 2, the third switching element 3 and the fourth switching element 4.
  • Each of the switching elements 1, 2, 3 and 4 is configured, for example, by FET (Field Effect Transistor).
  • Reference numbers 5 and 6 indicate low pass filters for filtering a noise and reference number 7 indicate a loud speaker as a load on the first full-bridge circuit.
  • Vcc2 represents a second direct-current power source.
  • the reference numbers 11, 12, 13 and 14 respectively indicate four switching elements constituting the second full-bridge circuit, namely, the fifth switching element 11, the sixth switching element 12, the seventh switching element 13 and the eighth switching element 14.
  • Each of the switching elements 11, 12, 13 and 14 is configured, for example, by FET (Field Effect Transistor).
  • the loud speaker 7 and the low pass filters 5, 6 bridge a pair of opposing connecting points "a2" and a3" of the first full-bridge circuit.
  • a2 is a connecting point between the first and the second switching elements 1, 2, and a3 is a connecting point between the third and the fourth switching elements 3, 4.
  • the loud speaker 7 and the low pass filters 5, 6 bridge another pair of opposing connecting points b2 and b3 of the second full-bridge circuit.
  • b2 is a connecting point between the fifth and the sixth switching elements 11, 12 and b3 is a connecting point between the seventh and the eighth switching elements 13, 14.
  • the loud speaker 7 and the low pass filters 5, 6 for filtering noise are connected as common load circuit to the first and the second full-bridge circuits. Therefore, the first full-bridge circuit and the second full-bridge circuit have a similar configuration, being provided with a common load circuit.
  • Fig. 2 is a waveform chart showing operations of each part of the pulse width modulation amplifier of the present embodiment.
  • Cf indicates a carrier signal as a control reference
  • A indicates a driving signal supplied to the first and the fourth switching elements 1, 4 of the first full-bridge circuit
  • A indicates a driving signal supplied to the second and the third switching elements 2, 3 of the first full-bridge circuit.
  • an active period "ta + ta"' of the driving signals A, A' is set to be approximately equal to the cycle "Tc" of the carrier signal Cf .
  • the active period ta + ta' represents a sum of the driving period "ta” of the driving signal A and the driving period "ta'" of the driving signal A'.
  • an active period "tb + tb'" of the driving signals B, B' is set to be approximately equal to the cycle "Tc" of the carrier signal Cf.
  • the active period tb + tb' represents a sum of the driving period "tb” of the driving signal B and the driving period "tb"' of the driving signal B'.
  • Vsp indicates a voltage applied to the loud speaker 7 and "isp” indicates a loud speaker current.
  • Fig. 3 is an overall block diagram of the pulse width modulation amplifier relating to the present embodiment.
  • the pulse width modulation amplifier includes an input section 21, a digital filter 22, a driving circuit (a PWM generating section 23, a driving signal generating section 25), and an output stage 26, and other things. It is to be noted since the configuration having a same reference number used commonly in Fig. 3 and Fig. 8 carries out a same function, explanation thereof will be omitted.
  • the driving signal generating section 25 generates driving signals A, A', B, and B' based on the driving signals D, -D, which have been generated in the PWM generating section 23.
  • the driving signal A is to be supplied to the first and the fourth switching elements 1, 4 of the first full-bridge circuit
  • the driving signal A' is to be supplied to the second and the third switching elements 2, 3 of the first full-bridge circuit
  • the driving signal B is to be supplied to the fifth and the eighth switching elements 11, 14 of the second full-bridge circuit
  • the driving signal B' is to be supplied to the sixth and the seventh switching elements 12, 13 of the second full-bridge circuit.
  • the output stage 26 is configured by a parallel circuit including the first full-bridge circuit connected to the first direct-current power source Vcc1, and the second full-bridge circuit connected to the second direct-current power source Vcc2.
  • Fig. 4 is an illustration for explaining the details of the driving signal generating section 25 of Fig. 3.
  • the driving signal generating section 25 includes a carrier signal generating section 31 which generates a carrier signal Cf, a divider 32 which divides the carrier signal Cf, for example, in half, a NOT circuit 33, and AND circuits 34, 35, 36 and 37.
  • the audio data is subjected to a computing process such as tone control and low pass filtering by the digital filter 22.
  • a computing process such as tone control and low pass filtering by the digital filter 22.
  • driving signals D, -D are generated based on a comparison result between the audio data and a triangular wave, and thus generated driving signals D, -D are inputted into the driving signal generating section 25.
  • the driving signal generating section 25 the logical AND between the driving signals D, -D from the PWM generating section 23 and an output from the divider 32 is carried out, whereby the driving signals A, A' are generated.
  • the logical AND between the driving signals D, -D from the PWM generating section 23 and an output from the NOT circuit 33 is carried out, whereby the driving signals B, B' are generated.
  • Those driving signals A, A' , B and B' thus obtained are respectively supplied to predetermined switching elements in the first and the second full-bridge circuits.
  • the driving signal A is supplied to the first and the fourth switching elements 1, 4 in the first full-bridge circuit
  • the driving signal A' is supplied to the second and the third switching elements 2, 3 in the first full-bridge circuit
  • the driving signal B is supplied to the fifth and the eighth switching elements 11, 14 in the second full-bridge circuit
  • the driving signal B' is supplied to the sixth and the seventh switching elements 12, 13 in the second full-bridge circuit.
  • the driving signal A which is supplied to the first and the fourth switching elements 1, 4, or the driving signal A' which is supplied to the second and the third switching elements 2, 3 becomes level "H"
  • a connection is established between the first direct-current power source Vcc1 and the loud speaker 7, to supply the forward voltage ⁇ or the reverse ⁇ with respect to the loud speaker 7.
  • the driving signal B which is supplied to the fifth and the eighth switching elements 11, 14, or the driving signal B' which is supplied to the sixth and the seventh switching elements 12, 13 becomes level "H”
  • a connection is established between the second direct-current power source Vcc2 and the loud speaker 7 to supply the forward voltage ⁇ or the reverse voltage ⁇ to the loud speaker 7.
  • the driving signals A, A' and the driving signals B, B' are alternately activated every cycle of the carrier signal Cf. Therefore, each of two sets of the switching elements, constituting one full-bridge circuit is alternately put into on-state for one time, while another two sets of switching elements constituting the other full-bridge circuit are in off-state.
  • two sets indicate a set of the first and the fourth switching elements and a set of the second and the third switching elements for the first full-bridge circuit, or a set of the fifth and the eighth switching elements and a set of the sixth and the seventh switching elements for the second full-bridge circuit.
  • each of two sets of the switching elements in the first full-bridge circuit (a set of the first and the fourth switching elements 1, 4 and a set of the second and the third switching elements 2, 3) is alternately put into on-state for one time.
  • each of the two sets of the switching elements in the second full-bridge circuit (a set of the fifth and the eighth switching elements 11, 14 and a set of the sixth and the seventh switching elements 12, 13) is alternately put into on-state for one time.
  • the set of switching elements 11, 14 is put into on-state in advance, which has a same positional relationship with the set of switching elements 1, 4, with respect to the loud speaker 7, the set of switching elements 1, 4 being also put into on-state in advance among the two sets of the switching elements of the first full-bridge circuit. Accordingly, the two full-bridge circuits are alternately activated.
  • the power source current is supplied to the load circuit alternately from the first direct-current power source Vcc1 and the second direct-current power source Vcc2. Therefore, comparing to the case where only one full-bridge circuit is employed in the output stage, the period when the power is applied from each of the direct-current power source Vcc1, Vcc2 is made one-half. Even in this state, since the output voltages generated by the two full-bridge circuits are synthesized at the both edges of the loud speaker 7, as shown in Fig. 2, the applied voltage Vsp of the loud speaker 7 has a waveform similar to that of the case where a pulse width modulation amplifier according to earlier development is employed.
  • the loud speaker 7 is forward-driven during the period t1 when the application period of the forward voltage ⁇ is longer than the application period of the reverse voltage ⁇ , whereas it is reverse-driven during the period t2 when the application period of the forward voltage ⁇ is shorter than the application period of the reverse voltage ⁇ .
  • the power supply current is supplied to a load circuit alternately from the first direct-current power source Vcc1 and the second direct-current power source Vcc2. Therefore, even if the output voltage of one direct-current power source is lowered due to a supply of a power source current, it can restore the output voltage, during the time when the other direct-current power source is supplying the power source current. For example, even after a flow of a load current in large volume, it is possible to secure a time to restore the voltage drop. Consequently, though a constant voltage diode is not employed for providing a transistor in the output stage with a constant voltage function, it is possible to prevent an occurrence of amplifier output distortion. In other words, the distortion of the amplifier output due to a regulation in the power supply voltage can be suppressed without deteriorating efficiency.
  • the driving signal D being one of the two types of driving signals D, -D, which have been generated by the PWM generating section 23, switches on and off the switching element 41 in the positive pole side of the first direct-current power source Vcc1 of the first half-bridge circuit and the switching element 52 in the negative pole side of the second direct-current power source Vcc2 of the second half-bridge circuit.
  • the other driving signal -D switches on and off the switching element 42 in the negative pole side of the first direct-current power source Vcc1 of the first half-bridge circuit and the switching element 51 in the positive pole side of the second direct-current power source Vcc2 of the second half-bridge circuit.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)

Claims (1)

  1. Amplificateur à modulation de largeur d'impulsion qui fournit à un circuit de charge une sortie amplifiée ayant été soumise à une modulation de largeur d'impulsion, comprenant:
    un premier circuit série comprenant un premier élément de commutation (41) relié à un côté de pôle positif d'une première source de puissance de courant continu (Vcc1), et un deuxième élément de commutation (42), une extrémité dudit circuit de charge étant reliée à un point de connexion entre ledit premier élément de commutation (41) et ledit deuxième élément de commutation (42), et
    un deuxième circuit série comprenant un troisième élément de commutation (51) relié à un côté de pôle positif d'une deuxième source de puissance de courant continu (Vcc2), et un quatrième élément de commutation (52), l'autre extrémité dudit circuit de charge étant reliée à un point de connexion entre ledit troisième élément de commutation (51) et ledit quatrième élément de commutation (52), caractérisé en ce que l'amplificateur comprend en outre:
    un circuit d'entraînement qui met en service un ensemble dudit premier élément de commutation (41) et dudit quatrième élément de commutation (52), et un ensemble dudit deuxième élément de commutation (42) et dudit troisième élément de commutation (51), ensemble par ensemble, chacun desdits ensembles étant alternativement mis dans un état en service.
EP03255954A 2003-02-17 2003-09-23 Amplificateur à modulation de largeur d'impulsion Expired - Fee Related EP1447907B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003038735 2003-02-17
JP2003038735 2003-02-17

Publications (2)

Publication Number Publication Date
EP1447907A1 EP1447907A1 (fr) 2004-08-18
EP1447907B1 true EP1447907B1 (fr) 2007-11-07

Family

ID=32677666

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EP03255954A Expired - Fee Related EP1447907B1 (fr) 2003-02-17 2003-09-23 Amplificateur à modulation de largeur d'impulsion

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US (1) US6967527B2 (fr)
EP (1) EP1447907B1 (fr)
DE (1) DE60317299T2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7932777B1 (en) * 2003-03-24 2011-04-26 Zipfel Jr George Gustave Switching amplifier for driving reactive loads
US7382188B2 (en) * 2006-06-16 2008-06-03 Mstar Semiconductor, Inc. Circuit for reducing distortion of class D amplifier
KR101122390B1 (ko) * 2007-02-01 2012-03-23 제이엠 일렉트로닉스 엘티디. 엘엘씨 스위칭 증폭기용 샘플링 주파수를 증가시키기 위한 방법 및 시스템
US8995691B2 (en) 2008-07-14 2015-03-31 Audera Acoustics Inc. Audio amplifier
CN102843110B (zh) * 2011-06-22 2016-02-24 无锡闻德科技有限公司 三电平d类音频功率放大器
EP2654205B1 (fr) 2012-04-16 2016-08-17 Nxp B.V. Amplificateurs de classe D
US9806684B2 (en) * 2015-09-11 2017-10-31 Ess Technology, Inc. Method and apparatus for achieving very high-output signal swing from class-D amplifier
US10658988B1 (en) * 2018-04-02 2020-05-19 Cirrus Logic, Inc. Open-loop class-D amplifier system with analog supply ramping

Family Cites Families (11)

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Publication number Priority date Publication date Assignee Title
JPS5839408B2 (ja) * 1976-02-10 1983-08-30 シャープ株式会社 パルス幅変調増幅器
JPS6139708A (ja) * 1984-07-31 1986-02-25 Akai Electric Co Ltd パルス幅変調アンプにおける電源電圧変動補正方法
JP2844479B2 (ja) 1989-11-17 1999-01-06 富士通テン株式会社 スイッチングアンプの電源変動補償回路
US5612646A (en) * 1995-08-30 1997-03-18 Berning; David W. Output transformerless amplifier impedance matching apparatus
US6175272B1 (en) * 1997-12-19 2001-01-16 Nikon Corporation Pulse—width modulation system
WO2000028658A1 (fr) * 1998-11-12 2000-05-18 Larry Kirn Amplificateur a commutation de haute precision, a references multiples
JP2002532933A (ja) * 1998-12-08 2002-10-02 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 信号を増幅する装置
US6388514B1 (en) * 1998-12-23 2002-05-14 International Rectifier Corporation Class D high voltage amplifier system with adaptive power supply
US6294954B1 (en) * 1999-09-23 2001-09-25 Audiologic, Incorporated Adaptive dead time control for switching circuits
US6211728B1 (en) * 1999-11-16 2001-04-03 Texas Instruments Incorporated Modulation scheme for filterless switching amplifiers
US6593807B2 (en) * 2000-12-21 2003-07-15 William Harris Groves, Jr. Digital amplifier with improved performance

Also Published As

Publication number Publication date
DE60317299T2 (de) 2008-08-28
US20040160271A1 (en) 2004-08-19
US6967527B2 (en) 2005-11-22
DE60317299D1 (de) 2007-12-20
EP1447907A1 (fr) 2004-08-18

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