EP1444780A1

EP1444780A1 - Semiconductor circuit, especially for ignition purposes, and the use of the same

Info

Publication number: EP1444780A1
Application number: EP02774426A
Authority: EP
Inventors: Rainer Topp; Horst Meinders; Wolfgang Feiler
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2001-10-09
Filing date: 2002-09-30
Publication date: 2004-08-11
Also published as: WO2003034590A1; US20040075103A1; DE10149777A1; US7057240B2; JP2005506707A

Abstract

The invention relates to a semiconductor circuit, especially for ignition purposes, comprising a semiconductor circuit-breaker device (100) provided with a first main connection (102), a second main connection (101) and a control connection (103); a clamping diode device (205a, 205b) which is arranged between the first main connection (102) and the control connection (103) and is used to clamp an external voltage (VA) applied to the first main connection, said clamping diode device (205a, 205b) comprising a first part (205a) having a first clamping voltage and a second part (205b) having a second clamping voltage, the second part (205b) being connected in series to the first part (205a); a controllable semiconductor switch device (402) which is arranged parallel to the first part (205a), for bridging the first part (205a) in a controllable manner in such a way that either the total voltage of the first and second clamping voltages, or the second clamping voltage, is used to clamp the external voltage (VA) applied to the first main connection (102); and a control circuit (403) for controlling the controllable semiconductor switch device (402) according to a pre-determined operating state of the semiconductor circuit-breaker device (100).

Description

Semiconductor circuitry, particularly for ignition uses, and use

STATE OF THE ART

The present invention relates to a semiconductor circuit arrangement, in particular for ignition applications.

Although also applicable to other similar semiconductor components, the present invention and the underlying problem with regard to a vertical IGBT (Insulated Gate Bipolar Transistor) for ignition uses are explained.

In general, the IGBTs are used as circuit breakers in the range from a few hundred to a few thousand volts reverse voltage. In particular, the use of such IGBTs as an ignition transistor, i.e. as a switch on the primary side of an ignition coil, of particular interest.

The structure of a vertical IGBT is similar to that of a VDMOS transistor, but with the difference that a p ⁺ emitter is arranged on its anode side instead of an n ⁺ substrate in the VDMOS transistor. A vertical MOSFET component with the basic structure of a vertical IGBT is known from DE 31 10 230 C3. In principle, two types of vertical IGBT or V-IGBT can be distinguished, namely the so-called punch-through IGBT (PT) and the so-called non-punch-through IGBT (NPT), as described for example in Laska et al. , Solid State Electronics, Volume 35, No. 5, pages 681-685.

The basic properties of these two IGBT types are described below with reference to FIG. 6.

FIG. 6 shows a schematic cross-sectional illustration of a known PT or NPT IGBT, which generally bears the reference symbol 100.

A PT-IGBT is usually produced on a thick, p ⁺ -doped substrate with an epitaxially applied n buffer layer 140 and an likewise epitaxially applied n ^~ drift region 104. Since the thickness of the n ^" drift region 104 is chosen to be as small as possible for a forward voltage drop that is as small as the width of the space charge zone in the n ^" drift region 104 requires for the desired blocking capability, the n buffer layer 140 serves to reach through the space charge zone to avoid the p ⁺ emitter 105 provided in the substrate. In order to achieve a rapid shutdown of the current despite a good p ⁺ emitter 105, the carrier lifetime is kept short by means of life-time killing, for example by means of radiation, and / or the doping of the n-buffer layer 140 is chosen to be correspondingly high. Since the forward voltage with increasing doping dose of the n-buffer layer 140, a good compromise between pass-through and switch-off behavior can be achieved with a highly doped thin n-buffer layer 140.

An NPT-IGBT can be derived from the PT-IGBT in that the n-buffer layer 140 is omitted and the thickness of the drift region 104 is chosen to be larger than the width of the space charge zone requires for the desired blocking capacity. The NPT-IGBT is usually produced on a low-doped substrate with a long charge carrier lifetime, whereby after the diffusion profiles have been introduced on the front of the wafer, a flat p ⁺ emitter 105 with only a few μm penetration depth (very much less than 20 μm) and poor emitter efficiency on the Wafer back is manufactured. Such a transparent p ⁺ emitter 105 serves to ensure that the current is quickly switched off during dynamic operation of the component with the aim of keeping the switch-off losses small. In order to achieve satisfactory transmission properties in spite of the poor p ⁺ emitter 105, the carrier lifetime in the n ^" drift region 104 must be chosen as high as possible, and furthermore the thickness of the n ^~ drift region 104 must be chosen as small as possible, taking into account the desired blocking capability of the component ,

At the front, a PT or NPT IGBT is composed of an active region 130 and an edge termination region 150, the latter ensuring the desired blocking capability towards the edge of the chip. The active area 130 sets consist of a large number of parallel-connected cell or strip-shaped MOS control heads 106, 107, 108. These MOS control heads 106, 107, 108 will be explained in more detail later in connection with the functioning of vertical IGBTs.

The MOS control heads 106, 107, 108 are obtained by continuously mirroring the half cell shown in FIG. 6 between the sections AA 'and BB' at the section AA '. In the edge area 150, field plate structures are customary to achieve the desired blocking ability. These usually consist of a cathode 101 designed as a metal field plate, a polysilicon field plate 153a electrically connected to it via the third dimension, not shown, a metallization 152 connected to an n ⁺ channel stopper 155, and a polysilicon field plate electrically connected to the metallization 152 via the third dimension, not shown 153b. Furthermore, reference numeral 159 denotes a field oxide and reference numeral 110 denotes an intermediate dielectric which, apart from targeted contacts, serves to electrically isolate the metallization level from the polysilicon level.

The mode of operation of an NPT or PT IGBT in the case of transmission is first explained in more detail below.

A gate 103, which is usually insulated from the semiconductor body by means of a thin gate oxide layer 109 and is usually made of polysilicon, is applied to the cathode 101 Potential brought above the threshold voltage of the MOS control heads 106, 107, 108. An inversion channel is then generated on the semiconductor surface under the gate 103 in the region of the p-body region 108, whereupon the semiconductor surface in the region of the n ^~ drift region 104 is in the state of accumulation. If the anode 102 has a positive voltage relative to the cathode 101, electrons are injected into the n ^" drift region 104 via the n ⁺ source region 106, the influenced MOS channel and the accumulation layer. The p ⁺ emitter 105 on the anode side is then injected Holes, through which the n ^~ drift region 104 is flooded by charge carriers in such a way that its conductivity is increased in the active region 130 and adjacent parts of the edge termination 150. These parts are in high injection at normal forward current densities 150 - 200 V is able to carry higher current densities with a smaller voltage drop between anode and cathode than a MOS transistor with the same breakdown voltage. In the forward case, the current flows from anode 102 to cathode 101. It is carried by electrons which be injected into the n ^" drift region 104 and via the anode-side p ⁺ emitter 105 to the anode 10 2 flow away and from holes which are injected from the anode-side p ⁺ emitter into the n ^" drift region 104 and flow away via the p regions 107, 108 to the cathode 101.

In addition to the planar vertical IGBT structures discussed here, there are also vertical IGBTs with so-called trench gate, in which the gate is embedded in the form of a trench in the semiconductor surface. See I. Omura et al. , ISPSD '97, Conf. Proc. , Pp. 217-220. The operation of these vertical trench gate IGBTs is completely analogous to the structures discussed above, but they offer the advantage of a lower forward voltage drop.

The mode of operation of the NPT or PT-IGBT in the event of a block is to be discussed below. In the blocking case, the gate 103 is brought to a voltage below the threshold voltage with respect to the cathode 101. If the anode 102 is now brought to a positive potential, the space charge zone formed at the boundary between the p-body region 108 and the n ^~ drift region 104 almost exclusively extends into the n ^~ drift region 104.

In the case of the NPT-IGBT, the thickness of the n ^" drift zone 104 is chosen to be greater than the width which the space charge zone has given the maximum blocking capability of the component. This leads to the triangular shape (dashed line) of the electrical indicated in FIG. 6 Field strength | E | along the thickness direction y of the component, the maximum field strength | E | being in the region of the MOS control heads 106, 107, 108.

In the PT-IGBT, the thickness of the n ^" drift zone 104 is selected to be smaller than the width which the space charge zone has for a given maximum blocking capability of the component would. In order to prevent the space charge zone from running onto the rear p ⁺ emitter 105, the n-doped buffer layer 140 is introduced here with the aim of avoiding the punch-through. This leads to the trapezoidal course (solid line) of the electric field strength | E | indicated in FIG. 6 along the thickness direction y of the component. The maximum of the field strength is also in the area of the MOS control heads 106, 107, 108.

FIG. 7 shows a conventional circuit topology in which a vertical IGBT 100 according to FIG. 6 is used as an ignition transistor in the primary circuit of an ignition coil for an internal combustion engine. For this application as an ignition transistor, a V-IGBT with a necessary blocking capacity of approx. 400 - 600 V has so far been used.

7, the V-IGBT 100, which has the main connections 101 corresponding to the cathode, 102 corresponding to the anode and the control connection 103 corresponding to the gate, is via a

Primary winding of an ignition coil 211 connected to the battery voltage V _Ba t at node 210. On the secondary winding side of the ignition coil 211, a spark plug 212, a protective resistor 214 of 1-2 kΩ and a diode 213 for suppressing the switch-on spark are connected.

The V-IGBT 100 is integrated in a circuit arrangement 200 which has the connection nodes 201, 202 and 203. The connection node 202 is directly connected to the first main terminal 102 of the V-IGBT 100 connected and the connection node 203, which is connected to ground GND, directly connected to the second main terminal 101 of the V-IGBT 100.

The further circuit components within the circuit arrangement 200 serve to control and clamp the V-IGBT 100. In this case, diode 204 serves to protect the gate 103, which is connected to it, against overvoltages. In the case of transmission, the diode 206 prevents a current flow from the control connection 103 to the main connection 102, which flows through the

Semiconductor material of the V-IGBT is connected to the terminal 152. The resistors 207 with, for example, 1 kΩ and 208 with, for example, 10-25 kΩ, on the one hand determine the input resistance of the circuit arrangement 200 at the connection node 201 for a control signal ST and, on the other hand, form the load of a clamp diode device 205, which usually consists of a plurality of clamp diodes Reverse direction of poled silicon zener diodes is executed. The elements 204, 205, 206, 207 and 208 are usually monolithically integrated with the V-IGBT, and in addition to the element 205, the diodes 204, 206 also normally consist of polysilicon.

As outlined, the clamp diode device 205 is not directly connected to the metallization of the anode 102, since this is located on the underside of the chip and is difficult to access. Rather, it is in contact with the metallization 152 of the channel stopper 155, which except for one Forward voltage has the same potential as the anode 102. The circuit arrangement 200 can be operated by a control unit directly via the connection node 201. For this purpose, a control signal ST with a positive voltage of, for example, 5 V is applied to the connection node 201, whereupon a current rise is initiated by the ignition coil 211.

At a certain point in time, the voltage at the connection node 201 is reduced to approximately 0 V, whereupon the voltage at the metallization 152 and at the main connection 102 and thus at the connection node 202 rises steeply. The voltage rise is stepped up on the secondary side of the ignition coil 211 and leads to an ignition spark at the spark plug 212. The clamp diode chain 205 has the

Task to limit the voltage rise at the main connection 102 to the so-called clamp voltage V _L of approximately 400 V in order to protect the V-IGBT 100 on the one hand and the other circuit components of the circuit arrangement 200 on the other hand. This is particularly important in the so-called impulse case.

The pulse occurs when, for example, a spark is not generated due to a dropped ignition cable. Then namely the circuit arrangement designated 200 including the V-IGBT 100 must absorb the energy otherwise converted into the spark. FIG. 3 shows a schematic illustration of the time course of the bracketing of the anode voltage in the conventional circuit arrangement 200.

A time course of the voltage V _A at the first main connection 102 or at the connection node 202 is indicated in FIG. 3 with the dotted curve 302. It is assumed that the ignition switch was switched on for a certain time for t <0, so that a current of typically 7-20 A flows through the V-IGBT 100 and the ignition coil 211 at the time t = 0. If the V-IGBT 100 is switched off by reducing the voltage of the control signal ST at the connection node 201 to 0 V at t = 0, the ignition coil 211 initially forces the full current on it.

Thereupon, the voltage V _A at the first main connection 102 rises steeply. Without a voltage limitation, the voltage V _A at the first main connection 102 would rise up to the breakdown value of the V-IGBT 100 and destroy it. This is prevented by means of the clamp diode device 205 in that when the preselected clamp voltage V _{K is reached} at the time t _r (t _r is typically a few μs), the gate 103 of the V-IGBT 100 is driven just enough to exceed the clamp voltage V _κ ι is avoided at the main connection 102.

There would be no pulse case but the standard operating case shown by the solid curve 301 in Figure 3 is present, then the voltage V _A at the first main terminal 102 would after about ti -. T _r = Break in for 15 μs and generate the spark at spark plug 212 after another approx. 15 μs at tf. The result would be a conversion of the energy stored in the ignition coil 211 in the combustion chamber during the spark burning time t ₃ - tf, in which for the most part only the back-transformed operating voltage of approx. V _B = 30 V is present at the first main connection 102. At the end of the spark burning time t - t _f , the voltage V _A at the main connection 102 will drop again to the battery voltage Vβat = 14 V.

In the pulse case, shown by the dotted curve 302 in FIG. 3, on the other hand, the high clamp voltage of approximately 400 V remains until the time t, and the current flowing through the ignition coil 211 and the V-IGBT 100 consequently increases linearly over time until time t ₄ . At time t, the coil energy is reduced, ie converted in the form of heat in the circuit arrangement 200, and the voltage V _A at the connection 102 drops steeply to the battery voltage V _Bat . The time period t ₄ - t _r only lasts a few hundred μs, but due to the high level of power implemented, this operating case still places high demands on the pulse strength of the IGBT 100, which cannot always be guaranteed to a sufficient degree. In the worst case, this results in the destruction of the IGBT 100.

In J. Yedinak et al., ISPSD '98, Conf. Proc, pp. 399-402, using the example of a PT-IGBT, it is shown that a failure occurs as follows: In the event of a pulse, the space charge zone has covered the entire n ^" drift region 104 When the gate 103 is controlled by means of the clamp diodes 205, electrons are injected into the n ^" drift region 104 via the MOS channel that is formed, which drive the rear p ⁺ emitter 105. As a result of the high current density, the high electric field strength and the resultant associated high power loss in the area of the MOS control heads 106, 107, 108, the component becomes very hot, in particular in the area of the cathode 101, whereupon there is an electron leakage current from the MOS control heads 106, 107, 108. The electrons run in the direction of the anode 102 and control the p ⁺ emitter 105. They therefore act as an additional control of the IGBT 100.

In order to keep the voltage at the value of the clamp voltage, the control of the gate 103 is correspondingly reduced via the clamp diode chain 205. Under certain operating conditions, the activation by the thermally induced electron leakage current is so strong that the V-IGBT 100 can carry the load current without gate activation. Its controllability is lost. Thereupon the temperature and the leakage current of the component continue to rise. Eventually there is thermal positive feedback and the V-IGBT 100 is destroyed. An investigation of the dependence of the pulse strength of the V-IGBTs on the clamp voltage according to ZJ Shen et al., IEEE Electron Device Letters, Volume 21, No. 3, March 2000, pp. 119-122, shows that the pulse strength decreases with decreasing Clamp tension increases sharply. The reason for this is the reduction in the power implemented in the V-IGBT 100 due to the lower bracket Voltage, whereby the maximum temperature occurring in the area of the MOS control heads 106, 107, 108 during the pulse drop is reduced.

If one looks at standard ignition systems of motor vehicles, one finds that in these the clamp voltage cannot be freely selected and in particular cannot be reduced significantly. A significantly reduced clamp voltage would endanger the reliable generation of the ignition spark.

In Z. J. Shen et al., PCIM '96, Conf. Proc, pp. 11-16, discloses an intelligent V-IGBT with current limitation and overtemperature cut-off, in which polysilicon diodes are used as a temperature sensor. When switched on, the IGBT is switched off when a certain threshold temperature is reached by the monolithically integrated control circuit reducing the gate voltage. However, this IGBT is unsuitable as an ignition transistor because it lacks a bracket. In addition, an overtemperature shutdown would be counterproductive due to the reduction of the gate voltage in the event of a pulse, since it would render the bracketing also effective via the gate voltage ineffective.

The problem on which the present invention is based is therefore to create an improved semiconductor circuit arrangement, in particular for ignition applications, with a semiconductor power switch device which can be better protected against the pulse case. ADVANTAGES OF THE INVENTION

The semiconductor circuit arrangement according to the invention, in particular for ignition applications, with the features of claim 1 and the use according to claim 9 have the advantage that the semiconductor circuit breaker device can be better protected in a predeterminable operating phase without its clamp voltage being predefinable in another - reduce their time phase. The circuits necessary for the control according to the invention for determining the time phases can advantageously be monolithically integrated into the semiconductor power switch device.

The idea on which the present invention is based is that the clamp diode device widens a first part with a first clamp voltage and a second part with a second clamp voltage, the second part being connected in series with the first part. Furthermore, a controllable semiconductor switch device, which is connected in parallel with the first part, is provided for controllably bridging the first part, so that either the sum voltage of the first and second clamp voltage or the second clamp voltage for clamping the external ones present at the first main connection Voltage is provided. A control circuit is used to control the controllable semiconductor switch device as a function of a predetermined operating state of the semiconductor power switch device. Advantageous developments and improvements of the subject matter of the invention can be found in the subclaims.

According to a preferred development, the predetermined operating state is an operating temperature of the semiconductor circuit breaker device.

According to a further preferred development, a temperature sensor for detecting the operating temperature is the

Semiconductor circuit breaker device is provided and the control circuit is designed such that it controls the semiconductor switch device for bridging when the operating temperature of the semiconductor circuit breaker device exceeds a predetermined temperature.

According to a further preferred development, the predetermined operating state is a state that is present after a predetermined time delay after a change in state of a control signal present at the control connection.

According to a further preferred development, the control circuit has a timing element for detecting the time delay after the change of state and is designed in such a way that it controls the semiconductor switch device for bridging when the detected time delay exceeds the predetermined time delay. According to a further preferred development, the controllable semiconductor switch device is a second NMOS transistor, the control connection of which is connected to the first main connection via a resistance device and parts of the semiconductor chip.

According to a further preferred development, a voltage conversion device is provided between the control circuit and the controllable semiconductor switch device, which has a first NMOS transistor, the first main connection of which is connected to the control connection of the second NMOS transistor via two diodes connected in series and via the second main connection and Control connection, the control circuit is connected.

According to a further preferred development, the semiconductor circuit breaker device is a vertical IGBT, which has: a rear emitter region of a second line type, a drift region of the first line type and a rear anode contact as the first main connection; an optional buffer area between the drift area and the rear emitter area; a front-side MOS control structure with a front-side source region and a body region, which are introduced into the drift region, and a control contact, which is insulated above the body region and over an adjoining part of the drift region, as a control connection; a front cathode contact which is connected to the front source area and the body area; being the Clamping diode device, the semiconductor switch device and the control circuit are integrated on the front side between an active region and an edge metallization of the semiconductor power switch device.

DRAWINGS

Exemplary embodiments of the invention are shown in the drawings and are explained in more detail in the following description.

Show it:

1 shows a schematic cross-sectional illustration of a semiconductor circuit arrangement for ignition uses according to a first embodiment of the present invention;

2 shows a schematic cross-sectional illustration of a control and switch part of the semiconductor circuit arrangement for ignition applications according to a second embodiment of the present invention;

3 shows a schematic illustration of the time course of the bracketing of the anode voltage of the semiconductor power switch device in the conventional semiconductor circuit arrangement for ignition Phrases and in the embodiments of the invention;

Fig. 4 is a schematic cross-sectional view of a circuit integration solution of the

Semiconductor circuitry for ignition uses according to the embodiments of the invention;

5 shows a schematic top view of the circuit integration solution of the semiconductor circuit arrangement for ignition applications according to the embodiments of the invention;

6 shows a schematic cross-sectional illustration of a known NPT-IGBT or PT-IGBT; and

Fig. 7 shows a conventional circuit topology in which a vertical IGBT is used as an ignition transistor in the primary circuit of an ignition coil for an internal combustion engine.

DESCRIPTION OF THE EMBODIMENTS

In the figures, identical reference symbols designate identical or functionally identical components.

1 shows a schematic cross-sectional illustration of a semiconductor circuit arrangement for ignition uses according to a first embodiment of the present invention.

In FIG. 1, reference numeral 400 generally designates a semiconductor circuit arrangement for ignition uses according to the first embodiment with a special circuit 401 in the region of the clamp diode device 205a, 205b, which is connected between the first main connection 102 and the control connection 103 via the metallization 152. Reference numerals 404, 405, 406, 407 in FIG. 1 denote certain circuit nodes, which will be referred to later.

The clamp diode device 205a, 205b has a first chain part 205a with a first clamp voltage between the circuit nodes 404, 405 and a second chain part 205b with a second clamp voltage, the second part 205b being connected in series with the first part 205a.

Furthermore, a controllable semiconductor switch device 402 is provided, which is connected in parallel to the first part 205a and is used for controllably bridging the first part 205a, so that either the sum voltage of the first and second clamp voltage or the second clamp voltage for clamping the at the first main connection 102 applied external voltage V _{A is} provided.

A control circuit 403 serves to control the controllable semiconductor switch device 402 as a function of a a predetermined operating state of the semiconductor power switch device in the form of the V-IGBT 100.

In particular, the circuit arrangement according to the present embodiment can be provided with a bracket behavior by this special wiring, as is shown by the dashed curve 303 in FIG. 3.

The main idea in this first embodiment is to switch the clamp voltage at a time t ₂ > t _f after the spark generation from the high level of V _KL = 400 V to a significantly lower level V _K '. This lower clamp voltage V _KL 'is preferably above the back-transformed operating voltage V _B in order not to disturb the burning process in standard operation. For example, a value V _KL '= 50 V is a useful value. The time t _{2 should} preferably be chosen as shortly as possible after the spark generation at time t _f . The reduction in the clamp voltage after the spark has been generated on the one hand ensures reliable spark generation by maintaining the high clamp voltage V _KL in the spark generation phase. On the other hand, it significantly reduces the power loss and heat generation occurring in the V-IGBT 100 in the event of a pulse, thereby increasing its pulse strength. As clearly shown in FIG. 3, the dissipation of the energy stored in the ignition coil 211 is distributed over a larger time interval that ends at time t ₅ . According to this embodiment, this behavior can be generated in that the known clamp diode chain 205 according to FIG. 7 is divided into a high-blocking part 205a with a breakdown voltage of, for example, 350 V and a low-blocking part 205b with a breakdown voltage of, for example, 50 V, whereby the high-blocking part 205a can be bridged with the semiconductor switch device 402. When the switch device 402 is open, the full clamp voltage V _KL = 400 V is present, while when the switch device 402 is closed, the reduced clamp voltage V _KL 'is present.

The switching state of the switch device 402 can be selected by a correspondingly designed control circuit 403 according to predetermined criteria. For example, in the first embodiment, temperature control is based on the chip temperature using a temperature sensor TS.

In the temperature-controlled circuit version, the switch device 402 is initially open at t = 0. If the chip temperature detected by the temperature sensor exceeds a predetermined temperature value due to the presence of the pulse case, the switch device 402 is closed by the control circuit 403, whereby the clamp voltage is reduced to the voltage V _KL 'until the end of the pulse case. This end can either also be detected via the temperature, for example falling below one predetermined temperature value, or it can be set automatically after a predetermined time.

The temperature sensor TS required for such a temperature-dependent control can be represented, for example, by means of polysilicon diodes, the temperature-dependent forward voltage of which is evaluated. See Z. J. Shen et al., PCIM '96, Conf. Proc. , Pp. 11-16. In addition, the evaluation of the temperature-dependent reverse current of PN junctions or the temperature-dependent threshold voltage of MOS transistors is generally conceivable as a temperature sensor TS. The temperature sensor TS should preferably be arranged in the middle of the active region 130, since the chip becomes the hottest there. If a specific temperature gradient is taken into account, a placement away from the chip center or from the active region 130 is also possible with a suitable design of the evaluation in the control circuit 403. The voltage supply of the temperature sensor TS together with the associated control circuit 403 can be derived, for example, from the anode voltage or the circuit nodes 405, 406 according to the prior art.

FIG. 2 shows a schematic cross-sectional illustration of the control and switch part 401 of the semiconductor circuit arrangement for ignition applications according to a second embodiment of the present invention.

In the second embodiment, a time-controlled selection of the switching state of the switch device 402 takes place according to 1, which is realized here by the NMOS transistor 650 with the control terminal 653, the further circuit part outside the block 403 representing a voltage level converter.

In general, in the time-controlled selection, the switch device 402 is also open at the time t = 0. A predetermined time t ₂ after switching off the voltage of the control signal ST at the connection node 201 at t = 0, the switch device 402 is closed and the clamp voltage is reduced to V _KL '.

The special control circuit 403 according to FIG. 2 comprises an RC timer consisting of a resistor 510 and a capacitor 511, the latter being able to be formed from a polysilicon electrode which is only separated from the semiconductor by the thin gate oxide 109. The RC timer is charged during t <0 from the positive voltage of the control signal ST present at the connection node 201 via the diode 509 and the decoupling resistor 514 to a maximum of the voltage defined by the diode 504.

A first NMOS transistor 570 with a first and second main connection 571 and 572 and a control connection 573 is thereby switched on during t <0. At time t = 0, the V-IGBT 100 is switched off by applying 0 V to the connection node 201. The circuit node 406 is then also at 0 V and the diode 509 prevents it a sudden discharge of the RC timer, which is why the first NMOS transistor 570 initially remains switched on.

By switching off the voltage at the connection node 201, the voltage V _A at the main connection 102 rises to the high clamp voltage V _KL of 400 V. This clamp voltage V _K L is also approximately at the metallization 152 and consequently at the circuit node 404, while approximately the lower clamp voltage V _K 'is present at the node 405 and at the node 513. For this purpose, the breakdown voltage of the diode 505 is to be chosen to be identical to that of the second partial diode chain 205b. Furthermore, gate protection diodes 507a, 507b are provided for a second NMOS transistor 650 which is arranged in the edge region of the IGBT chip and initially remains blocked.

The capacitor 511 of the RC timer then discharges through the resistor 510, which results in the first NMOS transistor 570 being switched off at the predetermined time t = t ₂ . As a result of the current flow through the high-voltage-resistant polysilicon resistor 659, which is arranged, for example, in a meandering manner in the V-IGBT edge region, the voltage at node 513 rises and turns on the second NMOS transistor 650. Since this corresponds to the switch element 402 in FIG. 1, the high blocking part 205a of the clamp diode chain is then bridged and the clamp voltage is consequently reduced to V _K '. In principle, all of the components used can be integrated monolithically with the V-IGBT 100 from the circuit arrangement explained according to the first or second embodiment.

FIG. 4 shows a schematic cross-sectional illustration of a circuit-technical integration solution of the semiconductor circuit arrangement for ignition applications according to the embodiments of the invention.

In FIG. 4, 600 generally designates an integrated circuit arrangement with the active region 130, a logic circuit region 670 and an edge termination region 150 \, the n-buffer layer 140 being optional.

The known edge termination with the components 152, 153b, 155 according to FIG. 6 is supplemented by the high-voltage-resistant polysilicon meander resistor 659 and the second NMOS transistor 650 according to FIG. 2.

The second NMOS transistor 650 consists of a source metalization 651, which is equipped with a field plate to represent a high blocking capability, just like an associated polysilicon gate 653. 656 denotes an n ⁺ source region, 657 a p ⁺ contact diffusion and 658 a Bo - dy area, on the surface of which is located under the gate 653, an inversion channel can be formed. The first NMOS transistor 570 is represented in the logic area with the p-logic well 577, which is arranged between the cuts BB ′ and CC, and is representative of the other components that can be represented. This consists of a source metallization 571, an n ⁺ drain region 576, an n ⁺ drain metallization 572, an n ⁺ drain region 575 and a gate electrode 573. 577 denotes an associated p-well.

In order to have greater freedom in the interconnection, the n ⁺ source region 576 can be contacted individually via the source metallization 521 and is not short-circuited with the p-well 577. The p-well 577 is at the same potential as the cathode region 101, 107, 108 of the V-IGBT. As a result, it captures holes emitted by the anode-side emitter 105. To be as trouble-free as possible

To ensure the function of the logic, the p-logic trough 577 should be connected to the cathode 101 at as many points as possible via the p ⁺ contact diffusion 107. An optimal solution is to completely enclose each individual NMOS transistor with p ⁺ contact diffusions and body diffusions 107, 108 connected to 101, as is sketched in the cross section according to FIG. 4.

FIG. 5 shows a schematic top view of the circuit-technical integration solution of the semiconductor circuit arrangement for ignition applications according to the embodiments of the invention. In FIG. 5, in addition to the reference numerals 703 already introduced, denotes an area in which the polysilicon diode chains 205a, 205b, 505, 506 are arranged. 702 denotes a metallic gate bondland electrically connected to the gate 103. 701 denotes a cathode bondland, which is a partial area of the cathode metallization of the cathode 101 in the active part 130 of the V-IGBT.

Although the present invention has been described above on the basis of a preferred exemplary embodiment, it is not restricted to this but can be modified in a variety of ways.

Although the invention was explained on a planar n-channel PT-IGBT, it is in principle applicable to other circuit breakers, e.g. planar p-channel PT-IGBTs, planar NPT-IGBTs, trench-PT-IGBTs, trench-NPT-IGBTs, SPT-IGBTs, MOS transistors with planar gate or trench gate etc. can be transferred.

If you swap e.g. the types of doping and the signs of the voltage to be applied are obtained from the n-channel IGBT and a corresponding p-channel IGBT. In general, this is superior to the n-channel NPT-IGBT in terms of latch-up strength, but inferior in terms of avalanche strength.

The representation of RC timers with time constants in the μs range is space-intensive. An also integrable An alternative would be to use a multivibrator with a frequency divider, for example in NMOS resistance logic, instead of the RC timer in the control circuit. The exemplary embodiments of a switched bracketing explained above can be refined in a further, not illustrated embodiment. To do this, consider the case where several sparks cannot be generated in succession. In this case of a longer pulse sequence according to curve 303 from FIG. 3, the average power loss increases compared to a chain of pulses according to curve 302 from FIG. 3. In order to avoid the resulting damage in the construction and connection technology of the circuit arrangement, a warning signal should be generated during this operation by an additional logic, which prevents further power stage control.

For example, at a time t which lies between the time t ₂ and the time t ₅ , the voltage state can be queried by the node 405 or the gate connection 103. If this is above a certain threshold value, so that it indicates a pulse case according to curve 303 of FIG. 3, either the next positive control signal at node 406 can be suppressed directly or an entry into an error counter which only takes place when a certain number is reached of pulses according to curve 303 of FIG. 3 prevents further positive control signals at node 406. The necessary logic and the necessary error counter can be done in the usual way can also be integrated monolithically or arranged externally.

Semiconductor circuitry, particularly for ignition uses, and use

LIST OF REFERENCE NUMBERS:

Claims

Semiconductor circuitry, particularly for ignition and use purposes

1. Semiconductor circuit arrangement, in particular for grit uses, with:

a semiconductor power switch device (100) having a first main connection (102), a second main connection (101) and a control connection (103);

clamp diode means (205a, 205b), which is connected between the first main connection (102) and the control connection (103), for clamping an external voltage (V _A ) present at the first main connection (202);

the clamp diode device (205a, 205b) expanding a first part (205a) with a first clamp voltage and a second part (205b) with a second clamp voltage (V _K ), the second part (205b) in series with the first part (205a) is switched;

a controllable semiconductor switch device (402, 650), which is connected in parallel with the first part (205a), for controllably bridging the first part (205a), so that either the sum voltage (V _KL ) of the first and second clamp voltage or the second clamp voltage (Vκι) is provided for clamping the external voltage (V _A ) present at the first main connection (202); and

a control circuit (403) for controlling the controllable semiconductor switch device (402) as a function of a predetermined operating state of the semiconductor power switch device (100).

2. Semiconductor circuit arrangement according to claim 1, characterized in that the predetermined operating state is an operating temperature of the semiconductor power switch device (100).

3. A semiconductor circuit arrangement according to claim 2, characterized in that a temperature sensor (TS) is provided for detecting the operating temperature of the semiconductor power switch device (100) and the control circuit is designed such that it the semiconductor switch device (402, 650 ) is triggered to bridge if the operating temperature of the semiconductor power switch device (100) exceeds a predetermined temperature.

4. Semiconductor circuit arrangement according to claim 1, characterized in that the predetermined operating state is a state which after a predetermined time delay tion after a change of state of a control signal (ST) present at the control connection (103) is present.

5. Semiconductor circuit arrangement according to claim 4, characterized in that the control circuit (403)

Has a timing element for detecting the time delay after the change of state and is designed such that it controls the semiconductor switch device (402, 650) for bridging when the detected time delay exceeds the predetermined time delay.

6. Semiconductor circuit arrangement according to one of the preceding claims, characterized in that the controllable semiconductor switch device (402, 650) is a second NMOS transistor (650), the control connection

(653) is connected to the first main connection (102) via a resistance device (659).

7. Semiconductor circuit arrangement according to claim 6, characterized in that between the control circuit

(403) and the controllable semiconductor switch device (402, 650) a voltage conversion device is provided which connects a first NMOS transistor (570), the first main connection (571) of which is connected to the control connection (653) of the second NMOS transistor (650) is and via the second main connection (572) and control connection (573) the control circuit (403) is connected.

8. Semiconductor circuit arrangement according to one of the preceding claims, characterized in that the semiconductor power switch device (100) is a vertical IGBT, which has:

a rear emitter region (105) of a second conductivity type (p ⁺ ), a drift region (104) of the first conductivity type (n ^~ ) and a rear anode contact as the first main connection (102);

an optional buffer area (140) between the drift area (104) and the rear emitter area (105);

a front-side MOS control structure with a front-side source region (106) and a body region (108), which are introduced into the drift region (104), and one over the body region (107, 108) and over an adjacent part of the drift region ( 104) isolated control contact as control connection (103); and

a front cathode contact (101) connected to the front source region (106) and the body region (108);

wherein the clamp diode device (205a, 205b), the semiconductor switch device (402, 650) and the control circuit (403) are integrated on the front between an active region (130) and an edge metallization (152) of the semiconductor power switch device (100).

9. Use of a semiconductor circuit arrangement according to one of the preceding claims in an ignition, the first main connection (102) being connected to a primary winding of an ignition coil (211) and the predetermined operating state of the semiconductor power switch device (100) being selected such that it occurs after a point in time (t _f ) which is provided for generating an ignition spark on a spark plug (212) connected to the secondary winding of the ignition coil (211).

10. Use according to claim 10, characterized in that the total voltage (V _KL ) is between 200 and 650 V and the second clamp voltage (V _KL ^Λ ) is between 35 and 75 V.