EP1442522A2

EP1442522A2 - Method for controlling an integrated circuit output during activation, and integrated circuit therefor

Info

Publication number: EP1442522A2
Application number: EP02802644A
Authority: EP
Inventors: Majid Ghameshlu; Karlheinz Krause
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 2001-11-09
Filing date: 2002-11-04
Publication date: 2004-08-04
Also published as: WO2003041118A3; WO2003041118A2

Abstract

The invention concerns a method for controlling an integrated circuit output during activation, and an integrated circuit for implementing said method. The invention is characterized in that the output is maintained at a specific potential until a specific operating state of the integrated circuit is achieved. The inventive integrated circuit is characterized in that it comprises power-on initializing means which, after a power-on signal is established on the power-on signal line, can set at least a specific output at a specific potential for a specific period of time.

Description

description

Method for controlling an output of an integrated circuit during switching on and integrated circuit for carrying out the method.

The present invention relates to a method for controlling an output of an integrated circuit while it is being switched on, and to an integrated circuit with at least one output, the integrated circuit being supplied with voltage by a voltage supply which can directly or indirectly supply a power-on signal , and wherein the power-on signal is applied to the integrated circuit via a power-on signal line.

Electronic assemblies often consist of a large number of integrated circuits. When the module is switched on (power-on phase), it must be ensured that the various components do not work against each other. This means, in particular, that it must be ensured that interconnected outputs and inputs of different integrated circuits do not interfere may have conflicting potential. The behavior of the integrated circuits in the switch-on phase is generally not predictable for the following reasons:

The PLL circuits frequently used for clock generation have an undefined clock during their settling time, so there is no valid clock signal in the entire module.

Clock generation in the individual integrated circuits can also be unstable or invalid, especially if these are obtained from the module cycle using PLL circuits.

The synchronized reset of the clocked elements, these are mostly flip-flops, in the integrated circuits, which control the individual outputs, does not work without a clock signal.

Only those flip-flops that are asynchronously reset by the reset line directly from the integrated circuit without an interposed clock circuit in the integrated circuit or module have clear values during this phase. Due to technical requirements such as B. a synchronization reset, the integrated circuit must be reset synchronously. The asynchronous reset / preset inputs of the flip-flops are therefore not operated. One possible solution is to reset the flip-flops synchronously and asynchronously. This requires two networks within the integrated circuit, with which the flip-flops can be reset synchronously or asynchronously. The

For this purpose, flip-flops should each be equipped with asynchronous reset / preset inputs. This requires a high level of circuitry complexity within the integrated circuit.

The problem underlying the present invention is therefore to reduce the circuit complexity within the integrated circuit in order to achieve a defined power-on behavior of the circuit.

This problem is solved by a method according to claim 14 and an integrated circuit according to claim 1. In the method according to the invention it is provided that the

Output is set to a defined potential until a defined operating state of the integrated circuit is reached. This procedure only requires the wiring of all outputs without having to wire the entire core of the integrated circuit. Regardless of the size of the circuit core, this method therefore requires only a small amount of circuitry.

One embodiment of the method provides that the defined period of time extends until a defined operating state of the integrated circuit is reached. The defined operating state can be determined in such a way that there are valid signals on the output side.

In a further embodiment of the method it is provided that it is determined within the method when the defined operating state of the integrated circuit has been reached. In this way it is possible to dispense with a time switch which sets the output or outputs to a defined potential until a preset time period has expired. Instead, the state of the integrated circuit is considered and the reaching of this state is determined on the basis of measurable conditions.

In a further embodiment of the method, it is provided that the defined operating state is reached as soon as the integrated circuit is initialized. In this operating state, the integrated circuit is ready for operation, therefore the output signals are also valid.

In a preferred embodiment of the method it is provided that the output is set to a high-resistance potential becomes. This potential, labeled High-Z, has a neutral effect on the inputs / outputs of other circuits connected to the output, it prevents impermissible control of the respective input. This is particularly important for bi-directional inputs / outputs of the other circuit.

In the integrated circuit according to the invention it is provided that a power-on initialization is present which, after the power-on signal has been applied to the power-on signal line, can set the at least one output to a defined potential for a specific period of time. The configuration of the integrated circuit according to the invention makes it possible to specify the output signal during the switch-on phase without having to take any technical measures relating to the behavior of the entire core of the circuit. The configuration according to the invention only requires the addition of each circuit of the integrated circuit with additional circuit means, without having to make changes to the actual circuit core.

In a preferred embodiment of the integrated circuit, it is provided that the defined potential is high-resistance (high-Z). This potential holds the least risk of contradicting outputs with interconnected circuits. Alternatively, a low or high level could also be created.

In a preferred embodiment of the integrated circuit, it is provided that the specific period of time includes the period until the integrated circuit is initialized. The outputs of the integrated circuit are only valid afterwards. It is preferably provided that the specific time period includes the time period during which the module clock generator delivers no or no stable clock (t ≤ tpu-BG), furthermore the time period during which the internal clock generation does not supply an internal clock (tpLLBG <t < t _reS pond), the lock time of the internal clock generation (t _re sond <t <tpLLAsic) and the time period (t _PL Asιc <t <tASICUNIT) in the initialization of the integrated circuit 1. After these phases have expired, the integrated circuit is more ready for operation.

In a preferred embodiment of the integrated circuit, it is further provided that the point in time at which the integrated circuit (1) is initialized is determined by the integrated circuit itself. This point in time is therefore not determined by a timer with e.g. fixed preset time, but by circuit-internal conditions that allow a reliable conclusion about the operational readiness of the integrated circuit.

In a preferred embodiment of the integrated circuit, it is provided that it has several outputs. Multiple outputs enable the transmission of multiple independent signals.

In a preferred embodiment it is further provided that the integrated circuit is supplied with a clock signal by a module clock. The clock for several integrated circuits, which is obtained from a central module clock, enables the integrated circuits to be synchronized. Furthermore, it can be provided that the integrated circuit has an internal clock generation, which can reproduce the clock signal supplied by the module clock. In this way, the clock frequency of the integrated circuit can be chosen to be higher than the module clock.

Furthermore ^{, it} can be provided that the integrated circuit has a reset logic which enables the integrated circuit to be reset. Regardless of the operating state and in particular after the switch-on process, the integrated circuit can be reset in this way, the output (s) being set to a high-resistance potential in accordance with the procedure during the switch-on process.

In a preferred embodiment it is provided that the output is controlled via an output buffer. This measure galvanically isolates the circuit core from modules connected to the output.

In a preferred embodiment it is provided that the output buffer is driven by a flip-flop. In this way, the signal to be forwarded to the output is passed on with the clock.

In the preferred embodiment it is further provided that the flip-flop is a master-slave D flip-flop. With this configuration of the flip-flop, no impermissible combinations of signals can occur.

In the preferred embodiment it is further provided that an OR gate is arranged between the flip-flop and the enable input of the output buffer, the output of which is connected to the Enable input of the output buffer, the first input of which is connected to the Q output of the flip-flop and the second input of which is connected to the power-on initialization. In this way, the output signal of the flip-flop is only forwarded if a high level is present at the OR gate on the part of the power-on initialization.

An exemplary embodiment of the present invention is described in more detail below with reference to the accompanying drawings. It shows:

Figure 1 is a schematic diagram;

First, the basic circuit structure is described with reference to FIG. 1. An integrated circuit 1, for example an application specific integrated circuit (ASIC), is supplied with the voltage required for operation via a voltage supply 2. In addition, the voltage supply 2 supplies a power-on signal on a power-on signal line 3 when the supply voltage is present. As in the embodiment described here, the signal can be applied directly to the integrated circuit or via further intermediate units (eg modules, Assemblies), and thus indirectly, be placed on them. The integrated circuit 1 has several outputs 4, only one of which is shown here. A module clock 5 supplies the clock signal for the integrated circuit 1 via a clock line 6. The module clock 5 additionally delivers a lock signal 7. Alternatively, the lock signal 7 can be omitted, in this case the signal is provided by an internal timer delivered. The integrated circuit 1 u contains a circuit core, of which only the output of a circuit block 8 which controls the output 4 is shown in the present exemplary embodiment. The integrated circuit 1 also has an internal clock generator 9, which is designed, for example, as a phase lock loop (PLL) circuit and multiplies the external clock of the clock line 6. The internal clock generation 9 can be omitted if the module clock can be used directly. Furthermore, the integrated circuit 1 has a power-on initialization 10 and a reset logic 11.

The output side of the circuit block 8 is a D flip-flop 12 which is usually implemented as a master-slave D flip. Whose clock input C is connected to the internal clock generation 9, the input D is connected via an AND gate 13 on the one hand to the reset logic 11 and on the other hand to the other logic of the core. The non-inverting output Q of the D flip-flop 12 is connected to an output buffer 15 via a further AND gate 14, the second input of which is connected to the initialization 10. The output buffer 15 is in principle an isolation amplifier with an inverting input.

The function of the circuit when switched on (power-on phase) is described below. In this case, the

Power supply 2 has a power-on signal on power-on signal line 3, but there is still no clock on clock line 6. At this moment, all switching states in circuit 1 are undefined. For this reason, as will be described in the following, output 4 is set to a defined high-resistance potential “High-Z” so that it does not carry any dangerous potential for the modules connected to it. Once in a signal is present at the inverted input of the output buffer 15, the output 4 is set to the potential "high-Z".

As long as the input of the AND gate 14 connected to the power-on initialization 10 is at a low level, its output is also at a low level and, due to the inverting input of the output buffer 15, its output 4 is at a “high-Z ^w . After completion of the power-on initialization of the integrated circuit 1, the input of the AND gate 14 connected to the power-on initialization 10 is switched to "high *", so that the state of the output 4 only depends on the state of the flip-flop 12, or its output Q, depends.

The time behavior of the power-on initialization 10 is described in more detail below. This only switches the output 4 from “high-Z ^λλ ” by means of the output buffer 15 when the initialization of the entire circuit 1 has been completed. This process can be divided into four periods:

t ≤ tLLBG: This is the period of time within which the module clock 5 delivers no or no stable clock, but for which the integrated circuit 1 is already supplied with voltage.

tp _B G <t <t _r esond: During this time, the power-on signal of the power supply to the power-on signal line 3 is present, and at the same time the clock of the module clock 5 is present on the clock line 6. However, the internal clock generation 9 does not yet provide an internal clock.

t _re sond <t <tp _LLA sιc • "This is the lure time of the external clock generation. tpLLAsic <t <tAsicuNiT: The initialization of the integrated circuit 1 takes place in this period.

During these four time periods, all outputs 4 of the integrated circuit 1 are switched to “high-Z ^λ and only released after the initialization. This ensures that the integrated circuit 1 does not drive out any undefined and in particular no active cones. Low or high levels are achieved with pull-ups or pull-downs. The signal by which the output 4 of the integrated circuit 1 is switched to “high-Z 'is identical to the power-on signal of the voltage supply 2 up to t _reS po _n d and is subsequently activated by the power-on initialization 10 for the clock of the internal clock generation 9 um + t _A sιciNiτ extended. The following table summarizes the states for the initialization period.

If the integrated circuit 1 has no internal clock generator 9, the fourth column (t s _re ond _P <t <tp _L LAsιc) falls away.

Claims

claims

1. Integrated circuit (1) with at least one output (4), the integrated circuit (1) being supplied with voltage by a voltage supply (2) which can directly or indirectly supply a power-on signal, and wherein Power-on signal is placed on the integrated circuit (1) via a power-on-signal line (3), characterized in that a power-on initialization (10) is present, which occurs after the power-on Signal on the power-on-signal line (3) can connect the at least one output (4) to a defined potential for a certain period of time.

2. Integrated circuit according to claim 1, characterized in that the defined potential is high impedance (HighZ).

Integrated circuit according to Claim 1 or 2, characterized in that the specific time period comprises the time period until the integrated circuit (1) is initialized.

4. Integrated circuit according to one of claims 1 to 3, characterized in that the specific period comprises the period during which the module clock provides no or no stable clock (t ≤ t _PL LBG) / further the period during which internal clock generation no internal clock provides (t _PL BG <t <corresponding) r of the further the lock time of the internal _{clock generation} (t _reS po _nd

<t <tpLLAsic) and the period (t _PLL Asιc <t <tAsιcuNiτ) in the initialization of the integrated

Circuit 1 is done.

5. Integrated circuit according to claim 3 or 4, characterized in that • • the time at which the integrated circuit (1) is initialized is determined by the integrated circuit itself.

6. Integrated circuit (1) according to one of claims 1 to 5, characterized in that it has a plurality of outputs (4).

7. Integrated circuit (1) according to one of claims 1 to 6, characterized in that this of a module clock (5) with a

Clock signal is supplied.

8. Integrated circuit (1) according to one of claims 1 to 7, characterized in that it has an internal clock generation (9) which can reproduce the clock signal supplied by the module clock (5).

9. Integrated circuit according to one of claims 1 to 8, characterized in that it has a reset logic (11), the one reset of the integrated circuit (1) allows.

10. Integrated circuit (1) according to one of claims 1 to 9, characterized in that the output (4) is controlled via an output buffer (15).

11. Integrated circuit (1) according to claim 10, so that the enable input of the output buffer (15) is controlled by a flip-flop (12).

12. Integrated circuit (1) according to claim 11, characterized in that the flip-flop (12) is a master-slave D flip-flop.

13. Integrated circuit according to one of claims 11 or 12, characterized in that an OR gate (14) is arranged between the flip-flop (12) and the enable input of the output buffer (15), the output of which is connected to the enable -Input of the output buffer (15), the first input of which is connected to the output (Q) of the flip-flop (12) and the second input of which is connected to the power-on initialization (10).

14. Method for controlling an output (4) of an integrated circuit (1) while it is switched on (power-on phase), characterized in that the output (4) is at a defined potential, for example low, for a certain period of time. High or High-Z.

15. The method according to claim 14, characterized in that the defined period of time until a defined operating state of the integrated circuit (1) is reached.

16. The method according to any one of claims 14 or 15, characterized in that it is determined within the method when the defined operating state of the integrated circuit (1) is reached.

17. The method according to claim 16, characterized in that the defined operating state is reached as soon as the integrated circuit (1) is initialized.

18. The method according to any one of claims 14 to 17, characterized in that the output (4) is set to a high-potential (High Z).