EP1430690B1 - Procede pour acceder a une unite de commande pour un reseau de transmission de donnees - Google Patents

Procede pour acceder a une unite de commande pour un reseau de transmission de donnees Download PDF

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Publication number
EP1430690B1
EP1430690B1 EP02774365A EP02774365A EP1430690B1 EP 1430690 B1 EP1430690 B1 EP 1430690B1 EP 02774365 A EP02774365 A EP 02774365A EP 02774365 A EP02774365 A EP 02774365A EP 1430690 B1 EP1430690 B1 EP 1430690B1
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Prior art keywords
command
user device
pointer
application
writing
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Expired - Lifetime
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EP02774365A
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German (de)
English (en)
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EP1430690A2 (fr
Inventor
Dieter BRÜCKNER
Franz-Josef GÖTZ
Dieter Klotz
Karl-Heinz Krause
Jürgen SCHIMMER
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Siemens AG
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Siemens AG
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Priority claimed from DE10237350A external-priority patent/DE10237350A1/de
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Publication of EP1430690B1 publication Critical patent/EP1430690B1/fr
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40019—Details regarding a bus master

Definitions

  • the invention relates to a method for access to a command unit for a data network, in particular a real-time Ethernet, a computer program product and a subscriber with such a command unit and a communication system.
  • a synchronous, clocked communication system with equidistance characteristics is understood as a system of at least two subscribers which are connected to one another via a data network for the purpose of mutual exchange of data or the mutual transmission of data.
  • the data exchange takes place cyclically in equidistant communication cycles, which are specified by the communication clock used by the system.
  • Subscribers are, for example, central automation devices, programming, configuration or operating devices, peripheral devices such as, for example, Input / output modules, drives, actuators, sensors, programmable logic controllers (PLC) or other control units, computers, or machines that exchange electronic data with other machines, in particular processing data from other machines. Subscribers are also called network nodes or nodes.
  • Controlling units are understood in the following controller or control units of any kind, but also, for example, switches and / or switch controllers.
  • data networks for example, bus systems such as e.g. Fieldbus, Profibus, Ethernet, Industrial Ethernet, FireWire or PC-internal bus systems (PCI), etc., but in particular also uses isochronous real-time Ethernet.
  • bus systems such as e.g. Fieldbus, Profibus, Ethernet, Industrial Ethernet, FireWire or PC-internal bus systems (PCI), etc., but in particular also uses isochronous real-time Ethernet.
  • Data networks allow communication between several participants through networking, ie connection of the individual participants with each other. Communication means the Transfer of data between the participants.
  • the data to be transmitted are sent as data telegrams, ie, the data is packed into several packets and sent in this form over the data network to the appropriate recipient. This is why we also speak of data packets.
  • the term transmission of data is used in this document completely synonymous with the above-mentioned transmission of data telegrams or data packets.
  • Automation components eg controllers, drives, Certainly today generally have an interface to a cyclically switched communication system.
  • a runtime level of the automation component (fast-cycle) (eg position control in a controller, torque control of a drive) is synchronized to the communication cycle. This sets the communication clock.
  • Other low-speed algorithms eg, temperature controls
  • the automation component can also communicate with other components (eg binary switches for fans, pumps, etc.) only via this communication clock, although a slower cycle would be sufficient.
  • High demands are placed on the bandwidth of the transmission link in the system.
  • command unit for accessing a data network (command interface) on a multi-master system
  • multiple applications can access the command unit simultaneously or in succession, but in any case uncoordinated. It is necessary to coordinate the individual applications with the command interface in order to ensure the transfer and processing of the commands on the command interface.
  • processors master of the subscriber can be provided.
  • the invention is therefore based on the object to provide an improved method for accessing a command unit for a data network.
  • the invention is further based on the object to provide an improved computer program for accessing an application to such a command unit and a subscriber to a communication system.
  • the instruction transfer to the instruction unit is not directly, but indirectly, by merely passing a pointer to the address area of the instruction structure in the memory of the subscriber in the input register of the instruction unit.
  • the transfer of the command to the command unit can be performed as an "atomic" write access to the input register, which requires, for example, only one bus clock.
  • the instruction unit is used to perform certain basic operations via the data network.
  • the command unit is used by the subscriber's various applications via a common interface. All applications are treated as equivalent.
  • the access to an internal data bus of the subscriber for the access of the applications to the command unit is regulated by an arbitration unit.
  • a command structure is first stored in the memory of the subscriber, in particular the communication memory, before this command structure is written into the input register by writing a pointer to the address area of the command structure in the memory. Both the processor and the instruction unit can access the communication memory.
  • the instruction unit then accesses the instruction structure and processes it.
  • This has the advantage compared to the direct transfer of the command parameters to the command unit, Command structures of any length, for example more than 32-bit, can be processed.
  • the execution time for executing a command structure is not limited and may return different amounts of information.
  • Another advantage is that commands can be issued by multiple applications, which need not necessarily be coordinated with each other. Furthermore, several, even same commands can be written directly one after the other in the input register, without having to wait for the execution of each command.
  • commands received via the input register are acknowledged by the instruction unit in that the instruction unit enters the confirmation in a confirmation field in the instruction structure in the memory of the subscriber.
  • the data bus there are no requirements for the data bus to be curled, that is, the bus is never lured beyond a single read or write operation.
  • the amount of information transmitted between the applications and the instruction unit is not limited to the top. Coordination such as interrupt locks between the calling applications is not necessary.
  • all commands issued by the applications are transferred to the input register (command interface) in a write cycle in order to avoid bus lock times.
  • the command interface is merely passed a pointer (address) to a memory area containing the command structure previously stored by the application in the memory. This avoids multiple write accesses to the command interface, otherwise required for multi-operand commands.
  • command data from a defined command structure are then read out from the command interface, interpreted and passed to the corresponding execution unit for processing.
  • the active bus users of the data bus can independently perform write accesses to the command interface. This also supports multi-tasking by unordered (mixed) accesses of the various applications to the command interface. In order not to interlock the individual tasks of an application by interrupt locks, mechanisms are preferably implemented in the command interface, which allow random access of all applications to the interface in the most different order and at different times.
  • the "acknowledge" field is preferably set first before the command interface becomes writable again.
  • the assumption of a command is usually completed with the chaining of the command structure in a command list, so it is done quickly.
  • An optimization on the shortest possible and guaranteed takeover time has priority in order to avoid unnecessary delays in the execution of the software when writing to the command interface again.
  • a command or sequences of applications is passed to the command unit via a shared input register (command register).
  • the address is stored in a command structure in the command register.
  • the structure itself contains all the data necessary for the execution of the command.
  • the transferred command structure is chained in a command list.
  • the command structure contains a "next" pointer, which can be used to chain unprocessed structures.
  • the "next" pointer contains the address of the next unhandled command structure. This chaining caches the command structures in the command list. This achieves a decoupling between command processing and command transfer.
  • the associated command structures are returned to the user.
  • the output register also referred to below as the output register
  • the edited structures are chained into separate, subscriber-dependent return lists. The return of each edited structure will be announced to the respective participant.
  • the concatenated command structures are returned via the return register.
  • an application passes a command structure through a write access to the command register to the command interface.
  • the application must preferably analyze the "acknowledge" field of the command structure. If the confirmation is set in the "Acknowledge” field of the structure, the command structure was adopted and linked into the command list. The unconfirmed transfer of the structure leads to a cyclic write access to the command register (polling).
  • the disclosed methods can be used or used in automation systems, in particular in and in packaging machines, presses, plastic injection machines, textile machines, printing machines, machine tools, robors, handling systems, wood processing machines, glass processing machines, ceramic processing machines and hoists.
  • the invention is suitable for both communication applications and other applications, e.g. Command interfaces of other intelligent subsystems, especially graphics systems, can be used.
  • FIG. 1 shows a subscriber 100 of a data network 102.
  • the data network 102 may be, for example, a real-time Ethernet for applications in automation technology.
  • To such a data network 102 typically several participants are connected, which are basically the same as the subscriber 100 is constructed. This creates a communication system.
  • the subscriber 100 has a plurality of applications 104, 106, 108,... That can access a data bus 110 of the subscriber 100.
  • the access of the individual applications 104, 106, 108,... To the data bus 110 is regulated by an arbiter 112.
  • the subscriber 100 has a memory 114 and an instruction unit 116.
  • the memory 114 and the instruction unit 116 are likewise coupled to the data bus 110.
  • Each of the applications 104, 106, 108 may describe the memory 114 with a command structure 118 via the data bus 110.
  • the instruction structure 118 is comprised of an instruction 120 executable by the instruction unit 116 and a confirmation field 122.
  • the instruction structure 118 is stored in an address area of the memory 114 pointed to by the pointer 124.
  • the instruction unit 116 is coupled to both the data bus 110 and the data network 102.
  • the instruction unit 116 serves to perform various basic operations involving the data network 102 with respect to the applications 104, 106, 108,.
  • the instruction unit 116 includes an interface for the applications 104, 106, 108,... Which has a command register 126 and a plurality of return registers 128.
  • the command register 126 serves as an input register for storing pointers 124.
  • the command register 126 can access any of the applications 104, 106, 108,... Via the data bus 110.
  • each of the return registers 128 is associated with a particular application.
  • the return register 130 is associated with the application 104, the return register 132 with the application 106 and the return register 134 with the application 108, etc.
  • the instruction unit 116 further includes a command list 136, which is also referred to as a so-called stack.
  • the command list 136 contains the commands accepted and to be processed by the command unit 116.
  • the instruction unit 116 has a logic circuit 138 for processing the instructions.
  • one of the applications of the subscriber 100 accesses the memory 114 via the data bus 110 in order to store a command structure 118 there. Thereafter, the application 104 accesses the command register 126 via the data bus 110 with a write access to write the pointer 124 to the command structure 118 in the command register 126.
  • the instruction unit 116 then takes the command structure 118 from the memory 114 into the command list 136 and confirms the acquisition by a corresponding entry in the confirmation field 122 of the command structure 118.
  • the instruction unit 116 After processing the instruction structure 118, the instruction unit 116 writes the pointer 124 into the return register 130 associated with the application 104.
  • the application 104 may query the return register 130 through read access over the data bus 110 to check if the instruction structure 118 has already been executed.
  • FIG. 2 shows a development of the command interface of FIG. 1.
  • the command register 126 can be described by the various applications 104, 106, 108, ... uncoordinated. From the inherited command structures 118, the command list 136 results.
  • each of the return registers 130, 132, 134,... is assigned a return list 140,...
  • the return list 140 being assigned to the return register 130, which in turn is assigned to the application 104.
  • the output of pointers 124 can be buffered.
  • the instruction structure 118 has a field 142 for storing one or more instructions 120 (see FIGURE 1), a field 144 for storing an acknowledgment, which corresponds to the confirmation field 122 of Figure 1, as well as a field 146 for storing a pointer 148 to another command structure 118, which is constructed in principle the same.
  • the further instruction structure 118 has a pointer 150 to another instruction structure 118, etc.
  • the last instruction structure 118 of the chain has no further pointer, indicating the last member of the concatenated instruction structure.
  • the instruction structures 118 also have fields 152 for storing parameters, payloads, or operands for execution of the particular instruction 120.
  • FIG. 4 shows a flowchart of a method for operating the system of FIG. 1.
  • the method is subdivided into a software process 154 and a hardware process 156.
  • the application executes the software process 154, for example the application 104 of FIG. 1, has write access to the command register in one bus cycle. This is done in step 202.
  • the application 104 passes the pointer 124 to a command structure 118 or a chain of command structures 118. This starts the hardware process 156.
  • step 204 of the hardware process 156 it is checked whether the command register is writable. If this is not the case, the process ends in step 206. In this case, the application must restart the software process 154 with step 200.
  • the command register is writable
  • the pointer 124 passed from the application 104 is entered into the Command Register, which is done in step 206. Thereafter, the writing of the command register is disabled in step 208 so that other applications can not overwrite the pointer in the register.
  • step 210 the command structure or the linked command structure is adopted, that is, there is a chaining of the commands to be processed in the command list and confirmation of the transfer in the confirmation field of the command structure.
  • step 212 the writing of the command register is released again in step 212, and the flow of the hardware process 156 ends with step 206.
  • step 202 After the write cycle in step 202, a read cycle is performed in the software process 154 in step 214 on the command register in step 214. In step 216, it is checked whether the data previously written to the command register in step 202, that is, the pointer 124, is still in the command register.
  • step 218 the software process ends with step 218. If so, this means that a takeover of the command structure has taken place in step 210, so that the software process ends with step 218. If the opposite is the case, this may mean that an acquisition has taken place and another application has already described the command register with another pointer, or that an acquisition by the hardware process 156 has not taken place. In this case, in step 220, the confirmation field in the command structure is checked. If a confirmation has been entered there, then the software process 154 can be terminated with the step 218 again. If this is not the case, the sequence control has to go back to the step 202.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Bus Control (AREA)
  • Read Only Memory (AREA)

Claims (17)

  1. Procédé pour accéder à une unité de commande (116) pour un réseau de données (102), avec les étapes suivantes :
    - fonctionnement de plusieurs applications (104, 106, 108, ...) dans un utilisateur (100) du réseau de données (102), les applications accédant à un bus de données (110) de l'utilisateur (100),
    - écriture d'au moins une structure de commande (118) dans une zone d'adresse d'une mémoire de l'utilisateur (100) par une première application par l'intermédiaire du bus de données (110),
    caractérisé par les autres étapes :
    - écriture d'un pointeur (124) sur la zone d'adresse dans le registre d'entrée (126) de l'unité de commande (116) par la première application par l'intermédiaire du bus de données (110),
    - accès de l'unité de commande (116) à la zone d'adresse par l'intermédiaire du bus de données (110) et traitement de la structure de commande (118),
    - écriture du pointeur (124) dans un registre de sortie (136, 130) associé à la première application après le traitement de la structure de commande (118) par l'utilisateur (100).
  2. Procédé selon la revendication 1, dans lequel l'accès au bus de données (110) est régulé par une unité d'arbitrage (112), dans lequel un accès est permis pour un nombre prescrit de cycles de bus et dans lequel le nombre prescrit de cycles de bus est suffisant pour l'écriture du pointeur (124) dans le registre d'entrée (126).
  3. Procédé selon la revendication 1 ou 2, dans lequel la structure de commande (118) contient un champ de confirmation (122), avec les autres étapes suivantes :
    - blocage du registre d'entrée (126) après l'écriture du pointeur (124) par l'utilisateur (100),
    - écriture d'une confirmation dans le champ de confirmation (122) par l'utilisateur (100),
    - déblocage du registre d'entrée (126) par l'utilisateur (100) après la confirmation.
  4. Procédé selon l'une des revendications précédentes 1 à 3, avec les autres étapes suivantes :
    - lecture du registre d'entrée (126) par la première application après l'écriture du pointeur (124),
    - vérification par la première application pour savoir si le registre d'entrée (126) contient le pointeur (124),
    - si ce n'est pas le cas : vérification pour savoir si une confirmation a été mémorisée dans le champ de confirmation (122).
  5. Procédé selon l'une des revendications précédentes 1 à 4, dans lequel la structure de commande (118) contient des instructions exécutables et des données utiles.
  6. Procédé selon l'une des revendications précédentes 1 à 5, dans lequel plusieurs structures de commande qui s'enchaînent sont écrites dans la mémoire par la première application et dans lequel le pointeur (124) pointe sur la zone d'adresse de la première structure de commande (118) de la chaîne.
  7. Programme informatique pour une application (104, 106, 108, ...) d'un utilisateur (100) d'un réseau de données (102), dans lequel l'application peut accéder à un bus de données (110) pour plusieurs applications de l'utilisateur (100) et l'utilisateur (100) comporte un registre d'entrée (126) et un registre de sortie (136, 130) associé à l'application, avec des moyens formant programmes pour la mise en oeuvre des étapes suivantes :
    - écriture d'une structure de commande (118) dans une zone d'adresse d'une mémoire de l'utilisateur (100) par l'intermédiaire du bus de données (110),
    caractérisé par les autres étapes :
    - écriture d'un pointeur (124) sur la zone d'adresse dans le registre d'entrée (126) d'une unité de commande (116) par l'intermédiaire du bus de données (110),
    - lecture du registre d'entrée (126) pour vérifier que la structure de commande (118) a été confirmée par l'unité de commande (116) .
  8. Programme informatique selon la revendication 7, dans lequel une vérification d'un champ de confirmation (122) dans la structure de commande (118) s'effectue lorsque, lors de la lecture du registre d'entrée (126), le pointeur (124) n'est plus dans le registre d'entrée (126).
  9. Programme informatique selon la revendication 7 ou 8, dans lequel plusieurs structures de commande qui s'enchaînent sont écrites dans la mémoire de l'utilisateur (100) et dans lequel le pointeur (124) pointe sur la zone d'adresse de la première structure de commande (118) de la chaîne.
  10. Programme informatique selon la revendication 7, 8 ou 9, dans lequel le registre de sortie (136, 130) associé à l'application est lu pour vérifier si la structure de commande (118) a été traitée par l'unité de commande (116).
  11. Appareil utilisateur (100) d'un réseau de données (102), avec
    - une unité de commande (116) pour l'accès au réseau de données (102),
    - des moyens pour le fonctionnement de plusieurs applications (104, 106, 108, ...), les applications pouvant accéder à un bus de données (110) de l'utilisateur (100), et
    - des moyens pour l'écriture d'au moins une structure de commande (118) dans une zone d'adresse d'une mémoire de l'utilisateur (100) par une première application par l'intermédiaire du bus de données (110),
    caractérisé par :
    - des moyens pour l'écriture d'un pointeur (124) sur la zone d'adresse dans le registre d'entrée (126) de l'unité de commande (116) par la première application par l'intermédiaire du bus de données (110),
    - des moyens pour l'accès de l'unité de commande (116) à la zone d'adresse par l'intermédiaire du bus de données (110) et pour le traitement de la structure de commande (118), et
    - des moyens pour l'écriture du pointeur (124) dans un registre de sortie (136, 130) associé à la première application après le traitement de la structure de commande (118) par l'utilisateur (100).
  12. Appareil utilisateur (100) selon la revendication 11, avec une unité d'arbitrage (112) pour la régulation de l'accès au bus de données (110), un accès étant permis pour un nombre prescrit de cycles de bus et le nombre prescrit de cycles de bus étant suffisant pour l'écriture du pointeur (124) dans le registre d'entrée (126).
  13. Appareil utilisateur (100) selon la revendication 11 ou 12, dans lequel un champ de confirmation (122) est contenu dans la structure de commande (118) et avec
    - des moyens pour le blocage du registre d'entrée (126) après l'écriture du pointeur (124) par l'utilisateur (100) ,
    - des moyens pour l'écriture d'une confirmation dans le champ de confirmation (122) par l'utilisateur (100),
    - des moyens pour le déblocage du registre d'entrée (126) par l'utilisateur (100) après la confirmation.
  14. Appareil utilisateur (100) selon la revendication 11, 12 ou 13, avec
    - des moyens pour la lecture du registre d'entrée (126) par la première application après l'écriture du pointeur (124),
    - des moyens pour la vérification par la première application pour savoir si le registre d'entrée (126) contient le pointeur (124) et, si ce n'est pas le cas, pour la vérification pour savoir si une confirmation a été mémorisée dans le champ de confirmation (122).
  15. Appareil utilisateur (100) selon l'une des revendications précédentes 11 à 14, dans lequel la structure de commande (118) contient des instructions exécutables et des données utiles.
  16. Appareil utilisateur (100) selon l'une des revendications précédentes 11 à 15, avec plusieurs structures de commande qui s'enchaînent dans la mémoire, le pointeur (124) pointant sur la zone d'adresse de la première structure de commande (118) de la chaîne.
  17. Système de communication avec un réseau de données (102) et avec plusieurs appareils utilisateurs selon l'une des revendications précédentes 11 à 16.
EP02774365A 2001-09-26 2002-09-13 Procede pour acceder a une unite de commande pour un reseau de transmission de donnees Expired - Lifetime EP1430690B1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE10147411 2001-09-26
DE10147411 2001-09-26
DE10237350 2002-08-14
DE10237350A DE10237350A1 (de) 2001-09-26 2002-08-14 Verfahren zum Zugriff auf eine Befehlseinheit für ein Datennetz
PCT/DE2002/003444 WO2003028337A2 (fr) 2001-09-26 2002-09-13 Procede pour acceder a une unite de commande pour reseau de transmission de donnees

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EP1430690A2 EP1430690A2 (fr) 2004-06-23
EP1430690B1 true EP1430690B1 (fr) 2006-06-21

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US (1) US20050025139A1 (fr)
EP (1) EP1430690B1 (fr)
CN (1) CN1636373B (fr)
AT (1) ATE331378T1 (fr)
CA (1) CA2461763A1 (fr)
DE (1) DE50207328D1 (fr)
ES (1) ES2266579T3 (fr)
WO (1) WO2003028337A2 (fr)

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JP4806295B2 (ja) * 2006-05-25 2011-11-02 富士通株式会社 通信インターフェース装置及び通信方法
JP4890613B2 (ja) * 2007-06-04 2012-03-07 富士通株式会社 パケットスイッチ装置
US20100145340A1 (en) * 2008-12-05 2010-06-10 Kyphon Sarl Introducer Tool for Bone Measurement
CN108664213B (zh) * 2017-03-31 2024-01-19 北京忆恒创源科技股份有限公司 基于分布式缓存的原子写命令处理方法与固态存储设备
DE102017208831A1 (de) * 2017-05-24 2018-11-29 Wago Verwaltungsgesellschaft Mbh Verarbeitung von Prozessdaten

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US5133062A (en) * 1986-03-06 1992-07-21 Advanced Micro Devices, Inc. RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory
JP2575557B2 (ja) * 1990-11-13 1997-01-29 インターナショナル・ビジネス・マシーンズ・コーポレイション スーパーコンピユータシステム
FR2702578B1 (fr) * 1993-03-12 1995-04-14 Bull Sa Système de communication avec un réseau.
US6467008B1 (en) * 1999-03-01 2002-10-15 Sun Microsystems, Inc. Method and apparatus for indicating an interrupt in a network interface
US7159223B1 (en) * 2000-05-12 2007-01-02 Zw Company, Llc Methods and systems for applications to interact with hardware
KR100716950B1 (ko) * 2000-08-11 2007-05-10 삼성전자주식회사 버스 시스템

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DE50207328D1 (de) 2006-08-03
EP1430690A2 (fr) 2004-06-23
WO2003028337A2 (fr) 2003-04-03
WO2003028337A3 (fr) 2003-08-07
CN1636373B (zh) 2010-06-16
CA2461763A1 (fr) 2003-04-03
ES2266579T3 (es) 2007-03-01
ATE331378T1 (de) 2006-07-15
US20050025139A1 (en) 2005-02-03
CN1636373A (zh) 2005-07-06

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