EP1423773A1 - Improving the timing of and minimising external influences on digital signals - Google Patents

Improving the timing of and minimising external influences on digital signals

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Publication number
EP1423773A1
EP1423773A1 EP02769986A EP02769986A EP1423773A1 EP 1423773 A1 EP1423773 A1 EP 1423773A1 EP 02769986 A EP02769986 A EP 02769986A EP 02769986 A EP02769986 A EP 02769986A EP 1423773 A1 EP1423773 A1 EP 1423773A1
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EP
European Patent Office
Prior art keywords
clock
signals
timing
receiver
digital system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP02769986A
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German (de)
French (fr)
Inventor
Falk HÖHNEL
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Siemens AG
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Siemens AG
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Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to EP02769986A priority Critical patent/EP1423773A1/en
Publication of EP1423773A1 publication Critical patent/EP1423773A1/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Definitions

  • Figure 1 shows the temporal position of a digital signal at the output of the driver of a transmitter and at the input of the receiver, the temporal influence of the factors mentioned being shown.
  • the setuptime requirement states how much ns before the clock edge a signal to be clocked in must be stable.
  • the holdtime requirement states how long the signal must remain stable after a clock edge. So if you change the position of the times of clock and signal to each other, this has a positive effect. sitiv out for one demand, but negative for the other.
  • the signals are very fast.
  • the beat may be not particularly quickly.
  • a holdtime problem arises here.
  • the signals are very slow under extremely unfavorable environmental conditions (temperature high, supply voltage low, driver weak, receiver with large parasitic capacitance).
  • the beat may be not too slow.
  • a setup time problem arises here.
  • the runtime of clock and signals must be optimized so that no timing violations occur anywhere, even in extreme environmental conditions. The compromise determines the maximum possible frequency and thus the performance of the system or forces restrictions in the architecture.
  • a table is created that lists all timing parameters to be observed for each signal and calculates a budget or a violation. This is done for the fast and the slow case.
  • the parameters can be influenced (within limits) by the selection of the components, the board layout and (if the transmitter or receiver are in an ASIC) the ASIC design.
  • the limits result from the selected components (driver strength, setup / hold time from the data sheet), the distances of the components on the board, the architecture of the networks (uni / bidirectional signals, number of drivers / receivers involved) and frequency or Cycle period. Then an optimization is carried out. But if optimization is done for the slow fall, this damages the fast fall and returns
  • Example SDRAM address signals in the PC Here the address signals are sent by the driver and only clocked in at the receiver after the next but one cycle. This has consequences for the design of the SDRAM controller and the performance of the entire system.
  • PC motherboards with SDRAM bus frequency 133MHz are only equipped with a maximum of 3 SDRAM modules (DIMM) in order to avoid timing problems. However, this limits the maximum possible memory expansion.
  • DIMM 3 SDRAM modules
  • a variant of the clock skew between transmitter and receiver that is already partly used uses a PLL in the transmitter module (eg ASIC), see Figure 2.
  • the clock and signals for the SDRAMs come from the same chip.
  • An additional clock output is looped back to the transmitter's PLL, with the same physical length as the receiver clock.
  • the PLL rather sends this feedback clock according to the board running time t_run, so that the feedback clock then arrives in phase with the reference clock clk_ref at the PLL input of the ASIC x s. Because of the same running time of the Reveiver clock, this is also in phase at its receiver at time T0.
  • the invention leads to an approximately constant clock-to-output time for the slow and the fast case.
  • Board layout measures also ensure that the edge spacing of clock and signals on the board is retained and is unchanged at the receiver. This makes it possible to increase the maximum frequency or operate the bus frequency with fewer restrictions.
  • the design risk for timing drops considerably (in Figure 3, arrows indicate that all areas of signals and clock have the same design, including the line lengths and the buffers that determine the clock-to-output time.
  • the clock-to -Output times are therefore independent of environmental influences and also of the manufacturing process of the ASIC.
  • the running times of the signals on the board are also set for equality and are therefore independent of environmental influences).
  • An essential feature of the invention is that
  • Output FFs for this bus should not be clocked with the normal system clock for the core of the ASIC, but with a clock that is derived from the output clock of the PLL (see Figure 3).
  • this clock is rather sent out by the PLL in order to be in phase at the PLL input with the reference clock.
  • the outputs of the signals are weaker and take longer on the board. Therefore it makes sense to send out the signals sooner. This is done automatically by the clocking with the output clock. In the case of a fast fall, the clock and signals are sent out later accordingly.
  • the buffer type and placement of clock and signal output buffers are identical.
  • the clock-to-output distance tco is always the same in both extreme cases.
  • the clock-to-output time can still be minimized by delay elements in the output clock path.
  • the runtimes of the signals are also shown in the board layout those of the clocks and feedback clocks set to equality. All signals on the bus are trimmed to the same length. Therefore, the clock-to-signal distance from the driver module to the receivers remains the same, regardless of the ambient conditions. This reduces several parameters in the timing table: clock-to-output, output skew and runtime skew. In addition, the parameters are ensured in the case of fast or slow fall.
  • the PLL ensures that the rising clock edges on the ASIC and on the DIMMs are in phase without skew at the time TO. With the same beat, the
  • a PLL clock driver and three delay lines can also be seen.
  • the input signals are treated separately.
  • These delay lines are used to independently adjust the timing of the forward and backward direction of bidirectional digital signals.
  • DIMM Dual Inline Memory Module
  • DRAM Dynamic Random Access Memory
  • SDRAM Synchronous Dynamic Random Access Memory
  • DDR SDRAM Double Data Rate Synchronous Random Access Memory
  • Clock skew Time difference that arises due to different durations and / or due to different driver strengths or receiver loads. Caused by clock skew, some receiver registers switch earlier / later than others,
  • Output skew the spread of the tco times for similar signals (buses)
  • input skew the spread of the input transit times from the outer pin to the receiver in the chip for buses

Abstract

The performance of digital signals depends to a great extent on the frequency. However, the higher the frequency, the shorter the remaining time, in which digital signals can be reliably received by a receiver from a driver via a printed conductor. The run time of the clock pulse and signals must be optimised in such a way that no timing losses occur at any location, even in extreme environmental conditions. The invention improves the timing and minimises external influences by coupling the output signals to an internal PLL clock pulse.

Description

Beschreibungdescription
Verbesserung des Timings und Minimierung externer Einflüsse bei digitalen Signalen.Improving the timing and minimizing external influences on digital signals.
1. Welches technische Problem soll durch die Erfindung gelöst werden?1. What technical problem is the invention intended to solve?
2. Wie wurde dieses Problem bisher gelöst? 3. In welcher Weise löst die Erfindung das angegebene technische Problem? 4. Ausführungsbeispiel [e] der Erfindung.2. How has this problem been solved so far? 3. How does the invention solve the stated technical problem? 4. Embodiment [e] of the invention.
Zu 1. Welches technische Problem soll durch die Erfindung gelöst werden?Re 1. What technical problem is the invention intended to solve?
Die Performance digitaler Systeme hängt stark von der Fre- quenz ab. Aber: je höher die Frequenz um so kleiner ist die verbleibende Zeit, um digitale Signale sicher von einem Treiber über eine Leiterbahn bis zu den Empfängern zu bekommen. Begrenzende Faktoren sind die Clock-to-Output Time, die Laufzeit auf dem Board, der Setup/Hold-Time des Empfängers, Out- put und Input Skew (Skew der Sender und Empfänger) sowieThe performance of digital systems depends heavily on the frequency. But: the higher the frequency, the shorter the time remaining to safely receive digital signals from a driver via a conductor track to the receivers. Limiting factors are the clock-to-output time, the runtime on the board, the setup / hold time of the receiver, output and input skew (skew of the transmitter and receiver) and
Clock Skew bzw. Jitter (tskew) .Clock skew or jitter (tskew).
Bild 1 zeigt die zeitliche Lage eines digitalen Signals am Ausgang des Treibers eines Senders und am Eingang des Empfän- gers, wobei der zeitliche Einfluß der genannten Faktoren dargestellt ist.Figure 1 shows the temporal position of a digital signal at the output of the driver of a transmitter and at the input of the receiver, the temporal influence of the factors mentioned being shown.
Die Setuptime-Forderung besagt, wie viel ns vor der Taktflanke ein einzutaktendes Signal stabil sein muss . Die Holdtime- Forderung besagt, wie lange nach einer Taktflanke das Signal noch stabil bleiben muss. Ändert man also die Lage der Zeitpunkte von Takt und Signal zueinander, so wirkt sich dies po- sitiv aus für die eine Forderung, aber negativ für die andere Forderung aus .The setuptime requirement states how much ns before the clock edge a signal to be clocked in must be stable. The holdtime requirement states how long the signal must remain stable after a clock edge. So if you change the position of the times of clock and signal to each other, this has a positive effect. sitiv out for one demand, but negative for the other.
Bei extrem günstigen Umgebungsbedingungen (Temperatur nied- rig, VersorgungsSpannung hoch, Treiber stark, Empfänger mit kleiner parasitärer Kapazität) sind die Signale sehr schnell. Der Takt ist aber u.U. nicht besonders schnell. Hier entsteht ein Holdtime-Problem. Bei extrem ungünstigen Umgebungsbedingungen (Temperatur hoch, VersorgungsSpannung niedrig, Treiber schwach, Empfänger mit großer parasitärer Kapazität) sind die Signale sehr langsam. Der Takt ist aber u.U. nicht auch langsam. Hier entsteht ein Setuptime-Problem. Laufzeit von Clock und Signalen müssen so optimiert werden, dass selbst bei extremen UmgebungsVerhältnissen nirgends Timingverletzungen entstehen. Der Kompromiss bestimmt die maximal mögliche Frequenz und damit die Performance des Systems oder zwingt zu Einschränkungen in der Architektur.In extremely favorable environmental conditions (temperature low, supply voltage high, driver strong, receiver with small parasitic capacitance), the signals are very fast. The beat may be not particularly quickly. A holdtime problem arises here. The signals are very slow under extremely unfavorable environmental conditions (temperature high, supply voltage low, driver weak, receiver with large parasitic capacitance). The beat may be not too slow. A setup time problem arises here. The runtime of clock and signals must be optimized so that no timing violations occur anywhere, even in extreme environmental conditions. The compromise determines the maximum possible frequency and thus the performance of the system or forces restrictions in the architecture.
Zu 2. Wie wurde dieses Problem bisher gelöst?Re 2. How has this problem been solved so far?
Üblicherweise wird eine Tabelle erstellt, die für jedes Sig- nal alle zu beachtenden Timing-Parameter auflistet und ein Budget bzw. eine Verletzung errechnet. Dies wird für den schnellen und den langsamen Fall durchgeführt. Die Parameter können (in Grenzen) beeinflusst werden über die Auswahl der Bauelemente, das Board-Layout und (falls Sender oder Empfän- ger in einem ASIC liegen) über das ASIC-Design. Die Grenzen ergeben sich, durch die ausgewählten Bauelemente (Treiberstärke, Setup/Hold Time vom Datenblatt) , die Entfernungen der Bauelemente auf dem Board, die Architektur der Netze (uni/bidirektionale Signale, Anzahl der beteiligten Trei- ber/Empfänger) und Frequenz bzw. Taktperiode. Dann wird eine Optimierung durchgeführt. Doch wenn für den langsamen Fall optimiert wird, schadet dies dem schnellen Fall und umge- kehrt ,Usually, a table is created that lists all timing parameters to be observed for each signal and calculates a budget or a violation. This is done for the fast and the slow case. The parameters can be influenced (within limits) by the selection of the components, the board layout and (if the transmitter or receiver are in an ASIC) the ASIC design. The limits result from the selected components (driver strength, setup / hold time from the data sheet), the distances of the components on the board, the architecture of the networks (uni / bidirectional signals, number of drivers / receivers involved) and frequency or Cycle period. Then an optimization is carried out. But if optimization is done for the slow fall, this damages the fast fall and returns
Tabelle 1: Setup und Hold Time Margin BerechnungTable 1: Setup and Hold Time Margin calculation
hold margin = tco,min + trun,min - tskew - thold setup margin = 7.5ns - tco,max - trun,max - tsetup - tskewhold margin = tco, min + trun, min - tskew - thold setup margin = 7.5ns - tco, max - trun, max - tsetup - tskew
Teilweise wurde das Problem auch gar nicht gelöst sondern umgangen. Beispiel SDRAM Adress-Signale im PC: Hier werden die Adress-Signale vom Treiber abgesendet und erst mit dem übernächsten Takt am Empfänger eingetaktet. Das hat Konsequenzen für das Design des SDRAM-Controllers und die Performance des gesamten Systems . Außerdem werden PC Motherboards mit SDRAM Busfrequenz 133MHz nur noch mit maximal 3 SDRAM Modulen (DIMM) ausgerüstet, um Timing-Problemen aus dem Weg zu gehen. Dies begrenzt jedoch den maximal möglichen Speicherausbau.Sometimes the problem was not solved at all, but avoided. Example SDRAM address signals in the PC: Here the address signals are sent by the driver and only clocked in at the receiver after the next but one cycle. This has consequences for the design of the SDRAM controller and the performance of the entire system. In addition, PC motherboards with SDRAM bus frequency 133MHz are only equipped with a maximum of 3 SDRAM modules (DIMM) in order to avoid timing problems. However, this limits the maximum possible memory expansion.
Eine bereits teilweise übliche Variante zur Minimierung des Takt-Skews zwischen Sender und Empfänger verwendet eine PLL im Sender-Baustein (z.B.ASIC), siehe Bild 2. Dabei kommen Takt und Signale für die SDRAM' s aus dem selben Chip. Ein zusätzlicher Taktausgang wird wieder zur PLL des Senders zurückgeschleift, und zwar mit der gleichen physikalischen Län- ge, die der Receiver-Clock hat. Die PLL schickt diesen Feedback-Takt entsprechend der Board-Laufzeit t_run eher los, damit der Feedback-Takt dann phasengleich mit dem Referenz-Takt clk_ref am PLL-Eingang des ASICxs eintrifft. Wegen der gleichen Laufzeit des Reveiver-Clocks ist auch dieser an seinem Empfänger zum Zeitpunkt T0 automatisch phasengleich. DerA variant of the clock skew between transmitter and receiver that is already partly used uses a PLL in the transmitter module (eg ASIC), see Figure 2. The clock and signals for the SDRAMs come from the same chip. An additional clock output is looped back to the transmitter's PLL, with the same physical length as the receiver clock. The PLL rather sends this feedback clock according to the board running time t_run, so that the feedback clock then arrives in phase with the reference clock clk_ref at the PLL input of the ASIC x s. Because of the same running time of the Reveiver clock, this is also in phase at its receiver at time T0. The
Clock-Skew zwischen Sender und Empfänger ist somit immer gleich Null . Zu 3. In welcher Weise löst die Erfindung das angegebene technische Problem ?Clock skew between transmitter and receiver is therefore always zero. 3. How does the invention solve the technical problem indicated?
Die Erfindung führt zu einer annähernd konstanten Clock-to- Output Zeit für den langsamen und den schnellen Fall. Durch Board-Layout-Maßnahmen wird außerdem dafür gesorgt, dass der Flankenabstand von Clock und Signalen auf dem Board erhalten bleibt und beim Empfänger unverändert ist. Damit ist eine Erhöhung der maximalen Frequenz bzw. der Betrieb der Busfre- quenz mit weniger Einschränkungen möglich. Das Design-Risko beim Timing sinkt erheblich (In Bild 3 deuten Pfeile an, dass alle Bereiche von Signalen und Takt gleich ausgeführt sind, also auch die Leitungslängen und die Buffer, die die Clock- to-Output-Zeit bestimmen. Die Clock-to-Output-Zeiten sind deshalb unabhängig von Umgebungseinflüssen und auch vom Her- stellungsprozess des ASIC's. Die Laufzeiten der Signale auf dem Board sind auch auf Gleichheit eingestellt und damit unabhängig von Umgebungseinflüssen) .The invention leads to an approximately constant clock-to-output time for the slow and the fast case. Board layout measures also ensure that the edge spacing of clock and signals on the board is retained and is unchanged at the receiver. This makes it possible to increase the maximum frequency or operate the bus frequency with fewer restrictions. The design risk for timing drops considerably (in Figure 3, arrows indicate that all areas of signals and clock have the same design, including the line lengths and the buffers that determine the clock-to-output time. The clock-to -Output times are therefore independent of environmental influences and also of the manufacturing process of the ASIC. The running times of the signals on the board are also set for equality and are therefore independent of environmental influences).
Ein wesentliches Merkmal der Erfindung besteht darin, dieAn essential feature of the invention is that
Output-FF's für diesen Bus nicht mit dem normalen System-Takt für den Core des ASIC's zu takten, sondern mit einem Takt, der vom Ausgangstakt der PLL abgeleitet ist (siehe Bild 3) . Dieser Takt wird ja von der PLL beim langsamen Fall entspre- chend eher losgeschickt, um phasengleich am PLL-Eingang mit dem Referenz-Takt zu sein. Im langsamen Fall sind auch die Outputs der Signale schwächer und brauchen länger auf dem Board. Deshalb ist es sinnvoll, auch die Signale eher loszuschicken. Dies geschieht automatisch durch die Abtaktung mit dem Ausgangstakt. Beim schnellen Fall werden Clock und Signale entsprechend später losgeschickt. Buffertyp und Platzierung von Clock- und Signal-Outputbuffern werden identisch ausgeführt. Der Abstand Clock-to-Output tco ist immer gleich in beiden Extremfällen. Durch Delay-Glieder im Output-Clock- Pfad kann die Clock-to-Output-Zeit noch minimiert werden.Output FFs for this bus should not be clocked with the normal system clock for the core of the ASIC, but with a clock that is derived from the output clock of the PLL (see Figure 3). In the slow case, this clock is rather sent out by the PLL in order to be in phase at the PLL input with the reference clock. In the slow case, the outputs of the signals are weaker and take longer on the board. Therefore it makes sense to send out the signals sooner. This is done automatically by the clocking with the output clock. In the case of a fast fall, the clock and signals are sent out later accordingly. The buffer type and placement of clock and signal output buffers are identical. The clock-to-output distance tco is always the same in both extreme cases. The clock-to-output time can still be minimized by delay elements in the output clock path.
Im Board-Layout werden auch die Laufzeiten der Signale mit denen der Clocks und Feedback-Clocks auf Gleichheit eingestellt. Alle Signale des Busses werden auf Gleichlänge getrimmt. Deshalb bleibt der Clock-to-Signal Abstand vom Treiberbaustein bis zu den Empfängern gleich, unabhängig von den Umgebungsbedingungen. Damit werden gleich mehrere Parameter in der Timing-Tabelle reduziert: Clock-to-Output, Output Skew und Laufzeit Skew. Außerdem wird für Gleichheit der Parameter beim schnellen bzw. langsamen Fall gesorgt.The runtimes of the signals are also shown in the board layout those of the clocks and feedback clocks set to equality. All signals on the bus are trimmed to the same length. Therefore, the clock-to-signal distance from the driver module to the receivers remains the same, regardless of the ambient conditions. This reduces several parameters in the timing table: clock-to-output, output skew and runtime skew. In addition, the parameters are ensured in the case of fast or slow fall.
Zu 4. Ausführungsbeispiel [e] der Erfindung.Regarding the fourth embodiment of the invention.
Das vorgestellte Prinzip ist beispielhaft verwirklicht bei einer SDRAM-Speicheransteuerung mit einem ASIC, 4x512MB SDRAM DIMM's und einem Clock-Multiplier für 133 MHz, siehe Bild 4.The principle presented is implemented as an example for an SDRAM memory controller with an ASIC, 4x512MB SDRAM DIMMs and a clock multiplier for 133 MHz, see Figure 4.
Die PLL sorgt dafür, dass zum Zeitpunkt TO die steigenden Taktflanken sowohl am ASIC als auch an den DIMM's phasen- gleich ohne Skew sind. Mit dem gleichen Takt werden auch dieThe PLL ensures that the rising clock edges on the ASIC and on the DIMMs are in phase without skew at the time TO. With the same beat, the
Signale losgeschickt, bezogen auf den Clock-Ausgang mit tco. Wenn die Laufzeiten von Takt und Signalen im Layout auf Gleichheit eingestellt werden, so ist der Abstand zwischen Takt und Signalen immer noch genau Tco. Dies gilt unabhängig davon, ob Umgebungsfaktoren und ASIC-Prozessfaktoren beschleunigend oder verlangsamend wirken. Ungenauigkeiten entstehen durch Laufzeitunterschiede, Output-Skew, Board-Skew, DIMM-Skew sowie DIMM-Clock-Skew und sind auf herkömmliche Weise einzurechnen.Signals sent, related to the clock output with tco. If the run times of clock and signals in the layout are set to be equal, the distance between clock and signals is still exactly Tco. This applies regardless of whether environmental factors and ASIC process factors are accelerating or slowing down. Inaccuracies arise from runtime differences, output skew, board skew, DIMM skew and DIMM clock skew and are to be included in the conventional way.
Bei diesem Ausführungsbeispiel sind noch zusätzlich ein PLL Clock driver und drei Delaylines zu erkennen. Ausserdem sind die Eingangssignale gesondert behandelt. Diese Delaylines dienen der unabhängigen Einstellbarkeit des Timing von Hin- und Rückrichtung bidirektionaler digitaler Signale beschrieben. Mit Nutzung .der beschriebenen Erfindung ist es möglich trotz der besonderen, in der PC-Welt nicht vorhandenen Forderungen (4 DIMM-Steckplätze mit schrägen Sockeln wegen niedriger Board-Aufbauhöhe 3cm, Adress-Signale liegen nur einen Takt an) , einen Bustakt von 133MHz bei sicherem Timing ohne Performance-Einbußen für das System zu verwirklichen.In this exemplary embodiment, a PLL clock driver and three delay lines can also be seen. In addition, the input signals are treated separately. These delay lines are used to independently adjust the timing of the forward and backward direction of bidirectional digital signals. Using the described invention, it is possible, despite the special requirements that do not exist in the PC world (4 DIMM slots with inclined sockets due to the low board height of 3 cm, address signals are only present in one cycle), a bus cycle of 133 MHz with reliable timing without sacrificing performance for the system.
Abschließend folgt eine beispielhafte Erläuterung hinsichtlich des notwendigen Abstandes zwischen Clock und Signal bei Sender und Empfänger: a) Annahme: Sender und Empfänger erhalten von extern phasengleiche Clocks. Der Sender hat eine bestimmte Clock-to- Output-Zeit tco. Der Empfänger verlangt eine bestimmte Hold-Zeit thd (nach der Taktflanke muss das Signal noch ei- ne bestimmte Zeit thd stabil gehalten werden, damit der Lo- ■ giklevel sicher erkannt wird) . b) einfachste Lösung, falls tco > thd: Selbst wenn gar keine Laufzeit auf dem Board wäre, so wäre doch die Holdtime erfüllt. c) Falls tco < thd: Die Board-Laufzeit sorgt für eine Verzögerung des Signals, so dass die Holdtime dennoch erfüllt ist. d) Die Board-Laufzeit ist sehr lang (große Entfernung) und die Taktperiode sehr kurz (hohe Frequenz) : Die Board-Laufzeit verzögert die Signalflanke so stark, dass die Setuptime tsu des Empfängers nicht eingehalten wird. Dann wird das Signal eventuell noch mit dem vergangenen Logik-Level abgetastet! Dieser Fall wäre bei 133MHz und 10cm Abstand und großer ka- papazitiver Last bei mehreren Empfängern normal. Darum werden die Signale mit. tco an den Takt gekoppelt und beide zu- sammen losgeschickt. Wegen der Gleichlängen auf dem Board wird der Abstand tco bis zum Empfänger beibehalten und erfüllt dort die Holdtime wie bei b) . Die SPLL sorgt dafür, dass um genau soviel voreilend ausgetaktet wird, wie nötig, e) In der Realisierung zeigte sich sogar, dass tco < thd war. Dies kann mit der Board-PLL und Delayl (siehe Bild 4) zu- rechtgeschoben werden. Verwendete AbkürzungenIn conclusion, there follows an exemplary explanation with regard to the necessary distance between clock and signal at the transmitter and receiver: a) Assumption: The transmitter and receiver receive externally in-phase clocks. The transmitter has a specific clock-to-output time tco. The receiver requests a certain hold time thd (after the clock edge, the signal must be kept stable for a certain time thd so that the logic ■ level is reliably recognized). b) simplest solution, if tco> thd: Even if there was no runtime on the board, the holdtime would still be fulfilled. c) If tco <thd: The board runtime delays the signal so that the holdtime is still fulfilled. d) The board running time is very long (long distance) and the clock period is very short (high frequency): The board running time delays the signal edge so much that the setuptime tsu of the receiver is not observed. Then the signal may still be sampled with the past logic level! This would be normal with 133MHz and 10cm distance and large capacitive load with several receivers. That is why the signals are included. tco coupled to the clock and sent both together. Because of the equal lengths on the board, the distance tco to the receiver is maintained and fulfills the holdtime there as in b). The SPLL ensures that the clock is clocked out by exactly as much as necessary. E) In the implementation, it was even shown that tco <thd. This can be justified with the Board PLL and Delayl (see Figure 4). used abbreviations
DIMM: Dual Inline Memory ModuleDIMM: Dual Inline Memory Module
DRAM: Dynamic Random Access MemoryDRAM: Dynamic Random Access Memory
SDRAM: Synchronous Dynamic Random Access MemorySDRAM: Synchronous Dynamic Random Access Memory
DDR SDRAM: Double Data Rate Synchronous Random Access Me- moryDDR SDRAM: Double Data Rate Synchronous Random Access Memory
PLL: Phase Locked LoopPLL: Phase Locked Loop
SPLL: PLL for SDRAMSPLL: PLL for SDRAM
Skew: (wörtlich übersetzt) Schiefläge, VerzerrungSkew: (literally translated) imbalance, distortion
Takt-Skew: Zeitdifferenz, die durch verschieden lange Laufzeiten und/oder durch verschienene Treiberstärken oder Empfängerlasten entsteht. Hervorgerufen durch Takt-Skew, schalten einige Empfänger-Register eher/später als andere,Clock skew: Time difference that arises due to different durations and / or due to different driver strengths or receiver loads. Caused by clock skew, some receiver registers switch earlier / later than others,
Output-Skew: die Streubreite der tco Zeiten bei gleichartigen zusammengehörigen Signalen (Bussen) , Input Skew: die Streubreite der Input-Laufzeiten vom äußeren Pin zum Empfänger im Chip bei Bussen Output skew: the spread of the tco times for similar signals (buses), input skew: the spread of the input transit times from the outer pin to the receiver in the chip for buses

Claims

Patentansprüche claims
1. Digitales System, mit1. Digital system, with
- einer Bearbeitungs-Einrichtung (Core) zur Bearbeitung von Daten, die über ein erstes Taktsignal getaktet wird, einem Datenausgangs-Register zum Senden von Daten über eine Signalleitung zu einem weiteren digitalen System, einer PLL-Einrichtung, die aus dem genannten ersten Takt- signal ein zweites Taktsignal erzeugt, welches über eine Taktleitung dem genannten weiteren digitalen System als Taktsignal zugeführt ist, wobei die Rückführungsschleife der PLL-Einrichtung die gleiche Laufzeit wie die genannte Signalleitung aufweist, dadurch gekennzeichnet, daß - das zweite Taktsignal dem Datenausgangs-Register als Taktsignal zugeführt ist, die genannte Taktleitung die gleiche Laufzeit wie die genannte Signalleitung aufweist.a processing device (core) for processing data which is clocked via a first clock signal, a data output register for sending data via a signal line to a further digital system, a PLL device which consists of the first clock signal generates a second clock signal, which is supplied via a clock line to said further digital system as a clock signal, the feedback loop of the PLL device having the same runtime as said signal line, characterized in that - the second clock signal to the data output register as a clock signal is supplied, said clock line has the same transit time as said signal line.
2. Digitales System nach Anspruch 1, dadurch geke nzeichnet, daß die Laufzeiten innerhalb des digitalen Systems und die Buffertypen von Taktsignalen und Datensignalen gleich gehalten sind.2. Digital system according to claim 1, characterized in that the transit times within the digital system and the buffer types of clock signals and data signals are kept the same.
3. Digitales System nach Anspruch 1 oder 2, dadurch geke nzeichnet, daß die genannte Gleichheit der Laufzeiten durch eine entsprechende Dimensionierung der physikalischen Länge der jeweili- gen Leitungen und/oder die Verwendung von mindestens einer3. Digital system according to claim 1 or 2, characterized in that said equality of the transit times by appropriate dimensioning of the physical length of the respective lines and / or the use of at least one
Verzögerungseinrichtung erreicht wird. Delay device is reached.
EP02769986A 2001-09-06 2002-08-30 Improving the timing of and minimising external influences on digital signals Withdrawn EP1423773A1 (en)

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EP01121403 2001-09-06
EP01121403 2001-09-06
PCT/EP2002/009693 WO2003023579A1 (en) 2001-09-06 2002-08-30 Improving the timing of and minimising external influences on digital signals
EP02769986A EP1423773A1 (en) 2001-09-06 2002-08-30 Improving the timing of and minimising external influences on digital signals

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US20040232958A1 (en) 2004-11-25

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