DE10164917B4 - Semiconductor memory system - Google Patents
Semiconductor memory system Download PDFInfo
- Publication number
- DE10164917B4 DE10164917B4 DE10164917.7A DE10164917A DE10164917B4 DE 10164917 B4 DE10164917 B4 DE 10164917B4 DE 10164917 A DE10164917 A DE 10164917A DE 10164917 B4 DE10164917 B4 DE 10164917B4
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- Germany
- Prior art keywords
- clock signal
- signal
- bus
- memory
- memory module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4082—Address Buffers; level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Abstract
Halbleiterspeichersystem mit
– einer Mehrzahl von Busleitungen, die wenigstens ein Taktsignal (CLK1, CLK2) sowie ein Adresssignal und ein Befehlssignal übertragen, und
– einem Speichermodul (700, 700'), das mit den mehreren Busleitungen verbunden ist, die ein erstes Taktsignal (CLK1) und ein zweites Taktsignal (CLK2) übertragen, wobei die Frequenz des ersten Taktsignals niedriger als die Frequenz des zweiten Taktsignals ist,
– wobei das Speichermodul ein Register (710), das mit dem Bus des ersten Taktsignals, dem Bus des Adresssignals und dem Bus des Befehlssignals verbunden ist und das Adresssignal und das Befehlssignal unter der Zeitsteuerung des ersten Taktsignals speichert, und mehrere Speicherchips (701 bis 706) aufweist, von denen jeder mit der Busleitung des zweiten Taktsignals verbunden ist und das Adresssignal und das Befehlssignal, die im Register gespeichert sind, unter der Zeitsteuerung des zweiten Taktsignals empfängt, wobei das Adresssignal und das Befehlssignal zu den Speicherchips in eine Richtung des Speichermoduls oder in zwei Richtungen von einem Mittenbereich des Speichermoduls aus übertragen werden.Semiconductor memory system with
A plurality of bus lines transmitting at least one clock signal (CLK1, CLK2) and an address signal and a command signal, and
A memory module (700, 700 ') connected to the plurality of bus lines carrying a first clock signal (CLK1) and a second clock signal (CLK2), the frequency of the first clock signal being lower than the frequency of the second clock signal,
- wherein the memory module is a register (710) connected to the bus of the first clock signal, the bus of the address signal and the bus of the command signal and stores the address signal and the command signal under the timing of the first clock signal, and a plurality of memory chips (701 to 706 ), each of which is connected to the bus line of the second clock signal and receives the address signal and the command signal stored in the register under the timing of the second clock signal, the address signal and the command signal to the memory chips in a direction of the memory module or in two directions from a central area of the memory module.
Description
Die Erfindung bezieht sich auf ein Halbleiterspeichersystem mit einer Mehrzahl von Busleitungen und einem damit verbundenen Speichermodul.The invention relates to a semiconductor memory system having a plurality of bus lines and a memory module connected thereto.
Der wachsende Bedarf an Computersystemen, die in der Lage sind, große Datenmengen mit hoher Geschwindigkeit zu verarbeiten, hat in der fortgesetzten Entwicklung von hocheffizienten Mikrocontrollern und Zentralprozessoreinheiten (CPUs) resultiert, bei denen der Trend zum Betrieb bei immer höheren Systemtaktfrequenzen geht. Die Verwendung höherer Systemtaktfrequenzen erfordert unter anderem ein Anwachsen der Datenkapazität und Übertragungsgeschwindigkeit eines mit der CPU in Verbindung stehenden Datenspeichers. Mit anderen Worten ist der Speicher so zu konfigurieren, dass er synchron zu den höherfrequenten Systemtaktsignalen arbeitet.The growing demand for computer systems capable of handling large amounts of data at high speed has resulted in the continued development of high-efficiency microcontrollers and central processing unit (CPU) systems, which are becoming the trend for operation at ever-higher system clock frequencies. The use of higher system clock frequencies requires, among other things, an increase in the data capacity and transmission speed of a data memory associated with the CPU. In other words, the memory is to be configured to operate in synchronism with the higher frequency system clock signals.
Das Taktsignal CLK wird den Speicherchips
Wie aus
Wie oben angedeutet, sind Hochgeschwindigkeits-CPUs von Hochfrequenz-Taktsignalen CLK begleitet. Allgemein können die Daten DATA des Datenbusses deshalb bei so hohen Frequenzen operieren, weil die Last jeder Datenleitung relativ gering ist (entsprechend einem Speicherchip). Andererseits können die relativ hohen Mehrspeicherchip-Lasten der Adressbus- und Befehlsbusleitungen einen Hochfrequenzbetrieb dieser Leitungen verhindern. Die Belastungen der Adressbus- und Befehlsbusleitungen können daher die effektive Betriebsgeschwindigkeit des Speichers auf weniger als die Systemtaktgeschwindigkeit begrenzen.As indicated above, high speed CPUs are accompanied by high frequency clock signals CLK. In general, the data DATA of the data bus can therefore operate at such high frequencies because the load of each data line is relatively low (corresponding to a memory chip). On the other hand, the relatively high multicast chip loads of the address bus and command bus lines can prevent high frequency operation of these lines. The stresses on the address bus and command buses may therefore limit the effective operating speed of the memory to less than the system clock speed.
Der PLL
Da das Speichermodul
In der Offenlegungsschrift
Der Erfindung liegt als technisches Problem die Bereitstellung eines Halbleiterspeichersystems zugrunde, mit dem sich arbeitsfähige Frequenzen für ein Adresssignal und ein Befehlssignal selbst bei einer Steigerung der Systemtaktsignalfrequenz verwenden lassen und bei denen ein Taktsignal mit ausreichend niedriger Frequenz geeignet für den Betrieb eines Registers verwendbar ist, selbst wenn die Frequenz eines Systemtaktsignals gesteigert wird.The invention is based on the technical problem of providing a semiconductor memory system which can use operable frequencies for an address signal and a command signal even with an increase in the system clock signal frequency and in which a clock signal of sufficiently low frequency is suitable for the operation of a register itself when the frequency of a system clock signal is increased.
Die Erfindung löst dieses Problem durch die Bereitstellung eines Halbleiterspeichersystems mit den Merkmalen des Anspruchs 1, 2, oder 3.The invention solves this problem by providing a semiconductor memory system having the features of
Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen angegeben.Advantageous developments of the invention are specified in the subclaims.
Vorteilhafte, nachfolgend beschriebene Ausführungsformen der Erfindung sowie das zu deren besserem Verständnis oben erläuterte, herkömmliche Ausführungsbeispiel sind in den Zeichnungen dargestellt, in denen zeigen:Advantageous embodiments of the invention described below and the conventional embodiment explained above for better understanding thereof are shown in the drawings, in which:
Die Frequenz des ersten internen Taktsignals CLK1 kann relativ zur Frequenz des zweiten internen Taktsignals CLK2 in Abhängigkeit von dem Steuersignal CTRL variieren. Nachfolgend wird der Fall beschrieben, dass die Frequenz des ersten internen Taktsignals CLK1 niedriger als diejenige des zweiten internen Taktsignals CLK2 ist. In diesem Fall entspricht die Frequenz des zweiten internen Taktsignals CLK2 im wesentlichen derjenigen des externen Taktsignals CLK. Bei einer angenommenen Frequenz des externen Taktsignals CLK von 400 MHz besitzt dann auch das zweite interne Taktsignal CLK2 eine Frequenz von 400 MHz. Das erste interne Taktsignal CLK1 kann beispielsweise eine Frequenz aufweisen, die halb so groß wie diejenige des zweiten internen Taktsignals CLK2 oder niedriger ist. Wieder angenommen, dass die Frequenz des zweiten internen Taktsignals CLK2 400 MHz beträgt, besitzt dann das erste interne Taktsignal CLK1 eine Frequenz von 200 MHz oder 100 MHz.The frequency of the first internal clock signal CLK1 may vary relative to the frequency of the second internal clock signal CLK2 in response to the control signal CTRL. The following describes the case where the frequency of the first internal clock signal CLK1 is lower than that of the second internal clock signal CLK2. In this case, the frequency of the second internal clock signal CLK2 substantially corresponds to that of the external clock signal CLK. For an assumed Frequency of the external clock signal CLK of 400 MHz then has the second internal clock signal CLK2 a frequency of 400 MHz. For example, the first internal clock signal CLK1 may have a frequency that is half that of the second internal clock signal CLK2 or lower. Again, assuming that the frequency of the second internal clock signal CLK2 is 400 MHz, then the first internal clock signal CLK1 has a frequency of 200 MHz or 100 MHz.
Der Adresspuffer
Im Betrieb empfängt das Halbleiterspeicherbauelement
Im Unterschied dazu werden das Adresssignal ADDR und das Befehlssignal CMD synchron mit dem ersten internen Taktsignal CLK1 verarbeitet, dessen Frequenz niedriger als diejenige des externen Taktsignals CLK ist. Auf diese Weise können die Hochfrequenz-Bauelementbeschränkungen überwunden werden, die bislang durch die Last der Adressbusleitung und der Befehlsbusleitung bedingt waren, was das Halbleiterspeicherbauelement
Ein Datenabtastsignal STROBE kann an den Datenpuffer
In Fällen, in denen der im Speicherchip des ersten oder zweiten Ausführungsbeispiels enthaltene Datenpuffer zum Empfang eines Datenabtastsignals STROBE angeschlossen ist, erfolgt das Eingeben/Ausgeben der Daten sowohl an der ansteigenden als auch der fallenden Flanke des Datenabtastsignals STROBE, wie in
Die Speicherchips
Die in den
Im Unterschied zum herkömmlichen Speichermodul, das ein einzelnes Taktsignal empfängt und selbiges über das Speichermodul hinweg verteilt, empfängt das erfindungsgemäße Speichermodul zwei Taktsignale CLK1 und CLK2 und führt selbige Bauelementen zu, die bei unterschiedlichen Frequenzen arbeiten, d. h. dem Register einerseits und den Speicherchips andererseits. Das Speichermodul beinhaltet daher zwei Modulanschlüsse, die zum Empfangen der zwei Taktsignale CLK1 und CLK2 benutzt werden. In den Speichermodulen
In den Speichermodulen
Die Erfindung umfasst auch Ausführungsformen, bei denen das Speichermodul so konfiguriert ist, dass es nicht nur zwei Taktsignale CLK1, CLK2, sondern mehr als zwei Taktsignale unterschiedlicher Betriebsfrequenzen empfängt, die dann zu verschiedenen Bauelementen geführt werden, welche bei unterschiedlichen Frequenzen arbeiten.The invention also includes embodiments in which the memory module is configured to receive not only two clock signals CLK1, CLK2, but more than two clock signals of different operating frequencies, which are then routed to various devices operating at different frequencies.
Claims (5)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2000-52377 | 2000-09-05 | ||
KR20000052377 | 2000-09-05 | ||
KR2000-79186 | 2000-12-20 | ||
KR10-2000-0079186A KR100396885B1 (en) | 2000-09-05 | 2000-12-20 | Semiconductor memory device lowering high frequency system clock signal for the use of operation frequency of address and command and receiving different frequency clock signals, memory module and system having the same |
Publications (1)
Publication Number | Publication Date |
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DE10164917B4 true DE10164917B4 (en) | 2014-01-23 |
Family
ID=19687420
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Application Number | Title | Priority Date | Filing Date |
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DE10164917.7A Expired - Fee Related DE10164917B4 (en) | 2000-09-05 | 2001-09-05 | Semiconductor memory system |
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KR (1) | KR100396885B1 (en) |
DE (1) | DE10164917B4 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100732280B1 (en) * | 2001-06-27 | 2007-06-25 | 주식회사 하이닉스반도체 | Memory system |
JP4812976B2 (en) * | 2001-07-30 | 2011-11-09 | エルピーダメモリ株式会社 | Register, memory module and memory system |
KR100546097B1 (en) * | 2001-11-21 | 2006-01-24 | 주식회사 하이닉스반도체 | Control and Address Clock Non-Distributed Memory System |
KR100588593B1 (en) * | 2005-06-09 | 2006-06-14 | 삼성전자주식회사 | Registered memory module and control method therefor |
KR100812600B1 (en) * | 2005-09-29 | 2008-03-13 | 주식회사 하이닉스반도체 | Semiconductor memory device using various clock-signals of different frequency |
KR100888597B1 (en) | 2006-09-20 | 2009-03-16 | 삼성전자주식회사 | Apparatus and methods for controlling memory interface |
KR101944964B1 (en) * | 2012-01-13 | 2019-02-01 | 삼성전자주식회사 | Semiconductor memory device and memory system including the same |
US10467158B2 (en) | 2017-11-29 | 2019-11-05 | Micron Technology, Inc. | Apparatuses and methods including memory commands for semiconductor memories |
KR20220087231A (en) | 2020-12-17 | 2022-06-24 | 삼성전자주식회사 | Apparatus, memory controller, memory device, memory system and method for clock switching and low power consumption |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999030240A1 (en) * | 1997-12-05 | 1999-06-17 | Intel Corporation | Memory system including a memory module having a memory module controller |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6265298A (en) * | 1985-09-17 | 1987-03-24 | Fujitsu Ltd | Write system of eprom |
JP3078934B2 (en) * | 1992-12-28 | 2000-08-21 | 富士通株式会社 | Synchronous random access memory |
JP3277603B2 (en) * | 1993-05-19 | 2002-04-22 | 富士通株式会社 | Semiconductor storage device |
JPH08212784A (en) * | 1995-02-03 | 1996-08-20 | Hitachi Ltd | Multiport memory device |
JPH10199240A (en) * | 1996-12-26 | 1998-07-31 | Digital Electron Corp | Synchronous memory device |
JPH10208470A (en) * | 1997-01-17 | 1998-08-07 | Nec Corp | Synchronous semiconductor memory device |
JPH10247388A (en) * | 1997-03-05 | 1998-09-14 | Toshiba Corp | Storage device |
JPH11321400A (en) * | 1998-05-12 | 1999-11-24 | Ts Tech Co Ltd | Seat adjuster |
KR20010001968A (en) * | 1999-06-10 | 2001-01-05 | 윤종용 | Address buffer of semiconductor memory device |
-
2000
- 2000-12-20 KR KR10-2000-0079186A patent/KR100396885B1/en not_active IP Right Cessation
-
2001
- 2001-09-05 DE DE10164917.7A patent/DE10164917B4/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999030240A1 (en) * | 1997-12-05 | 1999-06-17 | Intel Corporation | Memory system including a memory module having a memory module controller |
Also Published As
Publication number | Publication date |
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KR20020019375A (en) | 2002-03-12 |
KR100396885B1 (en) | 2003-09-02 |
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