EP1421510A2

EP1421510A2 - Universal computer architecture

Info

Publication number: EP1421510A2
Application number: EP02747353A
Authority: EP
Inventors: Robert Newberry
Original assignee: DaimlerChrysler AG
Current assignee: OL Security LLC
Priority date: 2001-08-11
Filing date: 2002-06-07
Publication date: 2004-05-26
Also published as: USRE43619E1; US7103429B2; WO2003014959A3; US20040225415A1; JP4209771B2; JP2005502942A; WO2003014959A2; DE10139610A1

Abstract

A universal computer for a transport means, comprising a microprocessor (1) for the processing of control programmes, a storage means (3), for the data thus calculated and an interface (17) which permits a connection of the computer to a databus in the transport means. The computer comprises control programmes for controlling devices provided in the transport means, whereby the control commands are transmitted to the device to be controlled by means of device interfaces (15, 16). The computer also comprises reconfigurable hardware (2), which permits a retroactive reconfiguration of peripheral components or an interface in the assembled state of the computer. Transmission means (20, 22) are provided which transmit an algorithm for reconfiguration of the hardware to the storage means on the transport means, so that a process for reconfiguration of the hardware associated with the peripheral components or the interface may be carried out.

Description

Universal computer architecture

The invention relates to a universal computer for a means of transport with a microprocessor for processing control programs, a storage means for the data calculated thereby and an interface which allows the computer to be connected to a data bus in the means of transport, the computer providing control programs for controlling means of transport Devices and device interfaces via which the control commands are transmitted to the device to be controlled.

DE 197 48 536 C2 shows a computer for a means of transport which is provided with a microprocessor, various storage means and an interface which enables a connection to the CAN bus. Control devices of this type also regularly have device interfaces via which devices, for example a mobile telephone or a navigation device, can be coupled to the device interface.

A disadvantage of the conventional control devices is that these computers remain installed in the vehicle for the entire life of the vehicle, so that the hardware of the computers is predetermined. A subsequent replacement of the hardware in a vehicle in use is not feasible in today's networked systems with up to 60 computers in the vehicle due to the high configuration effort. As a result, the only consideration hitherto has been to replace various software modules during the life of the vehicle, so that the software is adapted to the changing circumstances.

There is now a need to make parts of the hardware flexibly adaptable. Especially in the telecommunications market, for example for mobile telephones, the housing and interface versions of the devices change within a short time. This means that it is hardly possible to subsequently connect a more modern mobile phone and connect it to a control unit in the vehicle.

DE 197 50 662 AI discloses a processor unit for a data processing-based electronic control system in a motor vehicle. The computer shown there provides a scalable computing unit, i.e. a hardware that is designed according to the performance requirements with different processor performance, and is interchangeable with a faster or slower microprocessor as required. If higher processing power is required in a computer, the microprocessor can then be replaced by a more powerful one, the scalable processor being insertable into the same processor bar. However, the hardware is replaced as a whole. This is possible when the control units are opened, the hardware is replaced and the software programs are loaded accordingly.

So-called field programmable gate arrays (FPGA) are known as reconfigurable hardware, for which reference is made merely by way of example to US 5457410, US 6014509 and WO 95/28769. FPGAs of this type have memory cells, such as flip-flops, which can still change their function even after manufacture. These memory cells can be freely configured with one another, with electrically conductive connections being re-wired so that various logic circuits can be set up as a result. Logical circuits can be simulated by means of such FPGAs, in particular electrical filters can be built up or they can simply be used as storage means.

It is an object of the present invention to provide a universal computer for a means of transport which is suitable for use with a data bus and other suitable control device that can be set within the vehicle and without changing the hardware to new interface requirements or subsequently exchangeable devices.

This object is achieved by the features of claim 1. The computer then has reconfigurable hardware which, when the computer is installed, permits subsequent reconfiguration of peripheral components or an interface, and a transmission means is provided which transfers an algorithm for reconfiguring the hardware to the storage means in the means of transport, so that a Process for reconfiguring the hardware relating to the peripheral components or the interface can be carried out.

The computer according to the present invention is installed in the form of a control unit in vehicle manufacture in the means of transport and forms a network within the means of transport together with other control units. The various control devices communicate with one another via the data bus, and control programs are provided in order to control devices that can be coupled to the network via device interfaces.

According to the invention, it is provided to use reconfigurable hardware which can be reconfigured by downloading an algorithm even years after delivery of the vehicle to the customer. The algorithm can be a hardware description language that describes the configuration of the hardware concerned. The reconfigurable hardware is used in particular for all interfaces and peripheral components that are particularly often affected by hardware changes. Peripheral components are understood to mean interrupt controllers, logic modules and circuits as well as filters and output stage control circuits which control connected devices. It also includes interface drivers, addressing components, devices for data bus Controller or logical units for memory control. The microcomputer itself can also be simulated by an FPGA module.

For example, a central vehicle display is arranged in the vehicle interior, which can be controlled via a control device. Various telematics devices, for example a mobile telephone, a navigation system or various audio or video devices, are connected to the network in the means of transport via a device interface. If an additional device is now connected to the network or a control device or an older device is replaced by a device according to the new standard, the necessary driver software is transferred from an external means of transfer to a storage means in the computer. On the other hand, the reconfigurable hardware can also be used to change the wiring between the device interface and the computer using an algorithm for reconfiguring the hardware, so that the entire device interface does not have to be replaced as usual, but the hardware is reconfigured. Furthermore, various digital filters and logic circuits can be reconfigured or re-wired by transferring an algorithm for reconfiguration from a service center to the storage means of the computer.

The advantage of this new universal computer architecture is that certain hardware elements can be reconfigured so that logical standard elements and their wiring can be changed or re-connected later. In this way, hardware will no longer have to be replaced in the future when new devices are retrofitted in the vehicle, but the hardware can be adapted accordingly using an algorithm for reconfiguring the hardware. In this way, new hardware does not have to be provided for every device change, but can be adapted via the reconfigurable hardware when using new devices. On the other hand, the long- lively computer architecture can be adapted to new circumstances in terms of its functionality.

The reconfigurable hardware preferably has freely connectable memory cells with reconfigurable electrical connections, which can be reconnected in accordance with the algorithm for reconfiguring the hardware when the computer is installed. The reconfigurable hardware can be a so-called field programmable gate array (FPGA). FPGA types of this type can either be ROM-based, information being retained in the event of a power failure and the hardware being changeable by UV light or electronic processes, or it can be RAM-based FPGAs, the information of which is lost in the event of a power failure. Such FPGAs can be reprogrammed accordingly using an algorithm, for example a set of instructions for programming digital, logic functions. FPGAs can also be used as state machines. The signals assume various predefined states, as is still implemented today in the form of state machines.

In a preferred development of the invention, the microprocessor of the computer has standard cell blocks (SCB), the microprocessor being constructed from various predetermined logical blocks, so that logical components from different electronics manufacturers can be combined in one microprocessor and in the form of a so-called user-specific module ( ASIC) can be implemented. The invention then combines the advantages of a standard cell block microprocessor core with reprogrammable hardware, the software and algorithms for reconfiguring the hardware being transferable to a memory means of the computer via a wireless interface. On the basis of the information transmitted by a service center via the wireless interface, the universal computer can then reconfigure itself in terms of hardware in accordance with the algorithms and thereby adapt to new external devices or further hardware requirements. In another development of the invention, a memory control means is provided which automatically transfers the algorithm for reconfiguring the hardware to the storage means in the means of transport without burdening the processor time of the microprocessor. If required, the memory control means, triggered by a service center or the microprocessor, can request the transmission of the algorithms for the reconfiguration of the hardware and then store the result data, for example, in a so-called flash memory. The wireless interface via which the data can be transmitted to the computer can be implemented, for example, in a GSM standard or in accordance with the Bluetooth standard. The memory control means according to the present invention thus relieves the computer which is in operation of control programs and transfers the algorithms for reconfiguring the hardware into a flash memory independently of the microprocessor. A flash memory is suitable for long-term storage of data that can be transferred from a service center to the means of transport. By transferring the reconfiguration algorithms via a wireless interface and reading the data and algorithms into the flash memory, a highly flexible and effective computer architecture is created that allows the hardware to be reconfigured later.

Since the microcomputer is preferably made up of standard cell blocks, the hardware structures can be modularized and also easily transferred to a reconfigurable hardware (FPGA). Such standard cell blocks are then saved in the microcomputer hardware and programmed in the form of FPGAs using the algorithms for reconfiguration. The standard cell blocks can also be provided within the microprocessor, which can then be variably wired to a device interface via the reconfigurable hardware. On the other hand, the reconfigurable hardware can also be arranged as a peripheral device next to the microprocessor be and carry out the wiring and processing of the electrical signals.

In addition to the data transfer control, the memory control means can also be responsible for data security. All data that are transmitted to the computer via the interfaces, for example the device interfaces or the interface for transmitting the algorithm for reconfiguration, can run for this purpose via the memory control means. The memory control means then checks a special activation number or private and public keys in accordance with an encryption method and only if the verification is positive can the data, i.e. the algorithm for reconfiguring the hardware to be transferred to the computer. If an algorithm is to be transmitted to the computer from an external service center or from a device coupled to the device interface, a request to transmit the reconfiguration data may first be required.

Furthermore, an activation signal to the memory control means may be required after the microprocessor has started up in order to signal that the system is ready for external data transfer and the memory control means can independently carry out the transfer of an algorithm to the flash memory or an overlay memory. A state can be provided in which an external transmission of hardware algorithms is completely prevented.

If, for example, hardware configuration data is stored in a special memory area of a memory, it can be provided that all can be called up at the same address, only one of the memory pages being active, which reflects the current hardware configuration for a connected device. The other data pages can provide algorithms in the form of a hardware configuration language if another device is to be connected. Then only one of the previously inactive ones Memory pages activated, which automatically adjusts the hardware configuration for the new device. The reconfigurable module is automatically rewired using the hardware description language with regard to the connections between the individual memory cells and wired differently with respect to the memory cells, which, for example, configures the interface with a new pin-to-pin connection.

There are now various possibilities for advantageously designing and developing the teaching of the present invention. For this purpose, reference is made to the subordinate claims on the one hand and to the following explanation of an embodiment on the other hand. It shows in a schematic representation

Fig. 1 is a diagram with various functional blocks according to an embodiment of the universal computer according to the present invention.

The universal computer according to the present invention has a microprocessor 1, as reconfigurable hardware an FPGA module 2 and a storage means 3 in which the calculated or read data can be stored via the data storage path 4. In addition, a floating point unit 5 for calculating floating point numbers and a bus interface unit 6 are provided which can transmit the data within the computer via the internal bus or control the data transmission. An interrupt controller 8 is provided on the internal data bus 7 for controlling the peripheral devices or for evaluating certain signals, which is used via a watchdog unit 9 and a timer to control the various control programs.

The internal data bus 7 is connected via a so-called bridge 10 to the internal data bus 11 for controlling the peripheral components and various interfaces 15-19. Peripheral components include real-time control device 12, another timer 13 for variable use, a pulse width modulator 14 and several device interfaces 15, 16 and several data bus interfaces 17 - 19. One of the data bus interfaces 17 is a CAN bus interface, with another interface 19 being suitable for coupling an optical data bus. A wireless interface 20, in particular according to the Bluetooth standard, is provided in order to wirelessly store software, data and algorithms for reconfiguring the hardware on a flash memory 21. In particular, a hardware description language, for example according to the Verilog standard, is used as the algorithm for reconfiguring the hardware.

A memory control means 22 is provided in order to automatically transfer the reconfiguration algorithm, the data or software to the flash memory 21 in the means of transport. The memory control means 22 can carry out the data transmission via the Bluetooth interface 20 independently of the microprocessor 1, as a result of which the microprocessor 1 can use its computing time for the control processes from devices connected externally to the interfaces 15-19. The flash memory 21 is provided in order to load special software which, on the one hand, allows the algorithm for reprogramming the FPGA and, on the other hand, the initial initialization of the FPGA module 2 in normal operation. In addition, the memory control means 22 can transfer data-synchronously or asynchronously to a computing process from the memory means 3 into the microprocessor 2.

The memory control means 22 provides a flash memory reprogramming mode in which an authorization check is first carried out for a transfer of data, and provides authorization to transfer algorithms, data or software into the flash memory 21. The memory control means 22 also provides an FPGA reconfiguration mode, an authorization check of the system user also being carried out here first and then an algorithm for reconfiguration being loaded. On The algorithm can be implemented, for example, in the Hardware Description Language (HDL), which describes how the hardware is redesigned.

The memory control means 22 can also control special memories which store algorithms and data on data pages. A selection value is assigned to these data pages and, at each access time, the memory control means 22 only takes into account that page that is currently valid after the selection value. In this way, several configuration algorithms for the FPGA 2 can be stored in a memory area, and the FPGA module 2 is configured by a memory access by the memory control means 22. Depending on the selection value, the memory control means 22 then accesses the currently valid data page at the same memory address and configures the FPGA hardware 2 accordingly. In the memory addressing area, the currently valid data page overlaps the other pages in a memory addressing area, which could be used as an alternative to the configuration of the hardware, but are currently not required due to the existing device circuitry.

One possibility of reconfiguring the hardware 2 is to change the interfaces 17-19 to the data bus. The wiring of the individual logic elements of the interface modules 17 - 19 is changed, which are then implemented in the form of FPGA memory cells 2. For example, the interface 19 can be adapted to a new data bus by reconfiguring the hardware. On the other hand, however, an interface 16 can also be adaptable to a new device, so that the logic cells and the wiring in the interface module 16 are changed. The more devices in the network, the more reconfiguration processes may be required during the lifetime of a means of transport. For this purpose, it can be provided that the devices themselves already provide a suitable algorithm for the reconfiguration of the hardware, which is then based on the corresponding appropriate interface is transferred to the memory control means 22 and automatically provides a reconfiguration of the interface modules 15 to 19. This automatic reconfiguration of the hardware 2 can be carried out by the memory control module 22 after an authorization check.

The universal computer can be designed to reconfigure its own architecture and to reconfigure the network control. For example, the wiring to the interfaces 15-19 or the wiring of the individual devices to one another can be changed on the basis of the computer architecture. On the other hand, the interfaces can be automatically adapted to devices if they provide an algorithm for the reconfiguration and transmission of the computer architecture and the memory control means 22 automatically provides for a reconfiguration of the circuits implemented in FPGA 2 on the basis of these algorithms.

Claims

claims

1. Universal computer for a means of transport with a microprocessor (1) for processing control programs, a storage means (3) for the data calculated thereby and an interface (17) which allows the computer to be connected to a data bus in the means of transport, the computer Control programs for controlling devices provided in the means of transport and the control commands are transmitted to the device to be controlled via device interfaces (15, 16), characterized in that the computer has reconfigurable hardware (2) which, when the computer is installed, has to be reconfigured afterwards peripheral components or an interface (15 - 20), and that transmission means (20, 22) are provided which transmit an algorithm for reconfiguring the hardware to the storage means (3, 21) in the means of transport, so that a process for reconfiguring the peripheral components or the Sc Interface (15 - 20) relevant hardware (2) can be carried out.

2. Computer according to claim 1, so that the reconfigurable hardware (2) has freely switchable memory cells with reconfigurable electrical connections which can be reconnected in accordance with the algorithm for reconfiguring the hardware (2) when the computer is installed.

3. Computer according to claim 1 or 2, characterized in that the reconfigurable hardware (2) is a so-called field programmable gate array (FPGA).

4. Universal computer for a means of transport with a microprocessor (1) for processing control programs, a storage means (3) for the data calculated thereby and an interface (17) which allows the computer to be connected to a data bus in the means of transport, the computer Has control programs for controlling devices provided in the means of transport and the control commands are transmitted to the device to be controlled via device interfaces (15, 16), characterized in that memory control means (22) are provided which do not burden the processor time of the microprocessor (1), automatically transfers the algorithm for reconfiguring the hardware (2) to the storage means (3, 21) in the means of transport and that a memory is provided in which a plurality of data pages for the configuration of the hardware (2) are stored, only one of these data pages being used for the existing device configuration as valid ft, and that the memory control means (22) accesses the applicable data pages according to the configuration.

5. Computer according to claim 1 or 4, characterized in that the storage means is a flash memory (21) which is connected to a wireless interface (20) via which the algorithm for reconfiguring the hardware in the flash memory (21st ) is transferable.

6. Computer according to claim 1 or 4, so that a part of the computer consists of standard cell blocks which are designed as reconfigurable hardware.

7. Computer according to claim 6, characterized in that the microprocessor (1) has standard cell blocks, which over the re configurable hardware can be variably wired with an interface (15, 16, 17, 18, 20).

8. Computer according to claim 1 or 4, so that the configuration of the hardware necessary for an external device coupled to the device interfaces (15, 16) is stored in the device in the form of a hardware description language for transmission to the computer.

9. The computer as claimed in claim 8, so that the device interface transmits the hardware description language for the computer's peripherals and interfaces to the computer and / or the memory control means (22).

10. Computer according to claim 1 or 4, characterized in that a memory control means (22) is provided, that a transmission security means has that a transmission of an algorithm for reconfiguring the hardware (2) only after a check whether in the current State of the vehicle or computer this type of data transmission is to be permitted and / or whether the sender is authorized to transmit a new algorithm for reconfiguring the hardware (2).