EP1405418A2

EP1405418A2 - Method and device for producing mobile radio signals

Info

Publication number: EP1405418A2
Application number: EP02745084A
Authority: EP
Inventors: Frank Lillie
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 2001-07-10
Filing date: 2002-05-23
Publication date: 2004-04-07
Also published as: WO2003007478A3; WO2003007478A2; US20040176045A1; CN1605156A; WO2003007478A8; DE10133514A1

Abstract

The invention relates to a method for producing mobile radio signals using a DDS (12) (direct digital frequency synthesis) and a modulator (14), comprising the following steps: A) an intermediate frequency (fout-DDS) is produced by controlling the DDS (12) using a DDS control word (S) and a DDS clock pulse frequency (fclk-DDS), and B) the intermediate frequency (fout-DDS) is transformed into an emission frequency (fout-RF) of the mobile radio signals, using the modulator (14), according to a reference frequency (fref) of the modulator (14). According to the invention, the reference frequency (fref) of the modulator (14) is used as a DDS clock pulse frequency (fclk-DDS), said frequency being unmodified or divided by a division factor (N). In order to produce the intermediate frequency (fout-DDS), the DDS control word (S) is selected in such a way that it compensates fluctuations of the reference frequency (fref) of the modulator (14).

Description

description

Method and device for generating mobile radio signals

The present invention relates to a method for generating mobile radio signals using a DDS (direct digital frequency synthesis) and a modulator, comprising the steps:

A) Generating an intermediate frequency by driving the DDS with a DDS control word and a DDS clock frequency and

B) transforming the intermediate frequency to a transmission frequency of the mobile radio signals using the modulator as a function of a reference frequency of the modulator.

Mobile radio signals are transmitted as RF signals with a specific transmission frequency from a mobile station to a base station. For the synthesis of such signals with a desired frequency - for example an RF transmission frequency in the range of 900 or 1800/1900 MHz, as used in the currently common GSM standard - it is customary to mix, multiply or divide basic Winning frequencies. The base frequencies are generally derived from a quartz oscillator serving as a frequency standard, which oscillates stably at 26 MHz, for example. This basic frequency is used in the generation of the mobile radio signals immediately or after modification.

For example, in a mobile radio terminal as indicated at the beginning, an intermediate frequency is generated from the base frequency by means of a DDS (direct digital frequency synthesis), which is then processed further. The DDS is controlled via a DDS control word and a DDS clock frequency, the generation of the intermediate frequency basically going back to a counting process carried out in the DDS. In this counting process, a counter is incremented by the control word in time with the DDS clock frequency until the counter reaches an invariant maximum value which is inherent in the DDS (Phase battery width), whereupon it is reset again with an initial value which corresponds to the overflow of the previous counting cycle. Depending on the design of the DDS, either the maximum value reached by the counter or the incrementation of the counter is used to generate a signal with the intermediate frequency. This signal therefore depends on the DDS clock frequency and the control word.

For practical reasons, the DDS will use the

Intermediate frequency output signal is transformed with a downstream modulator, for example an offset phase locked loop (O-PLL), in the range of mobile radio transmission frequencies. For this purpose, two oscillators are required, one of which provides a reference frequency, which flows into the control of a further voltage-controlled transmission oscillator.

The generation of mobile radio signals described above requires a relatively high amount of hardware. In particular, it should be borne in mind that previously at least three frequency oscillators were required for the above implementation, namely a frequency oscillator for generating the DDS clock frequency, a frequency oscillator for generating the reference frequency for the O-PLL and a frequency oscillator for generating the transmission frequency. However, this hardware effort is in contrast to the trend to produce high-frequency transmitter / receiver modules for the mass market, which requires as few external components as possible and which have high circuit performance with good reproducibility. This requires reducing the number of individual circuit components as much as possible. In addition, one goal in the design of the circuits is to use as few oscillators as possible, since these disrupt the circuit performance, for example through harmonic generation, crosstalk or the like. It is therefore an object of the present invention to provide a method of the type described in the introduction with which the number of oscillators required can be reduced.

This object is achieved by a method for generating mobile radio signals using a DDS and a modulator, comprising the steps: A) generating an intermediate frequency by driving the DDS with a DDS control word and a DDS clock frequency and B) transforming the intermediate frequency to one Transmission frequency of the mobile radio signals using the modulator as a function of a reference frequency of the modulator. It is provided according to the invention that the reference frequency of the modulator - unchanged or divided by a division factor - is used as the DDS clock frequency, the DDS control word being selected to generate the intermediate frequency such that it compensates for fluctuations in the reference frequency of the modulator.

By using the reference frequency of the modulator downstream of the DDS as the DDS clock frequency, it is possible to omit the oscillator assigned to the DDS for supplying the clock frequency. This measure simplifies the construction of a corresponding circuit and improves the circuit performance and its reproducibility. The problem with the solution according to the invention arises that the reference frequency of the modulator can fluctuate, in particular if the reference frequency of the modulator is generated by a channel synthesizer for generating regularly changing frequency channels for the mobile radio signals. However, this problem is taken into account in the solution according to the invention in that the current DDS control word is selected in such a way that, in addition to the information for generating a desired intermediate frequency, it also contains information by means of which the fluctuations the reference frequency of the modulator can be compensated. This makes it possible to use the DDS to generate a signal with a desired intermediate frequency with sufficient stability, which can then be transformed up to a desired transmission frequency with the downstream modulator, for example with the 900 MHz or 1800/1900 MHz GSM standard , The invention thus shows a way in which, by simplifying the circuit of a high-frequency transmitter module, the reference frequency of a modulator connected downstream of the DDS can be used to generate the DDS clock frequency.

In a development of the invention it can be provided that the reference frequency of the modulator in the channel synthesizer is generated from a variable output frequency of a voltage-controlled oscillator by transformation to the reference frequency. The transformation to the reference frequency can be carried out by a synthesizer phase locked loop (PLL).

As stated above, the DDS control word must be determined in accordance with the current reference frequency of the modulator. The following relationship must be specified:

N S - [fout-DDS / fcl -DDS] * 2

in which

S the control word, fout-DDS the intermediate frequency, fcik-DDs the DDS clock frequency and

N is the phase battery width of the DDS.

With a constant phase battery width N of the DDS, the control word S must therefore be calculated from the desired intermediate frequency and the current clock frequency, which is directly dependent on the reference frequency of the modulator. The calculation can be made possible with relatively little hardware expenditure.

As an alternative to calculating the DDS control word from the currently available parameters, intermediate frequency and DDS clock frequency, it can be provided according to the invention that the DDS control word is determined from a previously stored table as a function of the current DDS clock frequency and the desired intermediate frequency. This variant of the invention is selected, for example, when a sufficient amount of storage space is available inexpensively.

In a further development of the invention it can be provided that the DDS control word is generated from an output signal of a further modulator, in particular a GMSK modulator. In this case, the DDS control word contains information on frequency modulation by the further modulator, on the intermediate frequency and on compensating for the fluctuation in the reference frequency of the modulator. However, the method according to the invention is inherently independent of the type of further modulator, so that other types of modulators can also be used instead of a GMSK modulator.

The invention further relates to a device for generating mobile radio signals, in particular according to the method of the type described above, comprising: a DDS (direct digital frequency synthesis) for generating an intermediate frequency from a DDS control word and a DDS clock frequency and - a modulator for transforming the Intermediate frequency to a transmission frequency of the mobile radio signals depending on a reference frequency of the modulator. In this device it is provided that the DDS clock frequency is derived from the reference frequency of the modulator and that the DDS control word is selected in accordance with the reference frequency of the modulator. In a development of the device according to the invention, a channel synthesizer can be provided for generating frequency channels of the mobile radio signals, the output frequency of the channel synthesizer - unchanged or divided by a division factor - being fed to the modulator as the reference frequency and the DDS as the DDS clock frequency. Furthermore, it can be provided according to the invention that the channel synthesizer has an oscillator, preferably a voltage-controlled oscillator, and a synthesizer phase locked loop connected downstream of this.

In order to adapt the reference frequency of the modulator to the requirements given for controlling the DDS, in a further development of the device according to the invention a frequency divider can be provided for dividing the reference frequency of the modulator down to the desired DDS clock frequency. This can be a conventional frequency divider or another DDS.

As indicated above, the DDS control word can be calculated or read from a previously stored table. Depending on the solution chosen, the device according to the invention can therefore have a calculation unit for calculating the DDS control word or a memory unit for storing and reading out a table which contains the DDS control word as a function of the current DDS clock frequency and the desired intermediate frequency.

According to the invention it can be provided that the modulator is designed as a phase locked loop, in particular as an offset PLL. This leads to a circuit concept for transforming up the intermediate frequency that can be easily integrated and implemented cost-effectively. However, other types of open-loop modulators are also conceivable, which enable the intermediate frequency to be stepped up. Furthermore, it can be provided that the device according to the invention comprises a further modulator, in particular a GMSK modulator, which is connected upstream of the DDS for generating a DDS control word.

The device according to the invention can be controlled by a higher-level control unit, which acts, for example, on the further modulator, the DDS, and on the channel synthesizer.

The invention is explained below by way of example with reference to the accompanying figures:

They represent:

FIG. 1 shows a functional block representation which shows one possibility of realizing the method according to the invention; and FIG. 2 shows a functional block view of the transmission circuit of an integrated high-frequency transmission

/ Receive module with a circuit concept according to the invention.

In Figure 1, a circuit arrangement according to the invention is generally designated 10. This includes a DDS (direct digital frequency synthesis device) 12, which is followed by a modulator designed as an offset PLL (offset phase locked loop) 14. A signal with a reference frequency fref is fed into the offset PLL 14 by a channel synthesizer 16 via the line 18. This signal with the reference frequency f _re f is further branched off via the line 20 and fed to a frequency divider 22. In the frequency divider 22, the frequency f _re f is divided down by a division factor N, so that a signal with a frequency ^r clk-DDS is obtained, which is fed via line 24 to the DDS 12 as a clock signal. For the frequencies of the signals ^■ the relationship applies: ^f ref = N ^• fclk-DDS-

The device according to the invention for generating mobile radio signals works as follows:

To generate a desired intermediate frequency fout-DDS, a control word S is fed to the DDS via a line 26 and a clock signal with a clock frequency f _c ik_ DDS is fed via a line 24. A periodic signal with the intermediate frequency fout-DDS ', for example of 20 MHz, is generated in the DDS 12 in a manner known per se. This is done by incrementing a counter with a predetermined maximum count value (phase battery width) in each clock cycle predetermined by the clock frequency fclk-DDS by the respectively specified control word S until the maximum count value (phase battery width) is reached or exceeded. The counter is then reset, the value by which the maximum count value was exceeded during incrementation being adopted for a renewed increment after the reset. The counter is then incremented again. The progress of the incrementation or the reaching of the maximum value is used to generate a periodic signal with the intermediate frequency fout-DDS.

This periodic signal with the intermediate frequency fclk-DD _S is then stepped up via the offset PLL circuit 14 to a transmission frequency fout-RF. For this purpose, the phase difference between the signal output via line 30 by the DDS with the intermediate frequency fout-DD _S ^and the comparison signal output on line 32 to the phase detector 28 is first detected in a phase detector 28. This comparison signal is obtained by mixing the mobile radio output signal with the frequency f _Q ut-RF ^and the reference signal with the frequency f _re f via a mixer 34. The signal output by the phase detector 28 via the line 36 is fed to a charge pump 38, via which a loop filter 42 is controlled via the line 40.

The output signal of the loop filter 42 is output via the line 44 for driving a voltage-controlled oscillator 46, the center frequency of which is, for example, 1800 MHz.

As can be seen from FIG. 1, one and the same oscillator, namely the oscillator 48 assigned to the channel synthesizer 16, is ultimately used to generate the reference signal for the offset PLL 14 and to generate the clock signal for the DDS 12. Its output frequency is stepped up to the reference frequency f _re f via a further phase locked loop 50. This makes it possible to dispense with the provision of a separate oscillator for generating a signal with the clock frequency fclk-DD _S for the DDS 12 when designing the circuit 10, which simplifies the construction of the device according to the invention and improves the circuit performance ,

FIG. 2 now shows an application for the circuit according to the invention according to FIG. 1. In order to facilitate the description and to avoid repetitions, the same reference symbols are used for the same or similar components as were described in FIG.

FIG. 2 shows a schematic illustration of a transmit / receive module 52, only the circuit concept relevant to the transmission of mobile radio signals being shown. However, it should be pointed out that there is a connection via line 54 to reception mixers and thus to the circuit parts relevant for the reception of mobile radio signals. Figure 2 now shows - partly highlighted with dashed lines - the three essential components of the invention, namely the DDS 12, the offset PLL 14 and the channel synthesizer 16. Furthermore, Figure 2 shows how these components in the circuit concept of the transmit / receive module 52 are involved.

Starting from a quartz oscillator 56 serving as a frequency standard, a signal with a fundamental frequency fbase ^of, for example, 26 MHz is fed into the circuit via a line 58. On the one hand, this is fed to a modulator 60 via a line 62, the frequency of which is divided in advance by means of a frequency divider 64 with a division factor M, for example to a frequency of 2.16 MHz.

The modulator 60 is controlled by a control unit 68 via a line 66. The modulator 60 is, for example, a GMSK modulator. The control unit 68 also controls an adder 72 via a line 70, which adds an output signal from the modulator 60 and an output signal from the control unit 68 to the control word S, which in turn is fed to the DDS 12 via the line 26.

The signal with the base frequency fbase is also fed to the phase locked loop PLL 50 of the channel synthesizer 16 as a reference signal. The PLL 50 interacts in the manner already described with reference to FIG. 1 with the voltage-controlled oscillator 48, which for example outputs a signal with a frequency of 3.6 GHz. A loop filter 70 is connected downstream of the oscillator 48.

The output signal of the PLL 50 with the reference frequency f _re f is fed to the offset PLL 14 on the one hand via the line 18 and on the other hand fed to the frequency divider 22 via the line 20. As explained above, the reference frequency quenz f _re f divided by means of the frequency divider 22 with the division factor N to the clock frequency f _c lk-DDS, which is supplied via line 24 to the DDS 12 as the frequency of the clock signal.

Based on the control word S fed in via line 26 and the clock frequency f _c lk-DDS ^e ^ - ⁿ signal input via line 24, the DDS 12 generates the signal with the intermediate frequency fout-DD _S 'which the offset PLL 14 uses line 30 is fed. This signal with the intermediate frequency fout-DS is processed as described above with reference to FIG. 1 in the PLL 14, more precisely via its components phase detector 28, charge pump 38, loop filter 42 and oscillator 46.

It should be pointed out that, depending on the desired transmission frequency in the embodiment according to FIG. 2, two oscillators are provided in the offset PLL 14, namely the oscillator 46 and the oscillator 74, the oscillator 46 having a center frequency such that these transmit frequencies in the range of 1800 or 1900 MHz, whereas the oscillator 74 is designed such that it has a center frequency in the range of 900 MHz. Such provision of two oscillators with these frequency ranges is required, for example, for the operation of a mobile phone in three different GSM networks.

It should also be pointed out that, depending on the active state of the oscillators 46 and 74, the reference frequency f _re f output via the line 18 is first divided down via a variably adjustable frequency divider 76 before it is fed to the offset PLL 14 and fed into the mixer 34 ,

The output signal with the transmission frequency fout-RF is fed and amplified via line 78 to a power amplifier 80 of the transmission output stage. From this the transmission signal fed to an antenna 82 and emitted in the form of electromagnetic waves.

The above description, which relates to FIG. 2, shows one possibility of how the circuit concept according to the invention can be integrated in a transmit / receive module 52 for a mobile radio terminal in such a way that, while simplifying the circuit concept, it can be reproduced well at high circuit performance - is settled. Again, as described with reference to FIG. 1, the reference frequency f _re f of the channel synthesizer 16 is used to both control the offset PLL 14 and to clock the DDS 12 after division by means of the frequency divider 22.

Claims

claims

1. A method for generating mobile radio signals using a DDS (12) (direct digital frequency synthesis) and a modulator (14), comprising the steps:

A) Generating an intermediate frequency (fout-DDS) by driving the DDS (12) with a DDS control word (S) and a DDS clock frequency ⁽ fclk-DDS) ^and d

B) transformation of the intermediate frequency (fout-DDS) ^o f a transmission frequency (fout-RF) of the mobile radio signals using modulator (14) in response to a reference frequency (f _re f) of the modulator (14), characterized in that as the DDS clock frequency (fclk-DDS) ° ^ - ^e reference frequency (fref) of the modulator (14) - unchanged or by a

Division factor (N) divided - is used, the DDS control word (S) being selected to generate the intermediate frequency (fout-DDS) such that it compensates for fluctuations in the reference frequency (fref) of the modulator (14).

2. The method according to claim 1, characterized in that the reference frequency (f _re f) of the modulator (14) is generated by a channel synthesizer (16) for generating frequency channels for the mobile radio signals.

3. The method according to claim 2, characterized in that the reference frequency (f _r ef) of the modulator (14) in the channel synthesizer (16) is generated from a variable output frequency by transformation to the reference frequency (f _r ef).

4. The method according to any one of the preceding claims, characterized in that the DDS control word (S) is determined from the following equation: S = [fout-DDS / clk-DDS] *,

where S is the control word, fout-DDs the intermediate frequency, fci _k -D _D s the DDS clock frequency and

N is the phase battery width of the DDS.

5. The method according to any one of claims 1-3, since you rchgek characterized that the DDS control word (S) from a previously stored table depending on the current DDS clock frequency (fclk-DDS) ^{un (} the desired intermediate frequency (fout-DDS ) is determined.

6. The method as claimed in one of the preceding claims, that the DDS control word (S) is generated from an output signal of a further modulator (60), in particular a GMSK modulator.

7. Device (52) for generating mobile radio signals, in particular according to the method according to one of the preceding claims, comprising: a DDS (12) (direct digital frequency synthesis) for generating an intermediate frequency (fout-DDS) ^from a DDS control word ( S) and a DDS clock rate (clk-DDS), and - a modulator (14) for transforming the intermediate frequency (fout-DD _S) ^o f a transmission frequency (fout-RF) of the mobile radio signals in response to a reference frequency (f _re f) of the modulator (14), characterized in that the DDS clock frequency (f clk-DDS) is derived ^from ^ ^he reference frequency (fref) of the modulator (14) and that the DDS Control word is selected in accordance with the reference frequency (f _r ef) of the modulator (14).

8. Device (52) according to claim 7, characterized by a channel synthesizer (16) for generating frequency channels for the mobile radio signals, the output frequency (f _r ef) of the channel synthesizer (16) - unchanged or divided by a division factor (N) - the modulator (14) as the reference frequency (f _re f) and the DDS (12) as the DDS clock frequency (f _c ik_ DS) is supplied.

9. The device (52) according to claim 7 or 8, so that the channel synthesizer (16) has an oscillator (48), preferably a voltage-controlled oscillator (46), and a synthesizer phase locked loop (50) connected downstream of the latter.

10. Device (52) according to one of claims 7 to 9, characterized by a frequency divider (22) for dividing the reference frequency (f _r ef) of the modulator (14) to the desired DDS clock frequency (fclk-DDS) •

11. Device (52) according to one of claims 7 to 10, g e k e n n z e i c h n e t d u r c h a calculation unit (68) for calculating the DDS control word (S) according to the following relationship:

S = [fout-DDS / fclk-DDS] * 2,

in which

S the control word, fout-DDs the intermediate frequency, fci-DDs the DDS clock frequency and

N is the phase battery width of the DDS.

12. Device (52) according to one of claims 7 to 10, characterized by a memory unit for storing and reading out a table which the DDS control word (S) as a function of the current DDS clock frequency (fclk-DDS) ^and & ° the desired intermediate frequency (out-D _DS ).

13. Device (52) according to one of claims 7 to 12, that the modulator (14) is designed as a phase locked loop (14), in particular as an offset PLL.

14. The device (52) according to one of claims 7 to 13, a further modulator (60), in particular a GMSK modulator, which is connected upstream of the DDS (12) to generate a DDS control word (S).

15. Device (52) according to one of claims 7 to 13, a control unit (68) for controlling the further modulator (60), the DDS (12) and the channel synthesizer (16).