EP1384202A2 - Systeme et procede de decodage local d'une sequence de bits numerique pour commuter l'etat d'un pixel sur une base temporelle, dans le but de reguler les niveaux de gris et la correction gamma - Google Patents

Systeme et procede de decodage local d'une sequence de bits numerique pour commuter l'etat d'un pixel sur une base temporelle, dans le but de reguler les niveaux de gris et la correction gamma

Info

Publication number
EP1384202A2
EP1384202A2 EP02724978A EP02724978A EP1384202A2 EP 1384202 A2 EP1384202 A2 EP 1384202A2 EP 02724978 A EP02724978 A EP 02724978A EP 02724978 A EP02724978 A EP 02724978A EP 1384202 A2 EP1384202 A2 EP 1384202A2
Authority
EP
European Patent Office
Prior art keywords
pixel
display
ofthe
pixels
intensity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02724978A
Other languages
German (de)
English (en)
Inventor
James R. Huston
Jinsuk Kang
Mike Gunter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Three Five Systems Inc
Original Assignee
Three Five Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Three Five Systems Inc filed Critical Three Five Systems Inc
Publication of EP1384202A2 publication Critical patent/EP1384202A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
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    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G09G3/2025—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames having all the same time duration
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/3466—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on interferometric effect
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
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    • G09G5/14—Display of multiple viewports

Definitions

  • the present invention relates to a display system for producing an image and more specifically to methods for applying digital information to generate color and grayscale.
  • a continuing objective in the field of electronics is the miniaturization of electronic devices.
  • Most electronic devices include an electronic display.
  • the miniaturization of electronic displays is critical to the production of a wide variety of compact electronic devices.
  • electronic devices such as personal digital assistants, cell phones, digital still cameras, DVD players and internet appliances become ever smaller and more portable, the demands on the electronic displays for these products must meet difficult and seemingly contradictory requirements.
  • the displays must provide increasing amounts of high quality visual information, sometimes approaching that of a desktop monitor. Yet these displays must still be very compact and lightweight, consume little power, and be produced at low cost. Until recently, displays were not able to meet all of these requirements.
  • an electronic display is to provide the eye with a visual image of certain information.
  • This image may be provided by constructing an image plane composed of an array of picture elements (or pixels) which are independently controlled as to the color and intensity of the light emanating from each pixel.
  • the electronic display is generally distinguished by the characteristic that an electronic signal is transmitted to each pixel to control the light characteristics which determine the pattern of light from the pixel array which forms the image.
  • CTR cathode ray tube
  • AMLCD active-matrix liquid crystal display
  • the CRT is an emissive display in which light is created through an electron beam exciting a phosphor which in turn emits light visible to the eye.
  • Electric fields are used to scan the electron beam in a raster fashion over the array of pixels formed by the phosphors on the face plate of the electron tube.
  • the intensity of the electron beam is varied in an analog (continuous) fashion as the beam is swept across the image plane, thus creating the pattern of light intensity which forms the visible image.
  • three electron beams are simultaneously scanned to independently excite three different color phosphors respectively which are grouped into a triad at each pixel location.
  • an AMLCD display utilizes a lamp to uniformly illuminate the image plane which is formed by a thin layer of liquid crystal material laminated between two transparent conductive surfaces which are comprised of a pattern of individual capacitors to create the pixel array.
  • the intensity of the illumination light transmitted through each pixel is controlled by the voltage across the capacitor, which is in turn controlled by an active transistor circuit connected to each pixel.
  • This matrix of transistors (the active matrix) distinguish the AMLCD from the passive matrix liquid crystal devices which are strictly an array of conductors controlled by transistors external to the image area usually in the periphery of the matrix. The ability of each transistor to control the characteristics of just one pixel allows for the higher performance found in AMLCD displays in contrast to the passive arrays.
  • the electronic signals which control the images are transmitted to the pixel from driver circuits along the edges of the rows and columns.
  • driver circuits along the edges of the rows and columns.
  • an enabling signal to the corresponding row driver activates the transistor connected to each pixel in that row to pass the voltage onto the capacitor forming the pixel.
  • This storage mechanism is similar to dynamic memory cells (DRAM) although the cells are typically addressed serially (rasterwise) rather than randomly as DRAM implies.
  • DRAM dynamic memory cells
  • High resolution displays may contain hundreds of thousands of pixels.
  • the Super VGA (SVGA) display resolution consists of 480,000 pixels.
  • the frame storage is only equal to the approximately one-half megabit frame size.
  • the frame storage would approach 12 megabits.
  • At the frame rates which are common today for high performance displays at least 60 frames per second and up to 85 frames per second, as many as one gigabits per second must be transferred from the frame buffer to the display.
  • the state of semiconductor technology at present limits clock speeds to a level well below such transfer rates and parallel interfaces of 16 to 32 bit widths are typical in high performance displays.
  • DAC digital-to-analog converter
  • MEMS micro electro-mechanical system
  • polymeric dispersed cholesteric liquid crystals which are inherently bistable due to nonlinearities of the electro-optic response curve.
  • image storage within the device itself can be indefinite although without color or grayscale.
  • grayscale can be achieved through time division of the image frame into a multiplicity of on and off states which on average provide a shade proportional to the signal pattern.
  • a multiplicity of transistors may be provided in correspondence to each pixel such that a static memory (SRAM) cell (typically five or six transistors) can be utilized to activate each pixel.
  • SRAM static memory
  • There are several advantages to static memory such as the on-state output voltage always being at the rail voltage, the low state retentnion current, no voltage decay, and sufficient noise margin to read from the memory cells any stored data.
  • a static memory cell is itself bistable, the pixel activation will provide no analog grayscale. h general, displays with no analog response fall into three categories. Those displays with an extremely fast response in relation to the time divisions of the on- off cycles (as is typical of MEMS devices) can achieve grayscale through pulse width modulation.
  • This modulation can be a modulation of the liquid crystal response while the illuminating pulse is held constant or a modulation of the illumination duration while the liquid crystal is controlled to be either on or off during the period of illumination.
  • Those displays with a relatively slow response time in relation to on-off cycles can achieve grayscale through a root mean square (RMS) voltage level based on the average time- voltage product.
  • RMS root mean square
  • a variety of alternative schemes may be employed.
  • the inventions described herein will present several methods to provide high quality color display operation in these circumstances, h all cases however, there is a disadvantage in comparison to analog grayscale methodologies, that being the loss of parallelism of the data transfer of the grayscale bits. Data transfer rates from frame buffers to a binary display device can be significantly higher than an analog display.
  • each picture element pixel is divided into three or more sub-pixels and a color filter, typically red, green and blue, is placed in the light path from each sub-pixel.
  • the eye merges these sub-pixels to create a color image.
  • This method suffers from significant light loss in the color filters, requiring up to four times as much power to be supplied to the illumination system.
  • the color filters also add significant additional cost to the display.
  • the second method avoids the high power requirement and added cost of the sub-pixel/color filter method.
  • the pixel sizes are also small relative to the size of color filters used in TFT AMLCD displays to create color triads for each pixel.
  • LEDs light emitting diodes
  • This method of color creation is called field sequential color wherein each color field is sequentially illuminated by the appropriate diode. Because at least three different color field images need to be displayed at a rate faster than can be resolved by the eye, the field sequential color method at least triples the data transfer rate required as compared to a monochrome display.
  • the display system should also be adaptable for use as a microdisplay.
  • red, green and blue levels are stored into the array as analog voltage levels. These levels control directly the voltage applied to liquid crystal between pixel and ITO layer to produce the various shades of color under constant illumination.
  • the voltage level of each pixel is maintained by the active- matrix circuit until a new value is applied to the pixel.
  • Red, green, and blue component sub-pixels are simultaneously applied to the Liquid Crystal (LC) as a group to form a single pixel. Variations in color response of the LC is accounted for in each pixel, rather than by different voltage levels of ITO.
  • LC Liquid Crystal
  • Binary control of LC avoids many complications of analog drive methods. Analog control is far more sensitive to variations in cell gap, temperature, and LC contaminates, requiring high levels of quality control during manufacture. However, binary methods have inherently been more limited in terms of color depth due to optical response time of ordinary LC. What is needed is a system and method of driving the aforementioned displays that overcomes the disadvantages inherent in the prior art.
  • a display matrix is provided for forming a composite image from a series of sub-images.
  • the display matrix includes a plurality of display elements, each display element including a pixel, and a display circuit electrically connected to the pixel.
  • Each display circuit can include a plurality of memory cells, and a selector for outputting to the pixel data from one memory cell at a time.
  • An illumination source illuminates each of the pixels.
  • a plurality of memory cells in the display circuit are continuously electrically connected to the selector of the display circuit at the same time.
  • the display circuit including separate conductive elements for each memory cell in the display matrix which electrically connects a memory cell to the selector in the display circuit.
  • Logic controls the intensity of each pixel utilizing a digitally controlled waveform for controlling a duration of time that illumination is allowed to pass through liquid crystal of the display elements in liquid crystal displays.
  • the logic controls the duration that each of the OLEDs emits light.
  • logic sets pixel timers associated with each of the pixels with intensity values.
  • Logic is also provided for switching all of the pixels to a first state which is either on or off for example, initiating the pixel timers, and switching each of the pixels to a second state which is preferably opposite of the first state (i.e., on to off or off to on) upon termination of the associated pixel timer.
  • multi-bit memory associated with each of the pixels, a single bit digital analyzer associated with each of the pixels, and set/reset pixel state latches associated with each of the pixels is provided.
  • a value broadcasting mechanism broadcasts an intensity value to the digital analyzer.
  • the digital analyzer tests selected bit positions of the associated pixel memory for determining whether the selected bit positions match the intensity value.
  • Each of the pixels has been previously set to a first state.
  • a pixel is set to a second state upon determining that the selected bit positions associated with the pixel match the intensity value.
  • the broadcasting mechanism is implemented outside an array of the display elements .
  • intensity values can be broadcast with a delay between each broadcast.
  • the digital analyzer tests selected bit positions of the associated pixel memory after each broadcast for determining whether the selected bit positions match the intensity value.
  • a pixel is set to the second state upon determining that the selected bit positions associated with the pixel match the current intensity value.
  • the delay between each broadcast can be different than the previous delay.
  • each level of gray displayed by a pixel is individually adjustable with respect to a next higher or lower level.
  • the system is designed to consume less power than other known types of display systems.
  • a method for driving a digital display is also provided.
  • Each of a plurality of pixel timers is set with an intensity value, where the pixel timers are associated with pixels of a display.
  • the pixels of the display are set to a first state (i.e., optically on or optically off).
  • Each of the timers is initiated. Illumination is applied to the display.
  • Each of the pixels is switched to a second state upon expiration of the timer. The process is repeated for a predetermined number of times for generating an image.
  • a method for producing a grayscale image on a digital display is also provided according to an embodiment of the present invention.
  • Intensity values for each pixel are stored in pixel memories that are each associated with the individual pixels of a display. Each of the pixels is set to a first state.
  • a first intensity level is broadcast to the pixels. The first intensity level is analyzed with respect to the intensity values stored in the pixel memories. The pixels whose associated intensity value matches the first intensity level are switched to a second state.
  • Illumination is applied to the display. A predetermined amount of time is allowed to transpire.
  • a next intensity value is broadcasted to the pixels.
  • the next intensity level is analyzed with the intensity values stored in the pixel memories.
  • the pixels whose associated intensity value matches the next intensity level are switched to the second state.
  • the final two steps of the process are repeated for each level of desired intensity. The entire process can be repeated for each color. Similarly, selected steps of the process can be repeated for generating an image.
  • the predetermined amount of time between each broadcast of the intensity values is different than the previous amount of time.
  • each level of gray displayed by a pixel is individually adjustable with respect to a next higher or lower level.
  • the analysis of the next intensity level with the intensity values stored in the pixel memories and the switching of the pixels whose associated intensity value matches the next intensity level to a second state further include setting a value of an accumulator latch to true, selecting memory bits to be analyzed, analyzing the selected memory bits with respect to the next intensity level, and resetting the accumulator latch to false if a value of a selected memory bit matches a predetermined value, wherein the pixel is switched to the second state if the accumulator latch value is false.
  • the analysis is performed in increasing value order.
  • analysis of the broadcasted intensity levels is performed with respect to the intensity values stored in the memory of a particular pixel, and thus the process, is terminated upon the intensity values matching one of the intensity levels. Note that the process can resume for the next color field, image refresh, etc. As an option, a lower voltage can be changed to a higher voltage for output to a pixel electrode of a pixel.
  • a method for driving a digital display includes determining a pixel intensity value for each of a plurality of pixels of a display; storing the pixel intensity values as digital values; sequentially broadcasting intensity values to each of the pixels; analyzing the broadcasted intensity values to the pixel intensity values; switching each of the pixels to a second state upon the associated pixel intensity value matching the broadcasted intensity value; and repeating the process for a predetermined number of times for generating an image.
  • Each of the pixels can be an OLED or can use liquid crystal.
  • Figure 1 illustrates a display matrix
  • Figure 2 illustrates a display circuit which may be used in the display matrix of the present invention.
  • Figure 3 illustrates a prior art display circuit
  • Figure 4A illustrates a cross-sectional view of a liquid crystal device.
  • Figure 4B illustrates a top-down view of a liquid crystal device.
  • FIG. 5 illustrates a backplane integrated circuit (backplane IC) which may be used in a display matrix of the present invention.
  • backplane IC backplane integrated circuit
  • Figure 6 illustrates a configuration of strobe lines connected to display circuits.
  • Figure 7A illustrates a virtual image display system which includes a display matrix which projects an image onto a back surface of the first magnification optic which reflects (at least partially by total internal reflection) the image to a surface having a magnification function and a reflection function.
  • Figure 7B illustrates a virtual image display system which includes an illumination source which reflects light off the microdisplay system to a beamsplitter which reflects an image formed by the microdisplay to a surface of the first magnification optic having a magnification function and a reflection function.
  • Figure 7C illustrates a virtual image display system which includes an illumination source which reflects light off the microdisplay system to a back surface of a first magnification optic which reflects the light to a beamsplitter which reflects the light to a surface of the first magnification optic having a magnification function and a reflection function.
  • Figure 8 A illustrates the data transfer and display sequence of a prior art display matrix which employs a single memory cell per pixel.
  • Figures 8B and 8C illustrate data transfer and display sequences that may be used when a display matrix according to the present invention which employs two or more memory cells per pixel is operated in an FSC mode.
  • Figure 9 A illustrates a time line for displaying one bit plane for a larger portion of the time that a particular frame is displayed by displaying that bit plane longer than other bit planes.
  • Figure 9B illustrates a time line for displaying one bit plane for a larger portion of the time that a particular frame is displayed by displaying that bit plane more frequently than other bit planes.
  • Figure 10 illustrates a pair of display circuits and a pair of pixels, wherein the display circuits are partially within the footprints of each of the pixels, and the pixels are partially within the footprints of each of the display circuits.
  • Figure 11 illustrates a matrix of display circuits and pixels, wherein multiple data circuits overlap the footprints of multiple pixels, and data lines are connected to multiple display circuits.
  • Figure 12 illustrates five display circuits, each of which is partially within the footprint of each of five pixels, wherein a single set of data lines is connected to all five data circuits.
  • Figure 13 illustrates a local decoder connected to four rows of data circuits.
  • Figure 14 illustrates a system in which a processor interfaces directly to the backplane IC.
  • Figure 15 A illustrates an address map including scroll buffers.
  • Figure 15B illustrates an address map which can scroll pixel by pixel.
  • Figure 16 illustrates a system in which an external frame buffer is placed between the processor and the backplane IC.
  • Figure 17 illustrates part of a color rich mode sequence.
  • Figure 18 illustrates a color mixing mode
  • Figure 19 shows a block diagram of a display system employed in the present invention.
  • Figure 20 illustrates single color bit dynamics.
  • Figure 21 illustrates how the BBC method is used to produce a single RGB (red, green, blue) color frame.
  • Figure 22 is a flow diagram of a process for generating an image utilizing balanced binary color.
  • Figure 23 illustrates the basic shape of a waveform according to a Digitally Controlled Waveform (DCW) method.
  • DCW Digitally Controlled Waveform
  • Figure 24 is a flowchart of a process for generating an image utilizing a digitally controlled waveform.
  • Figure 25 A is a diagram of a circuit associated with a pixel according to an embodiment of the present invention.
  • Figure 25B is a flow diagram of a process for driving a display utilizing an analog controlled waveform.
  • Figure 26A is a flow diagram of a process for driving a display utilizing an analog controlled waveform.
  • Figure 26B illustrates a method for SuperFrame Dithering in accordance with one embodiment of the present invention.
  • Figure 27 illustrates spatially distributed phases for 2 bits of temporal color.
  • Figure 28 is a flow diagram of a process for producing a grayscale image according to a basic implementation of a DCW method.
  • Figure 29 is a flowchart of a process for the production of a grayscale image.
  • Figure 30 is a flow diagram illustrating a process for performing an analysis.
  • Figure 31 is a diagram of a circuit associated with a pixel according to an embodiment of the present invention.
  • Figure 32 is a circuit diagram of an OLED according to an embodiment of the present invention.
  • Figure 33 is a circuit diagram of an OLED display element according to an alternative embodiment of the present invention.
  • the present invention relates to a display matrix for forming sequentially formed composite images.
  • a sequentially formed composite image is an image formed by displaying a series of two or more different sub-images to an observer where the different sub-images are displayed one sub-image at a time on the display matrix.
  • These display matrices can be used in a display system component of a variety of electronic devices. Examples of such devices include, but are not limited to portable computers, personal communicators, personal digital assistants, modems, pagers, video and camera viewfinders, mobile phones, and television monitors.
  • the display matrices and display systems of the present invention are used in combination with one or more magnification optics to form a virtual image display system.
  • a unique property of the display matrix of the present invention is that data for a plurality of sub-images may be stored in the display matrix simultaneously. This property eases the instantaneous bandwidth requirements of the display matrix and, in certain situations, actually decreases the amount of data which must be transferred to the display matrix from external memory locations.
  • a display system forms a sequentially formed composite image by displaying a series of sub-images to an observer at a rate preferably faster than the eye of the observer can resolve.
  • Image quality is reduced if the eye is able to perceive an individual field sub-image, a phenomena known as flicker.
  • flicker In practice, it has been found that frame rates in excess of 60 Hz are necessary to avoid flicker.
  • the data for any sub-image should be present in the display matrix from the beginning until the end of the display of the sub-image. If the display matrix houses only a single sub-image at a time, then ideally the entire data transfer should take place between the display of one sub-image and the next. This places high instantaneous bandwidth requirements on the system in order to transfer all of the data for a sub-image in the interval between the display of sub-images.
  • FIG. 1 illustrates a typical display matrix 12 which includes a plurality of display elements 14.
  • Each display element 14 includes a pixel 16 and a display circuit 18 which is electrically connected to the pixel and controls the operation of the pixel 16.
  • the plurality of pixels incorporated into the plurality of display elements together form the source object formed by the display matrix 12.
  • the display circuit consists of a plurality of memory cells and a selector.
  • the selector is able to output to the pixel the contents of at most one memory cell at any instant.
  • the selector is controlled by additional input signals provided to the display circuit.
  • FIG. 2 illustrates a display circuit 18 which may be used in the display matrix of the present invention.
  • the display circuit 18 includes a plurality of memory cells 20A, 20B (two shown) which are each electrically connected to a selector 22.
  • the selector controls which memory cell is electrically connected to the pixel 16.
  • the display circuit 18 can also optionally receive one or more inputs 24 for controlling the operation of the selector 22.
  • a feature of the display circuit and display matrix of the present invention is that a plurality of the memory cells in the display circuit are continuously electrically connected to the selector of the display circuit at the same time. As a result, there is no need to address a particular memory cell to a particular selector. This may be accomplished, as illustrated in Figure 2, by the display circuit including separate conductive elements 21 for each memory cell in the display matrix which electrically connects a memory cell to the selector in the display circuit. The figure illustrates that all the memory cells in the display circuit are connected. It is noted that less than all of the memory cells may optionally be continuously electrically connected.
  • a further feature of the display circuit and display matrix of the present invention is that the display matrix is formed on a substrate having a plurality of regions where each region includes a memory circuit with a plurality of memory cells, and a selector electrically connected to each memory cell in the region.
  • Figure 1 illustrates a plurality of display circuits in separate regions. By having a plurality of regions which each include a complete memory circuit, a display matrix is provided where the memory cells are physically inter-dispersed among the selectors within the display matrix. This distinguishes the display matrix of the present invention over prior art displays with an external frame buffer.
  • the substrate may be any material on which the display circuit may be attached or formed.
  • the substrate is a semiconductor, such as silicon, on which the display circuits are formed by one or more of a variety of methods known in the art.
  • a further feature of the display matrix of the present is its ability to store more than one image at a time. Because the display circuit 18 has more than one memory cell per pixel, it is possible to display two or more different sub-images without having to write to the memory cells between displaying the different sub- images. In addition, data may be transferred to the display matrix for one sub-image while a different sub-image is displayed. Accordingly, the data transfer time for one sub-image can be spread over the entire display time of a different sub-image. This alleviates the need for a high instantaneous bandwidth or a high sub-image display rate, a clear advantage over prior art display systems.
  • Figure 3 illustrates a prior art display circuit.
  • the prior art display circuit includes a single memory cell 20C which is connected to pixel 16.
  • the prior art display circuit thus does not need a selector or input for controlling the operation of the selector.
  • the display circuit only includes one memory cell 20C, a memory matrix employing this display circuit can only store data for one sub-image and thus cannot display different sub-images without having to write to the memory cells between displaying the different sub- images.
  • the sub-images are typically composed in a spatial relationship and written simultaneously to the matrix.
  • the display matrix of the present invention may be any addressable display which includes a pixel and a display circuit which controls the operation of the pixel in response to control signals.
  • a pixel (a contraction of picture element) refers to any mechanism which can either emit light or modulate incident light in response to an electrical field to form one element of a source object.
  • the plurality of pixels incorporated into the plurality of display elements together form the source object formed by the display matrix.
  • suitable pixels include but are not limited to the pixels used in liquid crystal displays, spatial light modulators, gratings, mirror light valves, and LED arrays.
  • the pixels can be opaque or light transmissive.
  • Opaque pixels can be further divided into reflective, emissive, and scattering pixels.
  • the pixels used in the display matrix are sized to be a microdisplay.
  • a microdisplay refers to a display matrix which is used in a virtual image display system to form a source object which is then magnified by one or more magnification optics to form a magnified virtual image.
  • the microdisplay forms a source object having an area equal to or less than about 400 mm 2 , h one embodiment, the source object has an area between about 10 mm 2 and 400 mm 2 , more preferably between about 20 mm 2 and 200 mm 2 .
  • the pixels of the display matrix preferably have an area less than about 0.01mm 2 and more preferably between 50 nanometers squared and 500 nanometers squared.
  • microdisplays By designing a microdisplay to include a display circuit according to the present invention, microdisplays with reduced instantaneous bandwidth requirements and reduced average bandwidth are provided.
  • the reduced bandwidth requirements translate into lower power consumption, which is particularly important for battery-powered applications in devices which incorporate microdisplays.
  • a microdisplay which includes a liquid crystal device (LCD) and operates in either reflective or scattering modes.
  • LCD liquid crystal device
  • Figure 4A illustrates a cross-sectional view of a liquid crystal device while Figure 4B illustrates a top-down view of a liquid crystal device.
  • the LCD 32 is composed of a substrate 34 having a plurality of electrodes 36 corresponding to pixels, liquid crystal 38 arranged on the substrate 34, and a counter electrode 40 arranged on the liquid crystal 38.
  • the liquid crystal is caused to align or relax at each pixel in response to local electric fields applied across the liquid crystal between the pixel and the counter electrode.
  • the potential at each pixel on the substrate is determined by the corresponding display circuit, the design of which is the subject of the present invention. Sequentially changing the potentials at any or all of the pixels on the substrate via the corresponding display circuits causes the LCD as a whole to form a composite image when properly illuminated.
  • a sub-image is observed when the LCD is illuminated after allowing sufficient time for the liquid crystal to align or relax according to the voltage pattern on the pixels.
  • a multicolor image may be produced by performing the following sequence sequentially with different colored illumination sources: (1) turning off illumination; (2) stimulating the liquid crystal with a voltage pattern on the pixels for a first sub-image or field; (3) waiting a sufficient period of time for the liquid crystal to form the source object; and (4) illuminating the liquid crystal. The above sequence is repeated for each light source present.
  • Figure 5 illustrates a backplane integrated circuit (backplane IC) which may be used in a display matrix such as a LCD microdisplay.
  • backplane IC backplane integrated circuit
  • the backplane IC 42 integrates into a single electronic circuit a display matrix 44, programmable registers 46 that generate the control signal logic 48 provided to the display matrix 44 and other timing functions, and an interface 50 to a source of image data.
  • a display matrix for this backplane IC may be sized to include an 800 by 600 two-dimensional array of display circuits.
  • the display circuit for a backplane IC is composed of two or more memory cells and a selector circuit.
  • the memory cells maybe conventional Static Random Access Memory (SRAM) cells composed of six transistors each, though the use of other digital memory cells is intended to fall within the scope of the present invention.
  • SRAM Static Random Access Memory
  • SRAM for the memory cells facilitates fabrication of the IC.
  • SRAM can be fabricated by the same process steps and fabrication tools as the selector circuit.
  • the selector and SRAM may be formed on a substrate with one poly-silicon layer and metal layers. This obviates the need for different fabrication processes for the memory and logic components of the IC, and reduces the number of mask levels required in fabrication.
  • the SRAM cells may be called RED CELL, GREEN CELL, and BLUE CELL, respectively.
  • the cells are addressed for reading and writing via WORD signals.
  • Data is transferred into and out of the SRAM cells via BIT and BIT BAR signals.
  • the cells can share the BIT and BIT BAR data signals and have separate address signals, possibly named RED WORD, GREEN WORD, and BLUE WORD, respectively. Or the cells can share a WORD address line and have separate data signals, such as RED BIT and RED BIT BAR, etc.
  • the selector is accomplished with switches that connect the SRAM cells to the pixel at the output of the display circuit.
  • the switches may be pass gates controlled by RED STROBE, GREEN STROBE, and BLUE STROBE signals, respectively.
  • RED STROBE signal When the RED STROBE signal is asserted, the voltage stored in the RED CELL is transferred to the pixel.
  • the GREEN STROBE and BLUE STROBE signals operate analogously.
  • the various WORD and STROBE signals are provided to each display circuit based on programmable registers inside the backplane IC but outside the display matrix.
  • each cell is connected to a individual strobe line. This design allows each cell to be strobed individually, thereby minimizing the power consumed in the operation of the display system and optimizing the operation speed of the display.
  • multiple cells are connected to individual strobe lines.
  • This design reduces the wiring density of the IC.
  • the display system can be designed to have a desired level of wiring density. It is noted that power efficiency and operation speed decrease as wiring density decreases. The particular wiring density that is preferred will depend upon the particular application for which the display is being designed and the wiring density, power efficiency, and operation speed that are required.
  • Figure 6 illustrates an embodiment where the total number of strobe lines in the display system is reduced from a 1 : 1 strobe line to memory cell ratio by increasing the number of memory cells connected to individual strobe lines.
  • Figure 6 illustrates an embodiment where each strobe line corresponding to a color and is connected to a plurality of cells of the respective color so that each STROBE signal controls a plurality of cells of the respective color.
  • the figure depicts four display circuits 600, 602, 604, 606 with three SRAM cells per display circuit.
  • Each display circuit 600 has a RED CELL 608, a GREEN CELL 610, and a BLUE CELL 612.
  • the four RED CELLS (608A-D) are connected to a single RED STROBE 614 by connection 614A
  • the four GREEN CELLS (610A-D) are connected to one GREEN STROBE 616 by connection 616A
  • the four BLUE CELLS (612A-D) are connected to one BLUE STROBE 618 by connection 618A.
  • the RED STROBE signal is activated, the voltages stored in the four RED CELLS connected to the RED STROBE are transferred to their respective pixels.
  • the GREEN STROBE and BLUE STROBE signals operate analogously.
  • the display matrix of the present invention can be designed to be employed in a wide variety of electronic devices in which a real or virtual image needs to be displayed, hi particular, the display matrix is intended for use in small sized electronic devices such as portable computers, personal communicators, personal digital assistants, modems, pagers, video and camera viewfinders, mobile phones, television monitors and other hand held devices.
  • the display matrix is employed in a virtual image display system where the display matrix forms a source object which is then magnified by one or more magmfication optics.
  • the display matrix is preferably sized to be a microdisplay.
  • Figures 7A-7C illustrate three examples of a virtual image display which include a display matrix according to the present invention, and one or more magnification optics.
  • Figure 7A illustrates a virtual image display system which includes a display matrix 62 which projects an image onto a back surface 63 of the first magnification optic 64 which reflects (at least partially by total internal reflection) the image to a surface 65 having a magnification function and a reflection function.
  • the surface 65 reflects the image to a second magnification optic 66 and to an observer 67.
  • Figure 7B illustrates a virtual image display system which includes an illumination source 69 reflects light off the microdisplay system 62 to a beamsplitter 71 which reflects an image formed by the microdisplay to a surface 73 of the first magnification optic 64 having a magnification function and a reflection function.
  • the surface 73 reflects the image through the beamsplitter 71 to a second magnification optic 66 and to an observer 67.
  • Figure 7C illustrates a virtual image display system which includes an illumination source 75 which reflects light off the microdisplay system 62 to a back surface 77 of a first magnification optic 64 which reflects the light to a beamsplitter 79 which reflects the light to a surface 81 of the first magmfication optic 64 having a magnification function and a reflection function.
  • the surface 81 reflects the light through the beamsplitter 79 to a second magnification optic 66 and to an observer 67.
  • Examples of virtual image display systems which can be used include but are not limited to the virtual image display systems described in U.S. Patent Nos.: 5,625,372; 5,644,323; and 5,684,497.
  • One feature of the present invention is the efficiency with which the display matrices of the present invention may be operated in a field sequential color (FSC) mode, i a typical FSC mode, a composite image is formed through the repetition of a sequence of different color sub-images, typically red, green, and blue sub-images.
  • FSC field sequential color
  • a composite image is formed through the repetition of a sequence of different color sub-images, typically red, green, and blue sub-images.
  • the one or more sub-images 26 corresponding to a color is called a field 28.
  • a single sequence of the different fields is called a frame 29.
  • Sub-image data generally differs by field 28 in an FSC system, hi the special case where the data is identical across the red, green, and blue fields, the composite image appears monochrome with gray levels.
  • Data transfer requirements for an FSC mode are more stringent than for a general system for sequentially formed composite images.
  • the total length of time that a sub-image may be displayed, from the end of the display of the prior sub- image to the end of the display of the current sub-image, is limited by the minimum frame rate necessary to avoid flicker.
  • the data for a particular sub-image must also be present in the display matrix from the beginning to the end of the sub-image. The quality of the image produced is reduced if part of the one color frame is displayed while a part of another color frame is displayed.
  • Figure 8 A illustrates the data transfer and display sequence of a prior art display matrix which employs a single memory cell per pixel.
  • the entire data transfer for a sub-image takes place during a time period T DT after the time period for displaying the prior sub-image T DI - I and before the time period for displaying the current sub-image, also T DI - 2 - hi order to avoid flicker, the period of time available for data transfer and display is limited by the minimum frame rate T MFR -
  • the need to transfer the entire data for a sub-image during the time period T DT which is less than the minimum frame rate T MFR time period creates a high instantaneous bandwidth requirement on a prior art display matrix operating in an FSC mode.
  • the average bandwidth requirement which is a direct function of the frame rate as well, is accordingly high.
  • Figures 8B and 8C illustrate data transfer and display sequences that may be used when a display matrix according to the present invention which employs two or more memory cells per pixel is operated in an FSC mode.
  • a display matrix employs two or more memory cells per pixel, it is possible to store data for more than one sub-image, whether of the same or a different field, hi one embodiment, the display matrix includes sufficient data to store all of the individual sub-images of a field or the entire composite image simultaneously.
  • the use of two or more memory cells per pixel in a display matrix significantly reduces the instantaneous bandwidth requirement of the system.
  • the data for one particular field sub-image is the same as the that for the next sub-image of the same field, the data for the next sub-image does not need to be transferred at all, reducing the average bandwidth requirement.
  • the present invention is intended to encompass display matrices where each memory cell consists of one bit or more than one bit of memory.
  • a digital display system refers to a display system where a single binary bit of memory is associated with each memory cell.
  • the selector outputs a binary value as a function of the data stored in the memory cells, and binary control signals are provided to each display circuit.
  • binary is meant a two-level voltage system, where each voltage can be represented by either a 0 or a 1.
  • gray levels within a particular color field may be attained by multiplexing different sub-images of that field. By showing certain sub- images of a field longer than other sub-images, certain sub-images are rendered more significant to the composite field image than other sub-images.
  • the first memory cell in each display circuit may correspond to the most significant bit (MSB) of the binary representation of the grayscale values for a particular field.
  • the second memory cell in each display circuit may correspond to the least significant bit (LSB).
  • the first memory cell may be the most significant bit (MSB), the second memory cell the second significant bit (SSB), and the third memory cell the least significant bit (LSB).
  • a multiple grayscale field may be formed.
  • One bit maybe displayed for a larger portion of the time that a particular frame is displayed either by displaying that bit longer, as illustrated in Figure 9A, or by displaying that bit more frequently, as illustrated in Figure 9B.
  • a four-level grayscale system is achieved in a two bit system when the MSB sub-image is displayed for twice as long as the LSB sub-image.
  • the total display time for both sub-images equals the display time for the field.
  • the number of gray levels possible is equal to 2 N , when N is the number of sub-images.
  • One particular sub-image corresponds to the MSB ofthe binary representation ofthe gray level; another to the LSB.
  • Sub-images corresponding to the 2 nd (2 nd SB), 3 rd (3 SB), and further significant bits ofthe binary representation are possible for systems of more than two sub-images.
  • the total duration of one sub-image is proportional to 1 / 2 M , where M is the significance ofthe bit corresponding to the sub-image.
  • the total duration for one sub-image may be continuous or broken into smaller time slices for interleaving with other sub-images.
  • the total number of perceived colors possible in a system is the product of the number of gray levels for each constituent color field. For example, 64 colors may be generated by a three color system where each color has a four degree gray level (4x4x4).
  • two memory cells are present in each display circuit. Once data has been loaded into the display matrix, it is possible to form either a dichromic composite static image or a four-level grayscale monochromic composite static image.
  • one memory cell of each display circuit contains the data corresponding to one color field and to the location ofthe display circuit within the image.
  • the second memory cell contains the corresponding data for the second field.
  • the memory cells of each display circuit contain the MSB and LSB ofthe image data associated with a single color field.
  • the MSB and LSB ofthe image data associated with a single color field.
  • each memory cell in a display circuit ofthe present invention corresponds to a sub-image.
  • the sub-images corresponding to different memory cells are output from the display matrix according to the control signals provided to each display circuit.
  • the sub-images can have any order and may be displayed for any amount of time. For example, a particular sub-image may be displayed more frequently than other sub-images, as in the case ofthe MSB sub-image.
  • the sub- image may also be displayed for a longer period of time than other sub-images.
  • the assignment of sub-images to different memory cells may be dynamic.
  • the assignment ofthe first, second, and third memory cells as the MSB, SSB, or LSB can be changed, field to field and/or frame to frame.
  • the first memory cell of every display element may at one time be assigned to the MSB sub-image ofthe red field and at another time to the LSB sub-image ofthe green field.
  • the display image data is transferred to the display matrix from a frame buffer.
  • the frame buffer is typically external to the display system in the sense that the frame buffer is a separate component from the display matrix.
  • an external frame buffer The purpose of an external frame buffer is to house an entire frame of data and act as an intermediary between some sort of processor, which initializes and modifies the image in the frame buffer, and the display matrix, which displays the image or part thereof.
  • the data transfer bandwidth between the processor and the frame buffer varies according to the rate of change in the content ofthe image. For example, a static, monochromic image requires essentially zero bandwidth. In a display system operating in an FSC mode with a high frame rate, the bandwidth requirement remains high regardless of how static the image may be.
  • a display matrix ofthe present invention can also be used to store multiple sub-images, for example all the sub-images of a single color field as opposed to an entire frame.
  • a display matrix ofthe present invention operated in an FSC mode, it is possible to house an entire frame of data in the display matrix itself.
  • the advantage of housing an entire frame of data within the display matrix is that the external frame buffer may be completely eliminated from the display system, saving not only a component but also a great deal of bandwidth. Only the bandwidth between the processor and the display matrix would remain, hi contrast, operating a prior art display matrix in FSC mode, there is no room within the display matrix to house multiple sub-images simultaneously, necessitating an external frame buffer.
  • the display matrix behave like an external frame buffer from the processor point of view, hi particular, the display matrix should behave like a memory: random access addressable as well as readable and writable.
  • the display matrix of prior art typically is not random access addressable and is only writable.
  • the primary interface to the display matrix from the source of image data can mimic that of a synchronous SRAM.
  • the clocked interface includes a general backplane IC chip select and a read / write signal.
  • An internal write buffer supports consecutive writes to the memory cells in the display matrix and to programmable registers outside the display matrix.
  • the latency to the first read data from either the memory cells or the programmable registers is a fixed number of cycles. Data on consecutive cycles is returned on burst reads.
  • the length of burst accesses can be programmed to be 1, 2, 4, or 8 words, where the length of a word is defined as the data bus width. The latter is initialized to 8 bits on reset, but can be reprogrammed to 8, 16, or 32 bits.
  • a total of 20 address lines can be used to specify the destination of a read or write to the memory matrix.
  • the secondary interface can include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock, along with 8, 16, 24, 32, or some other intermediate number of bits of data.
  • the secondary interface can be used to scan data into the display matrix only, with no capability to read data from the matrix.
  • ROM read only memory
  • FPGA field programmable gate array
  • external frame buffer external frame buffer
  • An aspect ofthe present invention relates to layout designs for positioning a plurality of display circuits adjacent pixels of a corresponding display element. For instance, in a display system ofthe present invention, there are multiple memory elements per pixel. As the number of memory elements per pixel increases, it becomes increasingly difficult to position the display circuit including the plurality of memory elements adjacent the pixel. It is thus necessary to design the layout of the display matrix to accommodate for display circuits which do not fit within the spatial confine, or "footprint", ofthe corresponding pixel.
  • Figure 10 illustrates two rectangular display circuits 202 A, 202B placed under two pixels 204A, 204B.
  • Each display circuit is at least partially located within the footprints of both pixels. Additionally, each pixel is placed within the footprints of both display circuits. However, each ofthe display circuits has an electrical connection to only one ofthe pixels 206A, 206B, thereby preserving the correspondence of one pixel to one display circuit in each display element.
  • One feature ofthe layout designs illustrated in Figures 10-12 is the positioning of multiple address lines under each pixel or under each row of pixels.
  • each ofthe display circuits In order to facilitate random access to the memory elements of each display circuit, each ofthe display circuits must be separately addressable. This requires each display circuit to be connected to an address line. When two or more display circuits are placed in the footprint of a pixel, the same number of address lines are placed under the pixel, one for each display circuit.
  • Each ofthe display circuits 202A and 202B is connected to a single address line, 208A and 208B, respectively. But since both display circuits lie within the footprint of one pixel 204A, there are two address lines running under one row of pixels 212 in the display matrix.
  • the layout illustrated in Figures 10-12 were multiple display circuits are positioned within the footprint of a pixel provides a further advantage of enabling a substantial decrease in the number of data lines (e.g., bit and bit bar lines) used in the display system.
  • data lines e.g., bit and bit bar lines
  • the layout also results in an increase in the number of address lines that are used in the display system in order to preserve random access to the memory elements in the display system.
  • the reduction in the number of data lines is more significant.
  • Each display circuit in the display matrix connects to a BIT line and a BIT BAR line.
  • each display circuit within the footprint of a pixel can be connected to the same BIT and BIT BAR lines. This allows for a net reduction in the number of BIT and BIT BAR lines connected entering the display system.
  • display circuits 208 A, 208B are both located under pixel 204A and pixel 204B.
  • An address line is provided for each display circuit, shown in the figure as address lines 208A, 208B.
  • a single pair of data lines (BIT 210A and BIT BAR 210B) are used for both display circuits.
  • BIT 210A and BIT BAR 210B are used for both display circuits.
  • Figure 11 illustrates another embodiment where there are two rows and four columns of pixels (300A, 300B, 300C, 300D and 302A, 302B, 302C, 302D).
  • Each row of pixels is divided into two pairs with a pair of display circuits (304A-H) being positioned underneath the pair of pixels, as in Figure 10.
  • Two address lines (306A- D) are positioned under each row of pixels and a pair of data lines (308A-D) are provided for each two columns of pixels.
  • a total of 8 data and address lines are employed.
  • BIT and BIT BAR lines were used for each column of pixels, and an address line were used for each row of pixels, 10 data and address lines would be employed.
  • Figure 12 illustrates yet another embodiment where there are five display circuits (402A-E) and five address lines (404A-E) running under the display circuits. Meanwhile, a single set of data lines (406A-B) are used for the five display circuits. As can be seen, only 7 data and address lines are used. By contrast, if one were to use 1 address line and 5 it would be connected to 3 pairs of data lines, one pair per memory cell. Since there are 800 columns, there would need to be 4800 data lines. Combined, a total of 5400 lines are needed.
  • each display circuit includes 5 memory cells. Assume each display circuit is positioned within the footprint of each pixel. According to this layout design, there would be 600 address lines (1 address line per row) and 8000 data lines (800 columns x 2 lines per memory cell x 5 memory cells) for a total of 8600 lines.
  • An aspect ofthe present invention relates to the use of local decoding of row addresses in the display system to reduce the number of address lines, or "word lines," in the display system.
  • decoders are inserted at periodic intervals in the display matrix. These decoders are connected to surrounding display circuits, so that each decoder is connected to rows ofthe display matrix.
  • Each decoder receives a word line, two sub-word lines, and an enable line.
  • the sub-word lines supply two bits, a Most Significant Bit (MSB) and a Least Significant Bit (LSB) which provide an offset for selecting one ofthe rows connected to the decoder. This obviates the need to connect an address line to each ofthe rows connected to the decoder.
  • the enable bit is used to minimize power consumption.
  • Figure 13 is a schematic illustration of local decoding.
  • the local decoder 500 is connected to four rows of display circuits 502A, 502B, 502C, 502D in the display matrix.
  • the rows of display circuits connected to the local decoder 500 are referred to herein as a cluster of display circuits.
  • the third line entering the local decoder from above is an enable bit 504, intended to save power.
  • the data lines serve as sub-address lines by controlling which display circuits are being operated by the local decoder.
  • the two data lines MSB and LSB provide an offset for selecting one ofthe rows connected to the decoder.
  • Each value ofthe (MSB,LSB) pair connotes exactly one ofthe rows entering the decoder. For instance, "00" may denote the first row 502A, "01" the second row 502B, "10" the third row 502C, "11" the fourth row 502D.
  • the connection ofthe rows to the decoder, coupled with the offset provided to the local decoder, can be used to reduce the number of address lines connected to the rows ofthe display matrix. In particular, the number of address lines may be reduced by a factor equal to the number of values that can be denoted by the offset. To illustrate, consider Figure 13.
  • each of these four rows may be selected by one ofthe four values ofthe offset.
  • the display system needs only one word line connected to the decoder, and a pair of sub-word lines to select one of those four rows connected to the decoder.
  • the number of address lines used in the display system can be reduced by a factor of four.
  • the local decoders are placed after every 16 pixel columns.
  • the number of address lines are reduced by a factor of four, to 150, resulting in 450 fewer address lines.
  • the addition ofthe 150 offset and enable lines is countered by a decrease in 450 address lines.
  • the insertion of local decoders also confers benefits during fabrication ofthe display system, as it obviates the need to fabricate word lines in metal.
  • the present embodiment eliminates the need for global word lines which span each row of display circuits, as global word lines are replaced with relatively short interconnects between decoders.
  • the relative brevity ofthe interconnects allows them to be fabricated in poly-silicon rather than metal.
  • the absence of metal word lines in the IC results in improved packing density, and frees space for other metal interconnects.
  • the display circuit layout designs described above, for example with regard to Figures 10-12, can be combined with local decoding to produce a drastic reduction in the number of address and data lines entering the display matrix.
  • the number of data lines can be significantly reduced by connecting data lines to multiple data circuits.
  • the resulting increase in address lines can then be diminished by replacing global word lines with local decoders.
  • One mode referred to herein as the "Power Miser Mode” relates to a mode where writing to the display matrix is minimized, there reducing the amount of energy consumed by the display matrix.
  • Another mode of operation referred to herein as the “Color Rich Mode” relates to a mode where data is written to memory cells forming one bit plane while memory cells of another bit plane are used to display an image in order increase the number of sub-images that can be used to form a composite image. By being able to increase the number of sub-images that can be used to form a composite image, a greater number of colors may be formed by the display matrix.
  • Yet another mode of operation referred to herein as the "Color Mixing Mode,” involves operating a display matrix in a Power Miser Mode and Color Rich Mode at the same time.
  • FIG. 14 One mode of operating a display matrix according to the present invention is illustrated in Figure 14 in which a processor 54 interfaces directly with the display matrix (backplane IC) 42.
  • This mode is refe ⁇ ed to herein as power miser mode because the image is initialized and modified directly in the display matrix memory without the use and associated power consumption of an external frame buffer.
  • the backplane IC is fundamentally digital in nature, component and power consumption costs associated with digital-to-analog converters or other analog circuitry is avoided.
  • the backplane IC offers several functions in support of power miser mode.
  • the synchronous SRAM interface on the chip coincides with the memory model assumed by typical processors.
  • the chip also offers capacity for a red, a green, and a blue bit plane, the minimum necessary for a display matrix to operate in an FSC mode.
  • the chip can also be programmed for FSC control, a sequence such as the following:
  • the RED, GREEN, and BLUE cells of each display circuit are filled with the MSB, SSB, and the LSB ofthe corresponding image data.
  • the three bit planes can be strobed in a variety of time modulation schemes to achieve the eight levels of grayscale in the color ofthe single illumination source.
  • One possibility is to strobe the bit planes in RMS fashion using distributed binary coding as described later.
  • Scrolling in the present invention consists of shifting a scroll region horizontally or vertically by a pixel.
  • the contents of a scroll buffer are used to fill in the area vacated by the shift.
  • the scroll region can be an entire bit plane or portion thereof.
  • Figure 15A illustrates an address map including scroll buffers.
  • the address bus illustrated in the figure is 20 bits wide. Bits A 6 through A 0 specify the column address of a byte, Aj 6 through A 7 its row address, and A 18 through A 17 its bit plane address.
  • This address scheme assumes the three SRAM cells in each display element have been configured for separate address (WORD) signals.
  • the address space ofthe display matrix encompasses 0-99 in the column address, 0-599 in the row address, and 0-2 in the bit plane address.
  • Bit A 19 is the programming bit.
  • Buffers outside the active region are allocated for scrolling.
  • the address space of a horizontal scroll buffer encompasses 100 in the column address and 0-599 in the row address.
  • the address space of a vertical scroll buffer encompasses 0-99 in the column address and 600-607 in the row address.
  • a scroll procedure may comprise the following steps:
  • the scroll buffer for a particular direction and bit plane is modified through processor reads and writes to its address space.
  • the scroll region programming registers are modified as necessary.
  • the scroll command is issued by writing to the appropriate register.
  • the backplane IC begins scrolling.
  • the scroll region is the area over which data will be shifted.
  • the scroll region is defined by the coordinates of its upper left (X U , Y U L ) and lower right (X R , Y R ) corners.
  • the coordinates in the present invention are specified with byte granularity, so that the possible values are 0-99 in the X-direction and 0-74 in the Y- direction. Values greater than 99 in the X-direction and 74 in the Y-direction are prohibited. Data outside the scroll region will not be affected by the scrolling operation.
  • FIG. 15B A second embodiment of scrolling is illustrated in Figure 15B.
  • a scroll region is first defined, Figure 15B the region is eight pixels high by eight pixels wide. However, it can be any region within the display matrix on a one-pixel boundary in the vertical direction and a two pixel-boundary in the horizontal direction.
  • the scrolling operation can move the contents of the scroll region up or down by one pixel or left or right by two pixels without affecting any of the data outside ofthe scroll region.
  • one row of pixels is always left unchanged by vertical scrolling and two columns of pixels by horizontal scrolling. These unchanged pixels must be overwritten by the new information from the external system to complete the scroll.
  • Scrolling is an example of hardware assistance for a graphical operation that is outside the operation of display matrices of prior art.
  • the external frame buffer within the display matrix ofthe present invention in power miser mode, a wide variety of hardware assistance functions for image modification become possible and useful within the display matrix.
  • FIG. 16 A second mode of operating a display matrix according to the present invention is illustrated in Figure 16, in which an external frame buffer 56 is placed between the processor 54 and the display matrix (backplane IC) 42.
  • This mode is referred to herein as color rich mode, because the multiple bit planes in the display matrix are used to generate multiple levels of grayscale in each ofthe color fields. For example, when three bit planes are used, eight levels of grayscale (2 3 ) are produced in each of three color fields for a total of 512 colors (8 3 ) in FSC operation.
  • Figure 17 illustrates part ofthe above sequence.
  • the numbers 0, 1, and 2 are used to represent the RED, GREEN, and BLUE bit planes, respectively.
  • Each color field in the figure has been divided into a RECOVERY and an ACTIVE period.
  • the length ofthe ACTIVE period equals the length of time that the LEDs are turned on.
  • a detail contained in the figure though omitted in the above sequence is that the turn on time for an LED may be delayed from the start ofthe ACTIVE period.
  • the ACTIVE and RECOVERY periods may have different length. The sum of their lengths is determined by the length of a field, which is typically one-third the length ofthe frame.
  • the strobing ofthe bit planes both before and after an LED is turned on in the above sequence corresponds to strobing in the RECOVERY and ACTIVE periods in the figure. It has been found through experiment, that during the RECOVERY period, strobing the correct value for the color field is better than driving a constant binary 1 or 0 on the pixel.
  • Gray levels in a particular color field are produced by multiplexing sub- images temporally at a very fast rate.
  • the sub-images correspond to bit planes and multiplexing is the same as strobing.
  • RMS Root Mean Squared
  • strobing algorithms are possible to achieve a certain gray level. For instance, in a 3 bit-plane system, a conventional coding scheme might divide up an interval, such as the RECOVERY or ACTIVE period, into seven equal parts, and assign the MSB plane to the first four parts, the SSB plane to the next two parts, and the LSB plane to the last part. Then a gray level 4 would be achieved by a 1111000 sequence, a 5 by a 1111001 sequence, etc.
  • distributed binary coding One algorithm that has been found empirically to have a better RMS effect than the above conventional coding scheme for a particular LCD is called distributed binary coding.
  • a better RMS effect refers to the gradation in voltages driven on the liquid crystal being more uniform.
  • the interval is first always divided into (2 N - 1) time slots.
  • the MSB plane time slots are determined first.
  • the MSB plane is always placed in the first time slot and every other time slot there after.
  • the 2 nd SB plane time slots is calculated next.
  • the SSB plane is placed in the first available time slot and every fourth time slot thereafter.
  • the 3 rd SB occupies the next available time slot and every eighth slot thereafter, and so on until the LSB (N th ) plane is place in the middle time slot.
  • the formula is ⁇ MSB, 2 nd SB, MSB, 3 rd SB, MSB, 2 nd SB, LSB, MSB, 3 rd SB, MSB, 2 nd SB, MSB ⁇ .
  • the ability ofthe display system ofthe present invention to perform distributed binary coding is a strong example of one ofthe advantages that the display circuit ofthe present invention provides.
  • the grayscale level is strobed twice in one color field, once in the RECOVERY period and once in the ACTIVE period, for a total of 14 time slots. In a system with only one memory cell per display circuit, fourteen bit planes would have to be loaded in order to strobe during 14 different time slots. This would require a very high bandwidth transfer rate and pixel refresh rate.
  • the present invention it is possible to alternate the assignment of MSB memory matrices for consecutive color fields.
  • This enables the display matrix to further take advantage of having more than one memory cell in each display circuit.
  • the ⁇ RED, GREEN, BLUE ⁇ memory matrices were assigned to ⁇ MSB, SSB, LSB ⁇ for the RED field, while in the ensuing GREEN field, the assignments were switched to ⁇ LSB, SSB, MSB ⁇ .
  • This algorithm is driven by the nature of distributed binary coding, in which the LSB plane always falls in the middle time slot while the MSB plane is always at the beginning.
  • the memory plane can be used for the first plane needed by the GREEN field, which is the MSB plane.
  • the bit planes as MSB, SSB and LSB, etc., it is possible to increase the number of bit planes which can be written to memory and strobed.
  • the backplane IC can include logic for performing a variety of algorithms. Such software control can also accommodate timing parameter changes which may be necessitated by temperature conditions or other factors.
  • Interrupts to the external frame buffer can also be provided to trigger the transfer of data to the next available memory plane.
  • a third mode of operating a display matrix according to the present invention relates to the overlay of a color rich region on a power miser background. This mode of operation is illustrated in Figure 18.
  • a window of high information content can be formed without incurring the bandwidth and power consumption costs associated with full-screen color rich operation.
  • the reduction in bandwidth requirements improves the compatibility ofthe display matrix with video applications.
  • An example of a color mixing procedure that may be employed is as follows:
  • the power miser mode is specified to be either 3 color fields at 1 -bit/field or 3 -bit monochrome, by writing to the appropriate configuration register as necessary.
  • the window region is the area over which data will be displayed in color rich mode.
  • the area around the outside ofthe window region operates in power miser mode.
  • the window region is defined by the coordinates of its upper left (X U , Y UL ) and lower right (XLR, Y LR ) corners.
  • the coordinates must be specified with byte granularity, so that the possible values are 0 - 99 in the X-direction and 0 - 74 in the Y-direction. Values greater than 99 in the X-direction and 74 in the Y-direction are prohibited.
  • the present invention also relates to the incorporation of various algorithms into memory resources and their utilization in display systems to control data flow and operation of a display system.
  • Figure 19 shows a block diagram of a display system that may be used in the present invention. It should be noted that other configurations of displays, including those set forth above, may be used in practicing various embodiments ofthe present invention.
  • ASIC 802 is designed to take standard, bit-mapped data from the host system, either directly from the microprocessor 804 or by an interface circuit (not shown), and separate this data into separate color components (e.g., red, blue and green). These components are stored as separate color sub-images so that they may be supplied to the backplane 806 to generate each red, blue and green image (color fields) needed for sequential color definition.
  • various types of image processing such as spatial dithering, may be applied to the data either before or after the image data is separated into the color fields.
  • This storage can either take place within the ASIC chip 802 or on a separate frame buffer chip 808 (memory) connected to the ASIC.
  • a second feature ofthe ASIC 802 is its ability to rapidly send each color field to the backplane 806 in a specific sequence as may be required for a given algorithm.
  • the algorithms ofthe present invention involve different applications of individual bits of color field data, depending on the method. These various methods have been optimized for color generation under various device designs, environmental conditions and color requirements, and refresh rates. Data transfer bit sequencing, timing and clock speeds can be set by the ASIC chip.
  • this architecture allows for voltages supplied to the counter electrode 810 to be offset so that only the change in voltage required for liquid crystal transitions need be applied.
  • the counter electrode offset voltage must be supplied for both positive and negative liquid crystal voltages, as needed to possible negative effects caused by steady state (DC) voltage components.
  • the counter-electrode 810 signals originate on the backplane chip 806 and the voltage levels are set by an additional driver chip (not shown in Figure 19).
  • the ASIC chip 802 can work with the backplane 806 to determine when and how the counter-electrode voltage is altered, as will be discussed in the description ofthe drive methods.
  • a black and white image may be presented on a field sequential color display by presenting the same image bit pattern during Red, Green, and Blue sequential illumination. Pixels optically off will appear black, while those optically on will appear white.
  • the image data requires only 1 bit per pixel and this data may be sent to the backplane once for all three color fields.
  • a programmable 2x3 bit lookup table in the ASIC 802 provides a means of mapping colors to substitute for black and white image information, i.e. yellow text on a blue background.
  • the table contains one bit for each primary color (RGB) to substitute for "black” bits, and one bit for each primary color to substitute for "white” bits, in the monochrome image data.
  • the backplane then stores the substituted 3 bit color for each bit written to it.
  • the amount of data written to the backplane is still one bit per pixel, but the backplane can now present three substituted values, one for each ofthe color fields.
  • the 2x3 bit lookup table need not be restricted to use as color substitution in monochrome images. For higher color applications, this same table can be used as a means of generating a unique LC drive method.
  • a method for suppressing image brightness flicker is referred to herein as the Balanced Binary Color (BBC) method.
  • BBC Balanced Binary Color
  • This method may be used with high color applications where there is a need to suppress image brightness flicker.
  • the method can be used for color images or monochrome images by simply choosing the correct color field sequence. For example, normal color can be obtained by using the method to apply different color sub-images for red, green and blue color fields. The same data for each color field can be used for monochrome images of a black and white nature. Single color images will require only one color field. Other combinations are possible.
  • the core of this method is the way a single bit of color is generated. At this bit level, the method can be applied to other color schemes.
  • each bit is used to generate a voltage across the liquid crystal, and then illuminate the resulting full color field by an LED flash supplied to the full backplane chip image area.
  • the duration ofthe LED pulse provides a binary decoding.
  • the first pulse may be of 1 unit duration and represent the least significant bit of color information.
  • the next bit is then applied and the LED is flashed for 2 units of duration representing the next most significant bit. This is followed by a bit of data and an LED flash 4 units in duration, and so on.
  • the BBC method can be used to reduce viewing artifacts, such as flicker and contrast reduction, due to residual ionic contamination ofthe liquid crystal material.
  • Color depths can range from one to eight or more bits of color per color field. This co ⁇ esponds to from 2 to 256 shades of color for the color field. Consider the example of 4 bits, or 16 shades of color when decoded using binary counting. For a fully digital backplane design, only one bit at a time can be applied to the pixel electrode.
  • One aspect ofthe invention relates to how each bit is applied at the pixel electrode and counter electrode prior to and during the LED flash.
  • each bit used to generate color is applied in a manner that uses either zero applied voltage or equal plus and minus voltage pulses such that no net DC voltage component is applied.
  • Previous methods employing an analog backplane have not been able to do this, usually due to the need to apply an analog voltage at each pixel.
  • An analog voltage is not easily inverted and typically is inverted only on the subsequent frame (consisting ofthe full 3 color fields).
  • Digital methods have successfully applied inverted pulses at the bit level by means of alternating control voltages over the entire image area.
  • the first two values, Sub[l] and Sub[2] could also be viewed as "data" and "not data".
  • the Sub[3] bit is the same regardless of input data. This data, when switched to the backplane pixels causes all pixels to go to zero volts. Because the Sub[3] bit plane is always written with O's, new image data can be written (changing Sub[l] and Sub[2]) while the Sub[3] bit plane is switched to the pixel array without affecting the LC.
  • Figure 20 illustrates single color bit dynamics. As shown in Figure 20, at the beginning of each bit of color, all pixels in the image array are switched to zero volts on the pixel electrode.
  • the command for this action originates in the ASIC chip 802 and is carried out by the backplane 806, but may also be carried out entirely by the backplane 806 if circuit densities permit sufficient control and storage on the backplane 806 so as to negate the need for a separate ASIC chip 802.
  • the liquid crystal molecules are strongly switched into their normal state by the anchoring forces supplied by the alignment layers located at the pixel electrode and the counter electrode.
  • the normal state may result in either a normally bright or a normally dark state in the full display system, depending on the light path, polarizers employed and the type of electro-optic liquid crystal mode.
  • the BBC method works effectively in either case.
  • This zero voltage phase the most rapid possible return to the normal state is realized since any applied voltage during this period would only serve to slow the return of all pixels due to counter acting forces tending to orient the molecules away from this state.
  • This zero voltage phase lasts for a time long enough to allow the liquid crystal molecules to mostly relax to the normal state and may be on the order of a millisecond in duration.
  • two bits of data are supplied to the local storage at each pixel location. These data bits are complimentary and represent a 01 or a 10 pair. For purpose of example, suppose that we associate a 01 pair with a dark pixel and a 10 pair with a bright pixel. Let us further suppose that the normal state is bright. Then zero 01 pair, for example, can be associated with a Vdd pixel voltage followed by a zero pixel electrode voltage. During this time, the counter electrode will first be set at -Nb (during the pixel "0") and then at Vdd+Vb (during the pixel "1"). The result will be a high voltage of magnitude Vdd+Vb applied during the full data phase.
  • the result is a balance ofthe applied voltage, and the resulting electric field, at each pixel and for each individual bit comprising the color image.
  • This allows extremely little time for ion migration to occur and affect the desired performance. Since these effects can occur on timescales associated with a single polarity of applied voltage, this method can reduce such timescales to the sub-millisecond range. Contrast this to the analog method where a single polarity of applied voltage is applied during each color field. The polarity is not reversed until the next full color frame. Thus a 60 frame per second analog display would see a balanced voltage pulse applied at a rate of only 30 times per second since 2 frames are necessary.
  • the BBC method balances the applied voltages over timescales up to 50 times faster or more, hi fact, extremely high speed operation, with multiple alternating drive voltage swings during each bit, could be achieved in situations where the electronics can support this operation.
  • Figure 21 illustrates how the BBC method is used to produce a single RGB
  • the top curve 2102 shows the voltage at the liquid crystal.
  • the middle curve 2104 shows the liquid crystals response to this voltage.
  • the bottom curve 2106 shows the LED flash sequence with binary weighted flash duration.
  • a single full frame of red, green and blue is shown for the case were 3 bits of data are applied for each ofthe red, green and blue colors. This would produce 512 colors total, after the eye and brain ofthe viewer fuses the temporally separate color images.
  • the number of bits in the example is arbitrary. Total time for each color field is approximately:
  • N is the number of bits being displayed per color
  • a display matrix is provided and has a plurality of display elements which can include liquid crystal. Each display element includes a pixel.
  • a plurality of display circuits are electrically connected to a display element.
  • a plurality of memory cells are associated with each ofthe circuits, or form part ofthe circuit, and a selector continuously electrically connected to more than one ofthe plurality of memory cells, the selector outputting to the pixel data from one memory cell at a time.
  • Peripheral control circuits preferably control read and write operations to the memory cells.
  • the virtual image display system further includes a light emitting mechanism, which may be a mechanism provided at each pixel, a light modulating mechanism provided at each pixel, and/or an illumination source for illuminating the pixels.
  • a light emitting mechanism which may be a mechanism provided at each pixel, a light modulating mechanism provided at each pixel, and/or an illumination source for illuminating the pixels.
  • Logic suppresses image flicker utilizing balanced binary color. The same data can be used to display monochrome and color information.
  • each memory cell is divided into a bit that is used to generate a voltage across the liquid crystal and illuminate a color field using an LED pulse.
  • the duration ofthe LED pulse provides a binary decoding.
  • the pulse can have a set duration and represent a bit of color information, n pulses of n duration may be applied where each pulse represents the n most significant bit of color information.
  • the system reduces viewing artifacts due to residual ionic contamination of the display material.
  • a balance of an applied voltage and a resulting electric field form a color image rapidly which diminishes the time for ion migration and enhances the color image quality.
  • a polarity reversal to a voltage applied to a liquid crystal is decoupled from a display update frequency.
  • Figure 22 is a flow diagram of a process 2200 for generating an image.
  • a display element of a display is switched to zero volts for a first duration of time, where the display element includes a pixel.
  • a first voltage is supplied to an electrode ofthe display element for a second amount of time in operation 2204.
  • the second voltage may be of a substantially equal magnitude and can be supplied to the counterelectrode for about the same time as the aforementioned predetermined time.
  • An illumination pulse is applied to the pixel in operation 2208 for illuminating the display element for a predetermined number of units of duration where the units of duration can be in fractions of milliseconds, etc. This process can be repeated for each bit of color information to be displayed.
  • DCW Digitally Controlled Waveform
  • the DCW method can be performed by controlling individual bit responses using the techniques ofthe BBC method and a simple binary digital application ofthe data.
  • the DCW method is desirable when response speed is important, such as at lower temperatures.
  • the full BBC method is more desirable when it is needed to reduce flicker.
  • the DCW method's response time advantage is made possible by only requiring a single rise and fall time for each color field, rather than one per color bit as needed in standard binary methods.
  • the relaxation time (rise time for a display that is normally white) may or may not occur at zero volts in this method, and so the relaxation time could be somewhat longer. Nevertheless, the method still has a strong overall advantage in terms of response time due to the single waveform approach.
  • the basic shape ofthe waveform 2300 is shown in Figure 23.
  • 4 bits of data are used to display a 3 bit color image field for every pixel.
  • the waveform consists of a single rise and fall waveform incorporating from zero to 4 LED flashes depending on the value ofthe 4 data bits.
  • This scheme is able to fully display the shades of color produced by 3 data bits at the frame buffer.
  • the 3 data bits produce 8 levels of color for the red, blue or green color fields. These 8 levels correspond to values of 0 to 7 in intensity. These 8 levels can be represented by various combinations of LED flashes of weight 1, 2, 2, and 2.
  • the 4 bits supplied by the ASIC to the backplane map the original 3 bits into the new 4 bit space with only a single rise and fall. Table 2, below, shows an example ofthe mapping:
  • the waveform has only a single rise and fall.
  • the exact shape ofthe wavefo ⁇ n only indirectly controls the intensity value. This is due to the use ofthe waveform as an envelope to include the appropriate LED pulses of duration 1 and 2 units. To the degree that the waveform approaches a square wave, the coupling can be very weak. For finite rise and fall times, some interaction between the LED flashes and the waveform shape occurs. Because of this, the first LED flash of unit duration may be made slightly longer to compensate. Other adjustments can be made to achieve the most faithful representation ofthe original 8 levels. For a full color frame of data, similar sequences are strung together for red, green and blue color fields. Note that no special voltage pulses are required. Also, this technique relies on the use of local data storage for each pixel.
  • the write times for these pixels can be invisible as long as the data transfer rate from the ASIC and frame buffer is faster for each bit than either rise or a fall, but not the sum of rise and fall. This is due to the need only to begin or end the single waveform before or after an LED pulse.
  • the total duration of a color field is may be expressed by:
  • max time is the maximum of rise time or fall time
  • the waveforms of Figure 23 include this compensation bit. For cases where the falltime is much less than the risetime, this method can be considerably faster. Consider the case of 0.5 millisecond falltime and 1.0 millisecond risetime. Then the compensated DCW method requires 3 milliseconds per color field and frame rates approximately as high as 111 frames/second can be achieved. Alternately, lower temperature operation can be provided at 60 frames/second. Compare this to 3 bits per color with standard binary methods where 3(1.5milliseconds) are needed per field, resulting in a maximum frame rate of 74 frames/second.
  • Figure 24 is a flowchart of a process 2400 for generating an image.
  • a shade of color is generated by controlling a duration that each display element is optically on. Illumination is applied to illuminate the display element in operation 2404.
  • an additional data bit is used to display a color image field for each pixel.
  • n flashes co ⁇ esponding to the value ofthe data in the memory cell are used to vary the intensity ofthe image display.
  • a single rise and fall time can be used for a color field to enhance image processing, and this does not have to be dependent upon the number of bits employed.
  • the width of a pulse defines a grayscale of a color.
  • the width of a voltage pulse can be used a grayscale of color.
  • one or more illumination pulses can be applied to the display element for illuminating the display element for generating a shade of color, one pulse for each data bit in a sequence of data bits of a color field.
  • RGB levels are stored into the array as analog voltage levels. These levels control directly the voltage applied to liquid crystal between pixel and ITO layer to produce the various shades of color under constant illumination.
  • the voltage level of each pixel is maintained by the active-matrix circuit until a new value is applied to the pixel. Red, green, and blue component sub-pixels are simultaneously applied to the LC as a group to form a single pixel. Variations in color response ofthe LC is accounted for in each pixel, rather than by different voltage levels of ITO.
  • Analog control is far more sensitive to variations in cell gap, temperature, and LC contaminates, requiring high levels of quality control during manufacture.
  • the voltage (at each pixel) is compared to a reference voltage input to the LC to control the duration that the LC is "optically on", such as in a similar manner as set forth above in the section entitled “Digitally Controlled Waveform Method.”
  • a reference voltage input to the LC For each frame (or field when using field sequential color), all pixels in the matrix are allowed to become optically on (or off) prior to the application of illumination.
  • the reference voltage is changed over time, causing each pixel to change state (optically on to off, or off to on) at the precise time that its voltage value matches the reference level.
  • the matching value may instead be a threshold differential value for the transistor used as the analog comparator.
  • Figure 25 A is a diagram of a circuit 2500 associated with one pixel according to an embodiment ofthe present invention.
  • a multiplexer 2501 receives a reference input signal (that represents the reference voltage) and a data input (that will be stored in the capacitor as set forth below).
  • a Digital to Analog (D/A) converter 2502 converts the digital data input signal from the multiplexer to an analog pixel voltage that that is stored in a capacitor 2504. This is the voltage that will be compared to the reference voltage.
  • D/A Digital to Analog
  • the D/A converter generates an analog reference voltage from a digital reference input signal.
  • a comparator 2506 compares the reference voltage to the stored pixel voltage. Upon the reference voltage crossing over the pixel voltage, the comparator indicates such event, such as by switching from high to low, for example.
  • a select switch 2508 is used to send the input reference voltage to the comparator.
  • a pixel latch 2510 receives input from the comparator. If the comparator input indicates that there was a match, the pixel latch will switch to turn the pixel to the opposite state. If the comparator input indicates that there was not a match, the pixel latch will remain unchanged, as will the pixel state.
  • a level shifter 2512 changes the voltage to a higher voltage, such as where the output voltage to the pixel electrode is higher than the operating voltage for other portions ofthe circuit, for example. The higher or lower voltage from the level shifter is sent to a pixel electrode 2514 to change the state ofthe pixel.
  • the analog levels of RGB can be individually selected (multiplexed) over time for presentation to the analog comparator.
  • the output ofthe comparator controls the state of a single pixel, which is illuminated with the appropriate color in the field sequence.
  • the described circuit and method can be applied as an improvement to all existing implementations of analog active matrix LC panels and cells.
  • the described circuit may be equally applicable as an improvement to non-active matrix implementations of analog LC panels and cells as well as to MEMS displays and other types of displays.
  • the described circuit may have direct application to control color levels in OLED displays, hi this case, OLEDs may be driven digitally in their optimum illumination range, resulting in potential power savings and simplified color level control. Additionally, by separating pixel groups into multiple phased cycles, power consumption can be spread evenly over time. These grouped pixels may, of course, be physically interspersed on the display to avoid flicker a low update rates.
  • Figure 25B is a flow diagram of a process 2550 for driving a display.
  • a voltage value is stored in an analog memory associated with each pixel of a display, where each ofthe pixels also has a comparator associated with it. Note that there may be single memory cells for each pixel.
  • a reference voltage and the voltage values stored in the analog memory are applied to the comparators ofthe pixels in operation 2554.
  • the comparators are used to compare the voltage values with the reference voltage for determining which ofthe voltage values matches the reference voltage. The state ofthe pixels whose voltage values match the reference voltage is changed in operation 2558.
  • the display can be an active matrix panel display as well as a non- active matrix display, OLED display, or other type of display.
  • illumination may be applied after the actuation ofthe one or more pixels.
  • the reference voltage can be changed as a function of time to cause each pixel to actuate and de-actuate at a desired time.
  • Groups ofthe pixels can be actuated. In such case, the groups of pixels are actuated in multiple phased cycles. Preferably, the groups are interspersed on the display to avoid flicker at low update rates.
  • the human eye does not perceive light intensity in a linear fashion. If a light source is emitting twice the number of photons as another, it appears brighter to the human eye, but is not perceived as "twice as bright". Human perception of light intensity follows a logarithmic curve. Therefore, to faithfully reproduce an image, gamma correction may be required.
  • each pixel can be made to change state after a particular period of time has elapsed, the gamma of each pixel can be precisely controlled.
  • the level of gray can be adjusted for each pixel to provide gamma correction.
  • FIG. 26A illustrates a method 2600 in accordance with SFD.
  • Such method 2600 may be used for driving a digital display adapted to depict a first number of bits per color field during each frame. See operation 2602.
  • a second number of bits is displayed which is greater than the first number of bits, as indicated in operation 2604.
  • This is accomplished by alternating the display ofthe bits between frames. More information relating to such alternating technique will be set forth hereinafter in greater detail.
  • additional bits of color are displayed without increasing the number of bits per color field during each frame. See operation 2606.
  • the method enables N+M bits of color to be displayed using N digital bits per color field where M is 1, 2, 3 or more.
  • N+M bits of color are applied to N digital bits per color field over several frames where the M bits of additional color are applied in a spatially distributed manner so as to reduce the amount of brightness modulation that is observed.
  • the SFD method may or may not be used with the BBC method.
  • N+l bit per color
  • N bit/color drive method For example, four bits of color data are stored in the frame buffer. To display the fourth bit using a 3 digital bits, the value ofthe fourth bit of data may be added to every other frame where the third bit ofthe data would appear. Table 4 below illustrates the case for the example where the three most significant bits are 010 for both a 0 and a 1 fourth bit value over sequential frames.
  • the perceived pixel values for three bits as shown above correspond to the four bit pixel values, hi other words 010 and 011 average to the binary value 0101 as long as we apply the most significant bits with the same weighting for 3 or 4 bit numbers. Physically, the same effect on average is achieved that would be achieved by adding one more binary data cycle with a flash duration half as long as the original third bit's flash duration.
  • the SFD method further includes spatially distributing when the additional bit is displayed so that the additional bit is not displayed by all the pixels at the same time. Since the human vision system responds more slowly to data with fine detail, spatially offsetting the frames where the additional bit is being displayed reduces the perceived flicker.
  • Figure 26B shows one method for achieving a spatial offset. As illustrated in Figure 26B, each group of 2 pixels along a row or column contains pixels with both A and B frames.
  • a display operating at a frame rate of 80 frames/second will generate the correct intensity perception if the user can average over four frames.
  • the flicker which could be perceived as low as 20 cycles/second is suppressed by the spatial averaging.
  • Various other spatial averaging schemes are possible.
  • Controlling the intensity of a display pixel can be accomplished several ways.
  • the amount of light is attenuated to the desired intensity by changing the opacity ofthe LC with varying amounts of voltage. Since illumination is generally constant and continuous, the LC is used to filter the light to achieve the desired intensity for a given pixel. The amount of LC filtering corresponds to the voltage applied.
  • Binary modulation (as described in the Balanced Binary Color (BBC) method, above) can be incorporated into the present methodology.
  • the desired intensity is defined by a (multi-digit) binary number, each "on" bit contributing a portion of illumination according to its position in the binary progression. The most significant bit contributes twice the illumination ofthe next most significant bit, and that in turn is twice the illumination ofthe next, and so on to the least significant bit.
  • the apparent pixel intensity is controlled by the duration that illumination is allowed to pass through LC. The longer the amount of time that illumination is allowed to pass through the LC, the brighter the apparent intensity, and vice versa.
  • LC as a digital "light valve,” allowing all light to pass in one state (“on” state), and none to pass in the other (“off state).
  • the pixel intensity is expressed as a number between 0 and X. This value is then used to control the duration that the LC is optically "on”.
  • FIG. 28 shows an embodiment of a pixel circuit 2800 according to the present invention.
  • each pixel has an individual pixel circuit associated with it.
  • Each pixel circuit is preferably integrated in the backplane ofthe display.
  • each display includes an array of pixels and their associated pixel circuits.
  • Figure 28 shows only one such circuit.
  • each circuit includes a timer 2802, which is preferably implemented under the associated pixel.
  • the pixel timers are set with their respective intensity values.
  • the LC associated with all pixels is switched optically "on” by resetting a pixel latch 2804.
  • the timers are instructed to start their countdowns. Illumination is applied to the entire display.
  • the associated pixel switch changes value such that the pixel is switched to an optically "off state so that substantially no light passes through the LC (the pixel goes dark).
  • each timer causes a change in the state ofthe LC associated with its pixel to optically "off when the timer times out.
  • a level shifter 2806 can be used to change the voltage to a higher voltage, such as where the output voltage to the pixel electrode 2808 is higher than the operating voltage for other portions ofthe circuit, for example.
  • a multi-bit memory and single bit digital analyzer, and a set/reset pixel state latch are implemented under (or placed in communication with) each pixel, and a global timing mechanism is implemented outside the display a ⁇ ay.
  • This a ⁇ angement provides the functionality of a timer under each pixel, with the added benefits that the circuit is much smaller than a timer, and the pixel intensity values need not be reloaded for each field.
  • the single bit digital analyzer is employed to sequentially test selected bit positions of the pixel memory to ascertain whether or not it matches a "broadcast" value. Thus, a local decoding is performed at each pixel, where several bits are used to represent units of brightness in time. A more detailed description ofthe single bit digital analyzer is set forth below.
  • Figure 29 depicts a process 2900 for the production of a grayscale image.
  • the pixel memories are set with their respective intensity values.
  • the LC associated with all pixels is switched optically "on" in operation 2904.
  • the first intensity value (0) corresponding to black, is broadcast to all pixels.
  • the LC of pixels whose memory matches the first intensity value are switched to an optically off state in operation 2908.
  • the LC of pixels whose memory does not match the first intensity value remains unchanged. In this case the LC is left in the optically on state.
  • illumination is applied to the entire display.
  • An amount of time corresponding to the desired incremental amount of illumination is allowed to pass in operation 2912. Note that the amount of time can vary, such as when each increment ofthe desired amount of illumination is increased or decreased to provide gamma correction. See the sub-section below entitled “Gamma Generation” for a more detailed explanation.
  • next intensity value (previous value + 1) is broadcast to all pixels.
  • the LC of pixels whose memory matches the next intensity value are switched to an optically off state in operation 2916.
  • the LC of pixels whose memory does not match the next intensity value remains unchanged. Again, in this case, the LC is left in the optically on state.
  • Operations 2912 through 2916 are repeated for each level of intensity in operation 2918.
  • the preferred maximum number of levels is 2 N -1, where N is the number of bits in each pixel.
  • the grayscale process described above can be applied for each color (selected by illumination LED) using different groups of memory bits for each color.
  • the method does not require that all ofthe memory bits be used for each field, allowing some bits to be used for one field, and others to be used in subsequent fields. For example: if the display has 18 bits of memory under each pixel, six can be chosen to represent Red, eight for Green, and four for Blue.
  • the image data can be loaded to the pixel memory once, and all three color fields may be sequenced repeatedly without subsequent reloading ofthe memory.
  • the LC is initiated in an optically on state. This is the preferred mode for LC that has a substantially faster On-to-Off switch time than Off-to-On.
  • the On-to-Off mode is used because it allows for finer control ofthe gray levels.
  • Other LC formulations may have this property reversed, hi such case, it would be better under this method to start in the optically off state. Consequently (when starting optically off), the delay duration would start out large, and would decrease in duration between broadcasts to produce the desired Gamma illumination curve.
  • the methods ofthe present invention greatly conserve power, because the voltage required to switch and maintain states in the LC is kept to a minimum due to the relatively short amounts of time that the voltage needs to be applied. Also, the illumination can be turned on and off more opportunely to further conserve power.
  • Figure 30 illustrates a pixel circuit 3000 for driving a pixel according to a preferred embodiment ofthe present invention, hi a display, each pixel has a pixel circuit associated with it.
  • Each pixel circuit is preferably integrated in the backplane ofthe display, ideally under the associated pixel.
  • the arrangement ofthe circuit shown in Figure 30 contrasts from that of Figure 28 in that the circuitry described here provides the functionality of a timer under each pixel, with the added benefits that the circuit is much smaller than a timer, and the pixel intensity values need not be reloaded for each field.
  • a multi-bit memory matrix 3002 is provided for each color field to be displayed by the pixel.
  • the memory stores N bits that represent the desired intensity value ofthe pixel.
  • N bits that represent the desired intensity value ofthe pixel.
  • Intensity values are sequentially broadcast to all ofthe pixels ofthe display. Each broadcasted intensity value includes a bit sequence. For each bit stored in the memory, a digital analyzer 3004 analyzes the broadcasted intensity value with respect to the bit values from the memory in a sequential manner to determine whether they match.
  • the digital analyzer preferably comprises a single bit digital analyzer and a multiplexer to allow analysis of each bit individually.
  • the digital analyzer performs N single-bit analyses per color field, one analysis for each bit stored in the memory for that color field.
  • the digital analyzer for example, can provide an exclusive OR function to analyze each memory bit and the broadcasted intensity value.
  • each ofthe bits is selected through the multiplexer according to the broadcast sequence and strobed with the appropriate bit value of the broadcasted value, as discussed below in the sub-section entitled "The Single Bit Digital Analyzer.”
  • analysis nodes may be used to temporarily store information about the analyses. If the strobing matches for any ofthe bits analyzed, the value of a analysis node is switched. Note that the analysis node is precharged such that it holds a value (such as a high or low value) prior to each analysis.
  • An accumulator latch 3006 receives information from the digital analyzer and switches if a match is found. If analysis nodes are used, the accumulator latch obtains the state of each ofthe analysis nodes to determine whether there has been a match by evaluating whether the voltage of any ofthe analysis nodes is high or low. The accumulator latch temporarily stores each result until all N bits have been analyzed. Note that the accumulator latch is preset to a state prior to each cycle of N bits. An evaluator 3008 determines the state ofthe accumulator latch to evaluate whether a match of one ofthe bits was found or that no match was found. Then the accumulator latch is reset and the next bit sequence is analyzed such that a new evaluation is performed for each N bit sequence. Note that it does not matter which bit matches for the accumulator latch to switch values.
  • a pixel state latch 3010 receives input from the evaluator, preferably in the form of a pulse. If the evaluator input indicates that there was a match, the pixel state latch will switch to turn the pixel to the opposite state, i.e., off to on or on to off. If the evaluator input indicates that there was not a match, the pixel state latch will remain unchanged, as will the pixel state.
  • the circuit generates a drive signal and applies the drive signal to a pixel electrode 3014.
  • a level shifter 3012 can be used to change the voltage to a higher voltage, such as where the output voltage to the pixel electrode is higher than the operating voltage for other portions ofthe circuit, for example.
  • the pixel latch preferably includes an exclusive OR function that switches the voltage polarity ofthe pixel to reverse the state depending on the ITO state, which is determined exteriorly. Depending on the ITO state, the output voltage can be manipulated to reverse polarity to maintain a DC balance.
  • monitoring logic 3016 can be included that instructs the system not to perform analyses on the memory bit values for a particular color field once a match has been found, thereby saving power.
  • a multi-bit memory, a single bit digital analyzer, and a set/reset pixel state latch are implemented under each pixel.
  • the pixel state latch (PL) is used to hold the current state ofthe pixel (on or off).
  • the digital analyzer is comprised of another latch, used as an accumulator of the results ofthe analyses, and a multiplexer to propagate the value of a selected one of multiple memory bits.
  • the accumulator latch (AL) is preferably a set/reset type device. Note that any suitable type of latch can be used.
  • the digital analyzer's job is somewhat simplified, because in the illustrative system the only value desired to make analyses with is zero.
  • the actual orchestration ofthe analysis function is controlled externally via select lines (existing in parallel to all pixels).
  • select lines existing in parallel to all pixels. The list of select lines are as follows:
  • a broadcast consists of a sequence of bit values. Each bit to be tested is sequentially selected, hi other words, one bit is selected at a time. Only bits whose value, in the "broadcast value”, are equal to zero are selected. Bits whose values, in the "broadcast value”, are equal to one are not selected.
  • the evaluation select line is asserted to propagate the results to respective pixel latches.
  • Figure 31 is a flow diagram illustrating a process 3100 for performing a analysis. Keep in mind that the actual selections can be done globally from outside the pixel array.
  • the AL is set (indicating that, so far, the analysis is true).
  • the memory bit to be analyzed are selected, one at a time. When a memory bit is selected, the value ofthe memory propagates through the multiplexer onto the "Reset" line ofthe accumulator latch in operation 3106. If the propagated value is a "1”, the Reset line ofthe AL is thereby asserted in operation 3108, indicating that the analysis is false. If the propagated value is a "0", the Reset line ofthe AL is not asserted, retaining its previous state.
  • operations 3104 through 3108 are repeated until all bits that are to be considered have each been selected.
  • the evaluation line is asserted in operation 3112, propagating the held value of the AL onto the PL' s Reset line. If the AL' s value is TRUE, the PL's Reset line is asserted in operation 3114 and the pixel is turned optically off as a result. If the AL's value is FALSE, the PL's Reset line is not asserted, and the PL retains its previous state
  • the human eye does not perceive light intensity in a linear fashion. If a light source is emitting twice the number of photons as another, it appears brighter to the human eye, but is not perceived as "twice as bright". Human perception of light intensity follows a logarithmic curve. Digital images are most often encoded to reflect human perception rather than linear steps in photon counts. Thus, to faithfully reproduce an image as intended, a method of generating the appropriate, relative, levels of intensity is needed.
  • the method described employs a series of broadcasts, with a duration of time between each (see operations 2906, 2912-2914 of Figure 29).
  • decoding is performed locally by taking a bit and putting it through a digital analyzer circuit to use, for example, four bits to represent 0 to 15 units of brightness in time.
  • the timing of when analyses take place is controlled externally, i one embodiment ofthe present invention, the timing is controlled by varying the time period between broadcast ofthe bit value.
  • the evaluator and/or accumulator latch is used to vary the timing between switching cycles by controlling the timing when the pixel latch switches. Note that a separate timing input(s) into the evaluator and/or accumulator latch may be required in such an embodiment.
  • While the delay between broadcasts can be ofthe same duration, such as when based on a clock signal, they need not be ofthe same duration.
  • the intensity of each level can be correct relative to the other levels with respect to digital image encodings and human perception. That is, the resulting image would be displayed with the intended "Gamma”.
  • a different illumination timing profile could be programmed in the display system to provide "Gamma Correction".
  • Each level of gray can be individually adjusted with respect to the next level higher and lower, to provide for maximum flexibility in such corrections.
  • Tins is an unknown feature in LC displays — ndeed, it is a feature that has yet to be commercially introduced into the marketplace. [Existing displays utilizing prior art methods, if they offer Gamma control, allow the adjustment of three or four points on the curve only.]
  • the present invention is not to be limited to LC displays.
  • other embodiments ofthe present invention utilize Organic Light Emitting Diodes (OLEDs) rather than LC display elements.
  • OLEDs Organic Light Emitting Diodes
  • the duration that the OLEDs emit light is controlled utilizing the digitally controlled waveform according to the methodology set forth above.
  • each OLED is turned on to off or off to on at the appropriate time. This takes advantage ofthe fast on off and off/on time of OLEDs.
  • Figure 32 depicts an OLED circuit 3200 according to one embodiment ofthe present invention.
  • a variation ofthe system of Figure 30 can be implemented with this embodiment, where the level shifter and pixel electrode are replaced by a controller 3202 and a diode 3204.
  • a control signal from the pixel latch instructs a controller to pass a current to a diode to activate the diode.
  • the control input can also be a control pulse that lasts for a predetermined duration and the diode remains activated for the duration ofthe pulse.
  • Figure 33 illustrates an OLED circuit 3300 according to another embodiment ofthe present invention. As shown, an external control signal is input into a digital drive controller 3302 with variable output, which drives a diode 3304.
  • the control signal includes N bits that are decoded to determine a length of time the diode will remain illuminated and/or an intensity ofthe diode.
  • the variable output can include an electrical current of constant strength with a longer or shorter duration, an electric current of variable strength, or a hybrid of these.
  • OLED controllers and circuitry suitable for use in the system of the present invention are described in U.S. Patent Application No. 5,952,789 and entitled ACTIVE MATRIX ORGANIC LIGHT EMITTING DIODE (AMOLED) DISPLAY PIXEL STRUCTURE AND DATA LOAD/ILLUMINATE CIRCUIT THEREFORE; U.S. Patent Application No. 6,037,719 and entitled MATRIX- ADDRESSED DISPLAY HAVING MICROMACHINED ELECTROMECHANICAL SWITCHES; and U.S. Patent Application No.

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Abstract

L'invention concerne une matrice d'affichage destinée à former une image composite à partir d'une série de sous-images. En règle générale, la matrice d'affichage comprend plusieurs éléments d'affichage, chacun desquels comprenant un pixel, et un circuit d'affichage connecté électriquement au pixel. Une source d'éclairage éclaire chaque pixel. Une logique commande l'intensité de chaque pixel en utilisant une forme d'onde commandée numériquement pour commander une durée pendant laquelle l'éclairage peut traverser le cristal liquide des éléments d'affichage. L'invention concerne également un procédé de commande de l'affichage numérique. Chaque chronomètre de pixels, parmi un ensemble, est paramétré avec une valeur d'intensité, les chronomètres de pixels étant associés à des pixels d'un affichage. Les pixels de l'affichage sont paramétrés dans un premier état. Chaque chronomètre est initialisé. L'éclairage est appliqué à l'affichage. Chaque pixel est commuté dans un second état au terme de la durée de chronométrage. L'opération est répétée un nombre de fois prédéterminé pour générer une image. Dans un mode de réalisation, l'invention concerne également un procédé de production d'une image en niveaux de gris sur un affichage numérique. Des valeurs d'intensité pour chaque pixel sont stockées dans des mémoires de pixel toutes associées aux pixels individuels d'un affichage. Chacun des pixels est paramétré dans un premier état. Un premier niveau d'intensité est diffusé aux pixels. Le premier niveau d'intensité est analysé avec les valeurs d'intensité stockées dans les mémoires de pixel. Les pixels dont la valeur d'intensité associée correspond au premier niveau d'intensité sont commutés dans un second état. L'éclairage est appliqué à l'affichage. On laisse ensuite s'écouler une période de temps prédéterminée. Une valeur d'intensité suivante est alors diffusée aux pixels et le niveau d'intensité suivant est analysé avec les valeurs d'intensité stockées dans les mémoires de pixel. Les pixels dont la valeur d'intensité associée correspond au niveau d'intensité suivant sont commutés dans le second état. Les deux étapes finales du procédé sont répétées pour chaque niveau d'intensité souhaitée.
EP02724978A 2001-02-21 2002-02-20 Systeme et procede de decodage local d'une sequence de bits numerique pour commuter l'etat d'un pixel sur une base temporelle, dans le but de reguler les niveaux de gris et la correction gamma Withdrawn EP1384202A2 (fr)

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US20060044291A1 (en) * 2004-08-25 2006-03-02 Willis Thomas E Segmenting a waveform that drives a display
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FR3079957B1 (fr) 2018-04-05 2021-09-24 Commissariat Energie Atomique Dispositif et procede d'affichage d'images avec une memorisation de donnees realisee dans les pixels

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