Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/90—Buffering arrangements
  • H04L49/9084—Reactions to storage capacity overflow
  • H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
  • H04L49/9094—Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/04—Distributors combined with modulators or demodulators
  • H04J3/047—Distributors with transistors or integrated circuits
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/06—Synchronising arrangements
  • H04J3/0602—Systems characterised by the synchronising information used
  • H04J3/0605—Special codes used as synchronising signal
  • H04J3/0608—Detectors therefor, e.g. correlators, state machines
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/02—Details
  • H04J3/06—Synchronising arrangements
  • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04J—MULTIPLEX COMMUNICATION
  • H04J3/00—Time-division multiplex systems
  • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
  • H04J3/1605—Fixed allocated frame structures
  • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
  • H04J3/1617—Synchronous digital hierarchy [SDH] or SONET carrying packets or ATM cells
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/90—Buffering arrangements

Definitions

• This invention relates to the field of network systems and, more
• the Internet may be described in a simplified manner as a collection of
• networks e.g., transmission lines,
• switches and routers to enable the transfer of data among the computer systems.
• Data is typically transmitted i networks along a data path in the form of data
• Bit width is the
• bit width of a data path determines its bandwidth along with clock speed.
• Bandwidth is a measure of how fast data flows on the data path.
• bandwidth may be expressed as data speed in bits per second (bps).
• POTS Public Switched Telephone Network
• ISDN Integrated Services Digital Network
• legacy systems i.e., older systems designed earlier
• IP Internet Protocol
• SONET Synchronous Optical Network
• SONET synchronous digital hierarchy
• network adapters to encode and decode the data that is transmitted on a
• a data aligner More specifically, a data aligner
• multiplexer to an intermediate buffer, thereby leading to congestion of logic in
• the present invention pertains to a method and apparatus for byte
• the method may include receiving a
• the method may also include determining a state of the
• the method may include predicting a
• method may also include performing a calculation of a rotation amount of a
• the apparatus may include a first buffer
• the rotator coupled to the controller and the .first buffer.
• the rotator may include a
• first rotation circuit coupled to receive an input and generate a first output.
• rotator may also include a first multiplexer coupled to receive the input and the
• the first multiplexer selects between the input
• the first rotate amount control signal may be determined by predicting a number of bytes residing in the first buffer in a succeeding clock
• the present invention pertains to a method and apparatus for data alignment.
• the apparatus may include a plurality of circuitry stages coupled between a plurality of buffers. Later stage circuitry and corresponding buffers may be used to distribute the generation of an aligned data packet to reduce the operational time of earlier stage circuitry.
• the apparatus may include first stage circuitry coupled to a first buffer.
• the first stage circuitry may include a rotator coupled to the first buffer, a controller coupled to the rotator, and a first multiplexer coupled to the controller.
• the apparatus may also include a second buffer coupled to the rotator and second stage circuitry coupled to the second buffer.
• the second stage circuitry may include a second multiplexer.
• a third buffer may also be coupled to the second stage circuitry.
• the method may include receiving a first data element having a plurality of bytes and determining a first number of the plurality of bytes that contain data. The method may also include passing the first data element without operating on the first data element if all of the plurality of bytes that contain data and holding the data element if less than all of the plurality bytes contain data.
• the method may include receiving a head element having empty byte positions out of a plurality byte positions and receiving a first succeeding body element.
• the method may also include operating on the head element to generate a first packed element by combining the head element with the first succeeding body element to fill the empty byte positions of the head element with data from the first succeeding body element.
• the first packed element may have the plurality of byte
• the method may also include transmitting the first packed element if the plurality of byte positions of the first packed element are filled by the operation.
• the method may include receiving a first number of bytes of a non-continuous data stream and passing the first number of bytes through first and second buffers to a third buffer.
• the first number of bytes may be less than a predetermined number of bytes.
• the first buffer may be coupled to the second buffer and the second buffer may be coupled to the third buffer.
• the method may also include receiving a second number of bytes and passing on the first number of bytes from the second buffer to the third buffer.
• the method may also include feeding back the third buffer to the second buffer if the sum of the first and second numbers of bytes is less than the predetermined number.
• Figure 1 illustrates a digital processing system including one embodiment
• Figure 2 illustrates a network interface device including one embodiment
• Figure 3 illustrates one embodiment of a packet structure
• Figure 4 illustrates one embodiment of a data aligner.
• Figure 5 illustrates one embodiment of a method of data alignment.
• Figure 6 illustrates one embodiment of a complex to simple data stream
• Figure 7 illustrates an alternative embodiment for a data aligner.
• Figure 8 illustrates another embodiment of a method of data alignment.
• Figure 9 illustrates one embodiment of a rotator.
• Figure 10 illustrates one embodiment of a relationship between a rotated
• Figure 11 is an exemplary .embodiment illustrating outputs of a rotator
• Distribution of data operations may
• circuitry for some data operations in order to free-up first stage circuitry for
• the number of unaligned data scenarios is the number of unaligned data scenarios
• the data width is a configurable parameter. It should also be noted that the
• lines discussed herein that connect components may be either single bit lines,
• Figure 1 illustrates one embodiment of a digital processing system 100
• processor 110 coupled with bus 105
• Processor 110 may represent one or more
• processors such as a general purpose processor (e.g., a Motorola PowerPC
• processors or an Intel Pentium processor
• a special purpose processor e.g., a graphics processing unit (GPU) or an Intel Pentium processor
• a graphics processing unit or an Intel Pentium processor
• a special purpose processor e.g., a graphics processing unit (GPU) or an Intel Pentium processor
• DSP digital signal processor
• Digital processing system 100 further includes system memory 120 that stores instructions
• RAM random access memory
• dynamic storage device may include a random access memory (RAM), or other dynamic storage device
• bus 105 for storing information (e.g., packets) and instructions to be
• System memory 120 also may be used for storing instructions for processor 110.
• System memory 120 also may be used for storing instructions for processor 110.
• System memory 120 may also include a read only memory
• ROM -9- memory
• static storage device coupled to bus 120 for storing
• One or more network interface devices (network interface device 140 to)
• network interface device N may be coupled to bus 105.
• bus 105 In an alternative '
• network interface device 140 may reside external to digital
• Network interface device 140 includes network protocol
• interface device 140 includes circuitry for the generation of regular data streams.
• Network interface device 140 includes data aligner 150.
• Data aligner 150
• network interface device 140 may be a SONET card, an Ethernet card, token ring
• digital processing system 100 represents
• some systems often have multiple buses, such as a peripheral bus, a
• digital processing system 100 may
• controller coupled to bus 105 to assist processor 110 in
• digital processing system may be an intermediate node
• a switch or a router in a network that provides a network to network
• Such an intermediate node may provide an interface between similar
• network medium 160 may be a
• fiber optic medium and network medium N may be a transmission line medium.
• FIG. 2 illustrates one embodiment of an network interface device
• Network Interface device 210 may be network interface
• Data in the form of packets, is transmitted along a data
• Network interface device 210 formats the
• the packet protocol specifies the arrangement of information
• system 205 may be a client
• network 295 may be a SONET or Ethernet as mentioned above.
• Packets are transmitted in an egress direction from system 205 through
• network interface device 210 may include first-in-first-out
• Packets are received by FIFO 220 from system 205 on line 211. Packets
• network interface device 210 may
• FIFO 220 operates to buffer the data stream
• FIFO 240 operates to buffer the data stream received from
• buffering may be accomplished by
• a memory e.g., RAM, FIFO
• interface device 210 or a memory residing in system 205 (e.g., system memory
• Packets are transmitted from FIFO 220 to encapsulator 225 on line 224.
• Encapsulator 225 frames a packet according to a framing specification.
• the data stream packets are output from encapsulator 225 on line 229 to
• Data aligner 230 operates to gather bytes in the received
• Data aligner 230 receives unaligned
• aligner 230 outputs aligned data packets on line 234 to packet check generator
• 5 aligner 230 also transmits a control signal on line 233 to packet check generator
• Data aligner 230 may also indicate which bytes in the packet are valid.
• Data aligner 230 may also indicate which bytes in the packet are valid.
• EOP control signal The operation of data aligner 230 is discussed in detail
• a packet check generator 235 is used to verify the
• the packet check generator 235 generates an output
• receiving system e.g., packet error checker 245 to determine whether a packet is a packet.
• the data stream is
• detecting code such as 32 bit cyclic redundancy check (CRC) may be appended at
• Error detecting code such as CRC code is a number derived from a
• a receiver system (not shown) coupled to
• network 295 can detect transmission errors by recalculating a check code from
• packet check generator 235 need not be placed at the end of
• the transmit stage but may be placed at any location along the data stream path.
• Packets received from network 295 are input to decapsulator 255 on line
• Decapsulator 255 removes the framing data from data stream packets.
• the data stream may become
• This data stream is input to data aligner 250 on
• Data aligner 250 operates to gather non-continuous bytes in the
• the output of data aligner 250 is provided to packet error checker 245 on
• Packet error checker 245 may be used to verify the accuracy of the data
• the packet error checker 245 generates a code using the received data
• the output of packet error checker 245 may be passed to
• FIFO 240 operates to buffer the data stream output to
• a FIFO, packet error checker, encapsulator, and decapsulator are known
• interface device 210 has been shown with separate
• network interface device 210 may be combined into one or more integrated
• Figure 3 illustrates one embodiment of a packet structure
• a packet 310 may include one or more
• Each packet element may have one or more
• packet element size as an example, other packet element byte sizes may be used,
• Packet .310 includes..a singleJ ⁇ eafLelement ⁇ 20 ⁇ a singleJailjelement 350,
• body 335 that may includes_one_orj_nore body, elements (e.g., elements 330
• a head element 320 signifies the start of a packet and its byte positions
• Head 320 may be either partially or fully filled with data bits. Head 320 may be any suitable type of data bits. Head 320 may be any suitable type of data bits. Head 320 may be any suitable type of data bits. Head 320 may be any suitable type of data bits. Head 320 may be any suitable type of data bits. Head 320 may be any suitable type of data bits. Head 320 may be any suitable type of data bits. Head 320 may be any suitable type of data bits.
• SOP start of packet
• a tail element 350 signifies the end of a packet and its byte positions may
• Tail element 350 may be either partially or fully filled with data bits.
• EOP end of packet
• tail element 350 may either partially or fully fill the bytes of tail element 350 with data bits.
• body element has all of its byte positions filled with data bits (e.g., body element
• a partial body refers to a body element (e.g., element 330) that is partially
• hole is an empty element either within packet 310 or between packet 310 and another packet (not shown).
• Figure 3 also illustrates exemplary byte enables 321, 331, 341, and 351 that
• a byte enable of " ⁇ " indicates that data
• Figure 4 illustrates one embodiment of a data aligner.
• data aligner 400 includes a two stage (stages 404 and 406) pipeline
• Intermediate buffer 420 operates to
• Data aligner 400 also identifies all unpassed data between stages 404 and 406.
• Data aligner 400 also identifies all unpassed data between stages 404 and 406.
• buffers 410 and 430 coupled to the input of stage 404 and the output of
• buffers 410, 420, and 430 may be
• Buffers 410, 420, and 430 operate to store data received from a
• Data aligner 400 may also include control buffers 415, 425, and
• Buffers and registers are known in the art; accordingly, a detailed description is
• buffers 410, 420, and 430 may have a size
• buffers 410, 420, and 430 may have
• Buffers 410, 420, and 430 each have a clock input coupled to receive a
• the clock signal via line 481.
• the clock signal may be recovered from the data signal
• the clock may be generated by a clock generator (not shown).
• the clock may be generated by a clock generator (not shown).
• Buffer 410 has an input coupled to receive data packets on line 411. Buffer
• multiplexer 470 is coupled to buffer 430 via line 471.
• Controller 450 may be used to control the operation of multiplexers 460
• Controller 450 also has control outputs
• Rotator 440 operates to rotate one or more bytes into different byte slots
• a rotate amount control signal may be applied to rotator 440 on line
• controller 450 controls the output of rotator 440 as input data to buffer
• multiplexer 480 through multiplexer 480, and also as an input to multiplexer 460.
• function of the rotate amount control signal is to determine the amount by which
• buffer 410 contents of buffer 410 are rotated so that the remainder, if any, of buffer 410 and
• buffer 420 the remainder, if any, of buffer 420 are concatenated and the contents of buffer
• controller 450 may recognize various bytes states.
• buffer 410 In a first byte state, the content of buffer 410 is written to buffer 420 in a
• This byte state occurs when controller 450 determines that either buffer 420 is
• This byte state may also occur when, irrespective of the state
• buffer 410 contains an SOP signal. As such, there is no dependency
• amount for the next cycle may be predicted to be 16 minus the number of bytes
• this case may be predicted to be zero, again implying no byte lane crossing.
• a state represents the case where buffer 410 contains an EOP signal and the state
• buffers 410 and 420 are such that the data may be directly passed between
• The.rotate amount in.this case may be
• buffer 420 exceeds 16 and a remainder of the content in buffer 410 is. written into buffer 420
• the rotate amount for this case may be predicted
• buffer 420 may have 14 bytes as valid (containing data)
• buffer 410 may have 6 bytes as valid. In the following clock cycle, 16 bytes
• Multiplexers 460, 470, 480 are used to select between two of their data
• the output of multiplexer 460 is coupled to a data input of
• multiplexer 470 on line 461.
• the output of multiplexer 470 is coupled to buffer
• mulitplexer 480 is coupled to buffer 420.
• Multiplexers 460, 470, and 480 receive control signals on control inputs from
• controller 450 on lines 452, 453, and 455, respectively. It should be noted that the
• the multiplexers may reside within other component
• mulitplexer 480 may reside within buffer 420.
• 470 is to select the multiplexer's output form the contents of buffer 420 and the
• Controller 450 also has a control output coupled to buffer 420 via line 459.
• control signal output to buffer 420 via line 459 may be 16
• control signal output to buffer 420 may also determine the valid bytes in buffer
• controller 450 various states may be recognized by controller 450 during a current clock cycle.
• the content of buffer 410 may be written to buffer 420 in a pass
• buffer 410 contains a SOP
• write enables to buffer 420 are all "l"s.
• buffer 410 In a third case, no byte from buffer 410 is written to buffer 420. Buffer 410
• the write enables to buffer 420 are all "0"s.
• the data aligner 400 d scussed above may be used to receive unaligned
• Data aligner 400 may
• Figure 5 illustrates one embodiment of a method of data alignment.
• data aligner 400 may be any combination of schemes, as previously mentioned.
• data aligner 400 may be any combination of schemes, as previously mentioned.
• data aligner 400 may be any combination of schemes, as previously mentioned.
• data aligner 400 may be any combination of schemes, as previously mentioned.
• step 510 If the head element contains less than 16 bytes of data, then the
• the data is passed to buffer 430 to
• the head element may be followed by a body element or a tail element. If
• the head element is followed by a body element then, since the number of bytes
• step 550 The rotated bytes are written to intermediate buffer 420. Steps
• step 540 to 550 are repeated until controller 450 determines that a tail is reached, step 540
• step 570 the data aligner 400 converts a head element, body
• tail element of which the head and /or tail element may be
• a head element may be received in
• register 410 and determined by controller 450 to contain 7 bytes of data. Because
• the head element contained less than 16 bytes, the 7 bytes are passed to and
• the next element received is a body element.
• the body element is determined by controller 450 to have 16 bytes of data and
• controller 450 calculates that a total of 23 bytes of data have been received.
• controller 450 Because the total exceeds the 16 byte size of data aligner 400, controller 450
• multiplexer 460 The 9 rotated bytes, along with 7 bytes from buffer 420,
• Controller 450 sends a multiplexer
• Data aligner 400 now has 16 bytes in register 430, that are outputted, and 7
• controller 450 passes the 1 byte through rotator
• POS Packet Over SONET
• a complex data stream may contain holes and partial body
• -25- may be handled by mapping these elements to the elements of the simple data
• Figure 6 illustrates one embodiment of a mapping scheme to handle hole
• a head element in one embodiment, a head element
• a body element of a complex data stream may be mapped 620 to a body
• a hole may be handled
• Partial body functions may be mapped 650 and 660 to that of the tail of a
• Tail A element is one where the net count of bytes containing
• a Tail B element is one where the net count of bytes
• aligner 700 of Figure 7 is greater than or equal to 16.
• Figure 7 illustrates an alternative embodiment for a data aligner that may
• data aligner may be implemented with a complex data stream.
• data aligner may be implemented with a complex data stream.
• 700 may include two pipelined stages (stages 704 and 706) separated by buffers
• Data aligner 700 includes buffer 730, rotator 740, controller 750, and
• Rotator 740 and controller 750 may operate
• Buffers 710, 720, and 730 each have a clock input coupled to receive a
• the clock signal via line 781.
• the clock signal may be recovered from the data signal
• the clock may be generated by a clock generator (not shown).
• the clock may be generated by a clock generator (not shown).
• aligner 700 may be performed.
• Buffer 720 operates to store all unpassed data between stages 704 and 706.
• Data aligner 700 also includes buffers 710 and 730 coupled to the input of stage
• Control buffers 715, 725, and 735 are coupled to
• controller 750 and operate to store byte enables.
• Buffer 710 has an input coupled to receive data packets on line 711 and
• the output of rotator 750 is coupled to a data input of multiplexer
• the output of rotator 740 is also coupled to a data
• multiplexer 760 with the other data input of multiplexer 760 coupled to
• Rotator 750 operates to rotate one or more bytes into different byte slots
• a rotate amount control signal may be applied to rotator 750 via
• buffer 720 concatenated and the contents of buffer 720 are properly byte aligned.
• controller 750 recognized by controller 750 one clock cycle before the actual rotation occurs, as
• the net valid count is the number of bytes in buffer 710
• Controller 750 has control outputs coupled to rotator 740 and control
• Controller 750 also a control output coupled to rotator 740 via line
• the output of multiplexer 760 is coupled to a data input of multiplexer
• buffer 720 is coupled to the other data input of
• multiplexer 770 and to a data input of multiplexer 775, via line 721.
• Buffer 730 includes a
• the data output of buffer 730 is coupled to a
• Controller 750 also has control outputs coupled to buffer 720 via line 759
• buffers 720 and 730 via lines 759 and 751, respectively, may be 16 bits wide.
• control signal to buffer 720 controls the writing of the buffer byte by byte after
• signal output to buffer 720 may also determine the valid bytes in buffer 720 in a
• controller 750 may recognize states during a current clock cycle, similar to
• buffer 710 are in buffer 710 and 6 bytes are in buffer 720 and buffer 710 does not contain an
• EOP signal is not cover by the cases discussed above in relation to Figure 4.
• controller 750 determines that it is a partial body element case and
• buffer 720 and the generation of an output enable by controller 750 to buffer 730
• buffer 720 as having 14 bytes and buffer 710 as having 6 by_tes.
• _TJb_isj_e presents
• the write enables are 20-16, so 4 left over bytes are
• Data aligner 700 described above may be used to receive unaligned data
• Data aligner 700 may support
• Rotator 740 operates in a similar one clock cycle look ahead manner
• the net valid count is the number of bytes in buffer 710 plus the
• the rotate amount is the primary
• control and may also serves as a seed for other control signals.
• a packet element is received and
• step 810 If the element is
• step 815 the element is mapped to
• step 820 discussed above in relation to Figure 5, step 820.
• the element is not a head, body or tail, it is analyzed to determine
• step 825 If the element is determined to be
• step 830 if the element is determined to be a partial
• the partial body function of the element may be mapped to that of a
• the partial body element may be
• Tail A a Tail A mapped element mapped to a Tail B mapped to a Tail A mapped to a Tail B mapped to a Tail A and a Tail B, based on the
• step 845 with the following
• locations 1 to 16 are generated in second stage 706 but are suppressed through
• the net count in the current clock cycle may be predicted as the intermediate
• Steps 850, 855, and 860 are repeated until
• intermediate buffer 720 contains 7 bytes and buffer 710
• controller 750 suppresses control output 778.
• control output 778 is suppressed until the net count equals
• buffer 730 is fed back through multiplexers 775, 760 and 770 to be input to buffer
• step 865 with the
• control outputs (inclusive of SOP and byte enables)
• step 870 the EOP control signal is not generated, step 875;
• step 880 since it is properly updated.
• buffer 720 (inclusive of buffer 730
• bypass stores 8 bytes of data and an additional 8 bytes are received then the 8
• the concatenated output is passed to multiplexer 770 to be
• controller 750 In this manner, a partial body element that causes a net count at
• buffers 710 and 720 (inclusive of buffer 730 bypass) to equal or exceed 16 bytes is
• first stage that may have a strict timing requirement, and distributes logic
• FIG. 9 illustrates one embodiment of a rotator. In one embodiment,
• rotator 900 may be used as rotator 440 of Figure 4 or rotator 740 of Figure 7.
• Rotator 900 represents a 4 stage chain of byte rotation circuitry in which each
• byte rotation circuit 981-984 is capable of rotating 1, 2, 4, or 8 bytes by
• Each of byte rotation circuitry 981-984 may be bypassed based on a rotate
• rotator 900 can generate a rotated output
• Figure 11 is an exemplary
• Control signals 971-97 are applied as cor_Jr l_inp_uts..to. nultiplexers 991-
• Control signals 971-974 select between outputs 961-964,
• another type of rotator may be used, for example, a
• apparatus may be used in store gathering functions where multiple byte wide

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Data Exchanges In Wide-Area Networks (AREA)
• Detection And Correction Of Errors (AREA)
• Time-Division Multiplex Systems (AREA)
• Detection And Prevention Of Errors In Transmission (AREA)

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  • 2002-01-25 AU AU2002245320A patent/AU2002245320A1/en not_active Abandoned
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