EP1343174B1 - Test de memoire programmable - Google Patents

Test de memoire programmable Download PDF

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Publication number
EP1343174B1
EP1343174B1 EP03354020A EP03354020A EP1343174B1 EP 1343174 B1 EP1343174 B1 EP 1343174B1 EP 03354020 A EP03354020 A EP 03354020A EP 03354020 A EP03354020 A EP 03354020A EP 1343174 B1 EP1343174 B1 EP 1343174B1
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Prior art keywords
memory
test
data
bist
field
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German (de)
English (en)
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EP1343174A3 (fr
EP1343174A2 (fr
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Michael Nicolaidis
Slimane Boutobza
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Synopsys Inc
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Synopsys Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines

Definitions

  • the invention relates to the test of memories.
  • BIST Today Built-In Self-Test
  • US Patent 5,659,551 discloses a programmable built in self test system.
  • BIST Built in the same chip as the memory, all these problems are not encountered.
  • the BIST can be used for testing embedded memories at their operation speed (at-speed).
  • memory BIST reduces significantly the test cost of complex systems on a chip, since we can test a system on a chip including embedded memories by using an Automatic Test Equipment (ATE) designed for testing logic designs.
  • ATE Automatic Test Equipment
  • BIST has a significant limitation with respect to external test equipment. In fact, once the BIST hardware has been implemented, we can test the memory only by means of the test algorithm implemented in the BIST hardware.
  • BIST memory BIST
  • external testing can be used to apply any test algorithm required for debugging and failure analysis.
  • the debugging and failure analysis of faulty components returned from the field will not be performed at-speed, thus, reducing the efficiency of these tasks.
  • a solution for improving this situation is to implement a conventional BIST scheme that implements a large variety of test algorithms, but the cost of the BIST hardware can become prohibitive, and the test algorithms that can be executed after fabrication will be limited to those selected during the BIST implementation.
  • This invention presents a programmable BIST approach as defined in claim 1 that combines the advantages of the Built-In Self-Test and external test approaches while eliminating their limitations.
  • the invention combines the intelligence of the external test equipment, for determining the test algorithm at any time after circuit fabrication, with the at-speed test application offered by the BIST approach.
  • the BIST hardware is used for applying a test algorithm that is determined by the external test equipment. This is a difficult task.
  • we since we are targeting a very high (if possible unlimited) flexibility, in terms of memory fault models that we can cover, we may need to implement a very complex BIST hardware, in order to be able to program at any time after fabrication a large variety of memory test algorithms.
  • the selection of the test algorithm families able to cover a large variety of memory fault models may impact drastically the cost of the BIST hardware.
  • the most widely adopted memory fault models include stuck-at faults, transition faults, coupling faults, dynamic faults, passive pattern sensitive faults, active pattern sensitive faults (some times also called dynamic pattern sensitive faults), static pattern sensitive faults, and retention faults ("Testing Semiconductor Memories, Theory and Practice", by A.J. van de Goor, John Wiley & Sons publisher, 1991). Excepting the case of retention faults, which require some timing condition to be tested, the detection of any other of the above fault models can be achieved if we are able to provide certain states and perform certain operations over a set of memory cells. For instance, stuck-at faults require to write the 0 (1) state in each memory cell and read the cell.
  • Transition faults require performing the following operations to each memory cell: write 0 (1), write 1 (0), and read the cell.
  • a coupling fault requires setting the coupled cell to a certain value 0 or 1, perform a transition to the coupling cell, and read the coupled cell.
  • Dynamic faults require performing repeatedly some operations on the memory cell.
  • March test algorithms (SUK D. S., REDDY S. M. - "A march test for functional faults in semiconductor random access memories", IEEE Transactions on Computers, vol. C-30, n° 12, December 1981) are very popular since they are simple and can be used to detect a large number of predominant memory fault models, including memory cell faults such as stuck-at-faults, transition faults, various coupling faults and dynamic faults.
  • Memory prototype debugging and failure analysis may require testing the memory with test algorithms able to detect any of these fault models.
  • the variety of the test algorithms that can be used is vast, since the above fault models are numerous, and there are several varieties for some of these fault models.
  • idempotent coupling faults, inverting coupling faults, linked and unlinked coupling faults are some classes of coupling faults ( MARINESCU M. "Simple and efficient algorithms for functional RAM testing", IEEE International Test Conference, November 1982 .), (" Testing Semiconductor Memories, Theory and Practice", by A.J. van de Goor, John Wiley & Sons publisher, 1991 ). They correspond to a large number of test algorithms.
  • Dynamic faults are another example of faults requiring a large variety of test algorithms in order to be tested.
  • the test algorithm depends on the transistor level design of the memory cell (static cell, dynamic cell, one-transistor cell, two-transistor cell, ...), the electrical characteristics of the cell, the type of the defect, and its electrical characteristics. These characteristics lead to a large number of test algorithms for testing dynamic faults.
  • Other fault models can be tuned by several parameters (e.g. the number and location of neighboring cells in neighborhood pattern sensitive faults). They result in several test algorithms for each type of pattern sensitive faults.
  • March test algorithms are very popular because they are simple and can detect a large number of predominant fault models such as cell stuck-at faults, transition faults, coupling faults, dynamic faults, faults in the read/write logic, and decoder faults. Due to their simplicity and the coverage of a significant set of fault models, they were selected in our programmable BIST approach.
  • a march test algorithm consists of several march sequences.
  • a march sequence is a test sequence having a very regular structure. It performs at each memory cell the same sequence of read and write operations, using the same data.
  • Such a sequence addresses the memory cells one after another, following a given addressing order. For each new address, the fixed sequence of operations is performed on the cell selected by this address. This is repeated to all the memory cells. For instance a march sequence can perform the following sequence of operations at each cell (r 0 , w 1 , w 0 , w 1 , r 1 ). That is, it performs a read 0, a write 1, a write 0, a write 1 and a read 1 before moving to the next cell for performing the same sequence of operations.
  • a march sequence is defined by the sequence of operations performed on each memory cell, and by the order used for addressing the memory cells, which can be the up or the down order. In fact any addressing order can be selected. However, once this order is selected for a march test algorithm, any march sequence of this algorithm will use this order (up order) or its reverse (down order).
  • the notation ⁇ (W 0 ) ; (r 0 , W 1 , r 1 ) ; (r 1 , w 0 , r 0 ) is a march test algorithm consisting of three march sequences.
  • the first sequence initializes all the memory cells to 0.
  • the addressing order is meaningless in this sequence.
  • the second sequence performs a read 0, a write 1, and a read 1 to each memory cell using an up addressing order.
  • the third sequence performs a read 1, a write 0, and a read 0 to each memory cell by using a down addressing order.
  • march test algorithms are very regular, and thus easy to implement. In addition, they detect many predominant memory fault models (e.g. stuck-at, transition, coupling and dynamic faults). This regularity is natural and reflects the fact that each fault in a fault model may affect any of the memory cells. Thus, it is natural to repeat the same operations to each cell, since we need to test the same faults at all the cells. However, this regularity involves an important limitation.
  • a memory cell c i and a set of memory cells S j a set of memory cells S j .
  • the state of the cells S j can have two possible patterns, a pattern A and its inverse A ⁇ , where the pattern A is uniquely determined by the position of the cell C i with respect to the cells of the set S j within the addressing order of the march test algorithm.
  • bit-oriented memories we can use different word values in different march sequences. However, within the same march sequence, we can only use a single word value and its inverse. This constraint results in a similar limitation as with bit-oriented memories.
  • march test algorithms cannot cover fault models involving interactions between more that two cells. Algorithms with more complex structure than march test algorithms are proposed for such fault models. In addition, not only the structure of the algorithm is more complex but also this structure can be very different from one variant of a fault model to another. For instance, Eulerian sequences, Hamiltonian sequences, the tiling methods, the two-group method, etc. ("Testing Semiconductor Memories, Theory and Practice", by A.J. van de Goor, John Wiley & Sons publisher, 1991), have been used to generate test algorithms for different pattern sensitive faults models and different configurations of the neighboring cells. As another complexity, the sequence of operations performed by the test algorithms depends on the physical position of the cells in the memory cell array. This, in case of memories using address scrambling, will require an additional circuit for mapping the logic addressing order generated by the BIST circuit, into the addressing corresponding to the physical positions of the cells, as it can result from the address scrambling.
  • the invention proposes a different approach, which uses programmable march test algorithms combined with programmable data backgrounds.
  • a technique that allows a complete data-background flexibility any data background can be selected for the memory cell array; we obtain a powerful programmable BIST at low cost.
  • the system of the invention maintains low the cost related to the selection of any data background in such a vast data background space.
  • PNPSF passive neighborhood pattern sensitive faults
  • each base cell is tested for its two transitions 0 ⁇ 1 and 1 ⁇ 0 combined with each of the 16 states of its four-cell deleted neighborhood.
  • test sequence performed for each background is a march-like test sequence, since it performs at each cell a transition followed by a read.
  • the write operation for performing the transition does not write the same value at each cell. This is because the write value is the inverse of the value loaded in the cell by the given background, which is not constant from one cell to another.
  • the programmable BIST principle described in the present invention allows doing that with a low hardware cost.
  • the present invention contemplates, by adopting a principle able to program any march test algorithm, to test the fault models involving a single cell (stuck-at faults and transition faults and a subset of dynamic faults), or involving interactions between two cells (coupling faults and remaining dynamic faults). Then, by combining this approach with a technique able to perform these algorithms with any possible background we can test all the known models of pattern sensitive faults, and more generally any fault model involving interactions between more than two cells.
  • the present invention describes a new programmable BIST architecture, which uses a single instruction per march sequences, loaded by means of a scan path. This eliminates the need for using a specific memory for storing the microprogram, and allows the performance of march test algorithms containing any number of march sequences.
  • the programmable BIST uses this decomposition. It allows a simple representation of the march test algorithms, leading to a simple hardware.
  • the programmable BIST hardware for march test algorithms comprises the following blocks:
  • the instruction determining the current march sequence can comprise, in particular, the following fields:
  • Fig. 1 illustrates an embodiment of a programmable BIST system according to the invention for testing a memory 200.
  • An instruction register 1 holds the current instruction that determines the current march sequence.
  • An Address Counter 73 generates an address sequence in the up or down order as specified by an U/D field of the instruction register. During each clock cycle of the test process, the Address Counter provides on its outputs the address of the current memory operation. The size of the Address Counter is equal to the number n of the address bits of the memory.
  • the Address Counter can be implemented by any sequential circuit able to generate on a set of n signals all the possible 2 n binary values. The Address Counter generates these values at a first order (up order), or at a second order (down order) which is the reverse of the first order.
  • a Data Register 53 provides on its outputs the data to be written in the memory.
  • register 53 provides the data value expected to be read from the memory. This data value is compared through a comparator 100, against the actual data value read from the memory 200 to verify its correctness. Another possibility is to verify the read data by using a signature analyzer. In this case the values present on the outputs of the Data Register during the read operations are useless. Very often the data words used in memory testing have a periodic structure. In this case the Data Register can have a number k of bits, which is lower than the number w of bits of the memory words. The k bits of the Data Register 53 will be expended into w bits as shown in figure 1 . Also, in this case, the Data field of the Instruction Register 1 will have k bits only.
  • a Control Register 63 provides during each cycle of the test process the control signals that determine the operation to be executed by the memory (e.g. a read, a write).
  • the Address Counter 73, the Data Register 53, and the Control Register 63 are not specific to this invention. They are necessary for any memory BIST scheme.
  • a Decode Logic 74 decodes the last address of the up sequence of the Address Counter 73 and the last address of the down sequence of the Address Counter 73, and activates respectively signals LU and LD when these addresses occur. In this example we consider the value 1 as the active value of these signals.
  • the Decode Logic 74 also is not specific to this invention, since all BIST controllers need a signal indicating if all the addresses of the memory were visited by the current march sequence, in order to start executing the next march sequence.
  • a Cycle Controller 30 comprises the multiplexer 32, the cycle counter 42, a comparator 43, a flip-flop 44 and an OR gate 45 connected as explained below.
  • the successive values of the first t+1 operation fields of the Instruction Register 1 are provided at an output O of the MUX 32, and the successive values of the first t+1 polarity fields of the Instruction Register 1 are provided at an output P of the MUX 32.
  • the Cycle Controller repeats the above operation for each address generated by the address counter 73.
  • the binary counter 42 counts during t+1 cycles from 0 through to t, where t is the value stored in the field NO of the Instruction Register 1.
  • the outputs of the binary counter 42 control the multiplexer 32 having m sets of inputs coming from the m operation fields of the Instruction Register 1, m sets of inputs coming from the m polarity fields of the Instruction Register 1, one set of outputs O and a second set of outputs P.
  • the multiplexer 32 is designed so that, when the outputs of the binary counter provide the binary value i, the multiplexer provides to its set of outputs O the values of the field Oi of the Instruction Register 1, and to its set of outputs P the values of the field Pi of the Instruction Register 1.
  • the comparator 43 compares the value stored in the field NO of the Instruction Register 1 against the value present on the outputs of the binary counter 42. When the comparison matches the output of the comparator is activated high.
  • the D flip-flop 44 delays the output of comparator 43.
  • the output of flip-flop 44 initializes the binary counter 42 to the 0 binary state.
  • a second signal TS can be combined with the output of flip-flop 44, by means of a logic gate 45, to generate the signal that initializes the binary counter 42.
  • the signal TS can be generated by a system external to the BIST circuitry (e.g. by the global test controller of a system on a chip (SOC)), which sets the signal TS to 1 during a clock cycle, to activate the BIST hardware.
  • SOC system on a chip
  • the clock of the Address Counter 73 counts once every t+1 clock cycles, where t is the binary value stored in the NO field of the Instruction Register 1.
  • the contents of the Address Counter are hold unchanged during t clock cycles where t is the binary value stored in the NO field of the Instruction Register.
  • the Address Counter 73 is controlled by a Hold signal.
  • the signal Hold is active during a clock cycle, then, during the subsequent clock cycle the state of the Address Counter will be unchanged.
  • the said Hold signal is generated by means of comparator 43 and counter 42.
  • the comparator 43 compares the outputs of the counter 42 against the value stored in the NO field of the Instruction Register 1.
  • the comparator When the comparison does not match, the comparator provides on its output the active level of the Hold signal, and when the comparison matches it provides on its output the non active level of the Hold signal.
  • the Hold signal of the Address Counter 73 is generated by using flip-flop 44 to delay the output of the comparator 43 during one clock cycle.
  • the output of the comparator is eventually inverted by an inverter 78.
  • the state of the Address Counter is hold unchanged when the value stored in the U/D field of the Instruction Register 1 during the present clock cycle is different from the value stored in this field during the previous clock cycle.
  • the value stored in the U/D field of the Instruction Register 1 is loaded to a flip-flop 76 at each clock cycle.
  • An EXCLUSIVE OR gate 77 receives the input and the output of flip-flop 76.
  • the active level (i.e. the level 1) activates the Hold signal of the Address Counter.
  • a logic circuit 79 combines the signal generated by the flip-flop 76 and the XOR gate 77 with the signal generated by the Counter 42, the comparator 43, the flip-flop 44 and the inverter 78, to generate the Hold signal.
  • the memory can be addressed in two possible orders, up and down.
  • the order (up or down) on which the addresses of the memory are generated during the test phase is determined by the contents of the U/D field of the Instruction Register 1.
  • the output of the U/D field of the Instruction Register controls the said U/D control input of the Address Counter.
  • the contents of the Address Counter 73 are initialized at the beginning of the test session, when the Instruction Register is loaded for the first time.
  • the Address Counter is initialized to the first address of the up address sequence if the value loaded in the U/D field of the Instruction Register codes the up addressing order (e.g. value 1), and is initialized to the first address of the down address sequence if the value loaded in the U/D field of the Instruction register codes the down addressing order.
  • the test session is activated by activating during one clock cycle a control signal TS (e.g. the value of TS is set to 1).
  • a logic circuit 75 combines the signal TS and the content of the U/D field of the Instruction Register 1, and generates a first signal R that forces the Address Counter 73 to the first address of the up address sequence and a second signal S that forces the Address Counter to the first address of the down address sequence.
  • the Instruction Register 1 is loaded once at the beginning of the test session and once each time the Address Counter provides at its outputs the last address of the address order determined by the value stored in the U/D field of the Instruction Register 1 and at the same time the state of counter 42 matches the value stored in the NO field of the Instruction Register.
  • the contents of the Instruction Register 1 are hold unchanged during (t+1)2 n - 1 clock cycles, where t is the binary value stored in the NO field of the Instruction Register and 2 n is the number of addresses of the memory under test.
  • the Instruction Register 1 is for example controlled by a hold signal to be said the hold signal of the Instruction Register. When this signal is active during a clock cycle, then, during the subsequent clock cycle the state of the Instruction Register will be unchanged.
  • the Decode Logic circuit 74 generates a first signal LU that is active when the last address of the up address sequence is present on the outputs of the Address Counter 73, and a second signal LD that is active when the last address of the down address sequence is present on the outputs of the Address Counter 73.
  • a logic circuit 82 combines the outputs LU and LD of the logic circuit 74, with the output of the U/D field of the Instruction Register 1 to generate a signal LM that is active only when the Address Counter 73 provides the last address of the address sequence order specified by the value stored in the U/D address field of the Instruction Register 1.
  • a logic circuit 83 combines the signal LM generated by the logic circuit 82 with a control signal TS, which activates the test phase, and with the output of a comparator 43 that compares the value stored in the NO field of the Instruction Register 1 against the outputs of counter 42, to generate the said hold signal of the Instruction Register.
  • the Instruction Register 1 may include a wait field W.
  • the inactive value e.g. value 0
  • the active value of the wait field W of the Instruction Register 1 e.g. the value 1) forces the BIST hardware to provide on the control signals of the memory under test a value that corresponds to a non operation cycle of the memory.
  • the BIST system can be used to program wait phases of any given duration for detecting retention faults. This can be done by loading the Instruction Register several times with well selected values of the NO field and the W field. To force the memory on a wait cycle (i.e.
  • the Address Counter 73 can be implemented to have different operation modes, in addition to the up and down modes.
  • the addresses in the up mode can be generated by using the column address bits as the LSB bits of the Address Counter and the row address bits as the MSB bits of the Address Counter. In this case, for a given value of the row address bits, all the values of the column address bits are generated before generating a new value in the row address bits.
  • Another possibility is to use the row address bits as the LSB bits of the Address Counter and the column address bits as the MSB bits of the Address Counter.
  • a multiplexer which connects the outputs of the Address Counter to the address bits of the memory following the one or the other of the above connections according the values applied on the control signals of the multiplexer.
  • Another possibility is to implement two counters, a column address counter for generating the values applied on the column address bits and a row address counter for generating the values applied on the row address bits.
  • a signal detecting the 11...1 state in the column address counter will be used to activate the row address counter each time the column address counter is full.
  • a similar connection can be used to implement the case where the row address bits have to be the LSB bits of the Address Counter.
  • the memory can be organized in columns, rows, and blocks, and have column address bits, row address bits, and block address bits.
  • the Address Counter can allow any of these modes and use some control bits to determine which of these configurations is used at any given time. Other address generators modes can also be used.
  • the addresses can be generated in a step mode where the state of the Address Counter is increased (in up mode) or decreased (in down mode) by a constant value c.
  • This can be done by implementing the Address Counter as an accumulator and applying the constant c on the one input of the accumulator.
  • the constant c can be programmed to allow a high flexibility. If the Address Counter is composed of several smaller counters as described above (e.g. column address counter, row address counter, ...), each of these counters can be implemented to perform the step mode.
  • the Address Counter 73 can be implemented to have various operation modes in addition to the up and down modes. The selection of the operation mode of the Address Counter 73 is performed by means of a set of control bits.
  • a @mode field (to be said the address mode field) is added to the Instruction Register 1. The value stored in the @mode field of the Instruction Register 1 determines the values of the control signals that select the operation mode of the Address Counter.
  • the instructions will be applied to the inputs of the Instruction Register by another circuit, for instance by a memory in which the instructions where stored previously.
  • An interesting characteristic of the programmable BIST according to the present invention is that it uses only one instruction per march sequence. Thus, we can use a scan path 101 to shift the first instruction until the inputs of the Instruction Register 1, and activate the TS signal to load it in the Instruction Register. Then, during the period of time that the BIST executes the first march sequence, we can use the scan path 101 to shift the second instruction until the inputs of the Instruction Register 1. This instruction will be maintained at the inputs of the Instruction Register 1 until the end of the second march sequence, where it will be loaded in the Instruction Register 1.
  • the signal that enables the loading of the instruction Register can be monitored by the system that controls the scan path 101 or by decoding elements of circuit 83.
  • the use of the scan path avoids the implementation of a memory for storing the instructions, and allows to program march test algorithms having any number of march sequences, while the use of a memory for storing the instructions limits the number of march sequences to the number memory words.
  • This use of a scan path is not possible with the existing schemes of programmable BIST, since these schemes use a micro-programmable approach, where the frequent use of different microinstructions do not leave enough time for shifting them through a scan path.
  • the signal ck is used for the blocks of the BIST hardware.
  • This hardware is implemented in the same chip as the memory, so it can be run at the same speed as the memory and the other blocks of the chip.
  • the signals shifted through the scan path can come from the board.
  • the scan path which can be a simple shift register with a serial input and a parallel output, will be operated by a slow clock signal.
  • the signal Sck is a different clock signal for the scan path 101, the signal Sck.
  • the programmable BIST described in this invention allows to program march test algorithms using any number of march sequences and any combination of operations within each march sequence.
  • the only limitation concerns the maximum number of operations performed within a march sequence. This number is limited by the number m of the operation fields of the Instruction Register 1.
  • all the known march test algorithms are composed of march sequences that use a small number of operations.
  • the cost of the hardware implementing the programmable BIST described in this invention is low.
  • an increase of the number of the operation and polarity fields of the Instruction Register will only increase the hardware for implementing the Instruction Register 1 and the multiplexer 32.
  • An important limitation of the march test algorithms is the use of a single data word and its reverse during each march sequence.
  • An important aspect of the present invention concerns the capability of a programmable BIST to use any test data during any cycle of the test process.
  • Such flexibility may require a large amount of test data and thus a large amount of memory for storing them.
  • Implementing a BIST with such a large memory will require a very high hardware cost.
  • test data there are two conventional ways to apply test data to an embedded memory.
  • the first way uses a scan path and shifts the test data provided by the test equipment until the data inputs of the memory. However this requires a large number of shifts for applying each test data. It makes impossible to perform an efficient test, which will require applying one test vector per clock cycle.
  • the second way is to create a direct connection between the circuit pads and the memory inputs. This can be done for instance by using some multiplexers. Thus, the external test equipment will be able to apply one test data per clock cycle. However, this test cannot be done at the normal operation speed of the memory, since the test data come from the board, and thus are much slower than the internal signals of an integrated circuit.
  • One of the goals of the present invention is to conciliate the high flexibility offered by an external test approach with the test application at high speed offered by a BIST approach.
  • the test data are provided by an external test equipment during a first phase and the test algorithm is performed by the BIST hardware during a second phase.
  • the test equipment provides the test data by means of a serial access mechanism (i.e. a scan path) or by means of a parallel access mechanism.
  • This phase is eventually performed at low speed. Since the test data provided during the first phase will be used as test data during the second phase, they have to be stored in the chip. In the worst case, we need a memory as large as the memory under test to store these data. There are two memories in the chip, memory 1 and memory 2, memory 2 being the memory 200 to be tested. The test data are stored in memory 1 during the first phase.
  • test the memory 2 by reading the data stored in memory 1 and using them as test data for memory 2. This will be done as following: we perform two algorithms in parallel on the two memories.
  • the algorithm performed on memory 2 is the test algorithm.
  • the algorithm performed on memory 1 (the data source algorithm) can be derived from the test algorithm as follows:
  • the rules 1 and 2 are conflicting if the test algorithm performs at some time a read over a memory location followed by a write over a different memory location. For instance if the test algorithm performs at cycle i a read over a cell C1 and at cycle i+1 a write over a cell C2, then from rule 1 the data source algorithm must perform a read of the cell C1 at cycle i, and from rule 2 the data source algorithm must perform a read over the cell C2 again at cycle i.
  • a signature analyzer we eliminate the rule 1 by using a signature analyzer to verify the read. For algorithms where this conflict does not occur we can use either a comparator or a signature analyzer for verifying the read data.
  • Figure 2 illustrates an exemplary embodiment of the invention using the scheme.
  • the test data are loaded to a first memory (memory 1) 201, during a first phase (the data load phase). Some access means such as a scan path chain 102 can be used to facilitate the transfer of the test data to the inputs of the memory 1.
  • the memory 200 to be tested (memory 2) 200 is tested during a second phase (the test phase), by means of a test algorithm.
  • the BIST hardware 301 of memory 201 (said read-only BIST) is programmed to perform an algorithm obtained by replacing each write operation of the test algorithm by a read operation.
  • the BIST hardware 302 of memory 200 (said BIST) is programmed to perform the test algorithm.
  • the read-only BIST 301 of the memory 201 is activated at cycle 0 by means of a control signal TS.
  • the BIST 302 of memory 200 is activated one cycle later than the read-only BIST 301 of memory 201, by means of a signal TS +1 .
  • the data read from memory 201 at any cycle are stored in a set of latches 401.
  • the data stored in this set of latches are applied on the inputs of a set of EXCLUSIVE OR gates 402.
  • Each XOR gate of the set of XOR gates 402 receives a first input from the output of a latch of the set of latches 402 and a second input from a polarity signal P generated by the BIST 302 of memory 200.
  • the outputs of the XOR gates 402 provide the data values to be written in memory 200.
  • a comparator 100 compares the data read from memory 200 against the outputs of the set of XOR gates 402, to check the correctness of the read data.
  • the above process can be repeated by exchanging memory 1 and memory 2, in order to perform the test algorithm over memory 1.
  • the BIST block 302 and the read-only BIST block 301 can be merged into a single block. For doing so, we implement only the BIST block 302 and we add a stage of latches between the outputs of this block and memory 2 (200). At the same time, we supply directly to memory 1 (201) the address signals, the MEM enable signal and the R/W signals generated by the BIST block (i.e. without passing through the stage of latches). But we modify the R/W signal to activate only read operations in memory 1 (201).
  • Another solution for using as test data for a memory the data supplied by an external test equipment at a low speed, and at the same time perform the test of the memory at a high speed consists of using a first phase (the data load phase) during which we load the test data in the memory, and a second phase (the test phase) during which we test the memory by using as test data the contents of the memory itself.
  • Fig. 3 illustrates another embodiment of the present invention.
  • the test data are loaded in the memory 203 by means of a test access mechanism 102 during a first phase.
  • the BIST hardware 303 is programmed to perform a test algorithm in which each set of consecutive memory operations performed over the same memory address starts by a read.
  • the data read from the memory 203 at any cycle or at some specific cycles are stored in a set of latches 401.
  • the data stored in this set of latches are applied on the inputs of a set of XOR gates 402.
  • Each XOR gate 402 receives a first input from the output of a latch of the set of latches 401 and a second input from a polarity signal P generated by the BIST hardware 303.
  • the outputs of the XOR gates 402 provide the data values to be written in the memory 203.
  • the data read from the memory 203 at any read cycle are injected to a signature analyzer 404, which is used for verifying the correctness of the read data.
  • two memories are tested concurrently by means of a first phase that loads the test data to each of the memories, and by means of a second phase that applies a test algorithm to each memory, which uses the data loaded in each memory as test data for that memory as described above.
  • the data read from the two memories at any cycle are compared against each other for checking their correctness.
  • a signature analyzer we can use a comparator that verify the read data at every t cycles, where t is the number of BIST clock cycles required to shift through the scan path a data word. Then, we repeat the test t times. The first time, we scan and check through the comparator the data read during the 1, t+1, 2t+1 ... cycles. The second time, we do the same for the 2, t+2, 2t+2 ... cycles. The t th time, we do the same for the t, 2t, 3t ... cycles.
  • test data can be loaded to the memory under test by means of a test access mechanism such as a scan path chain, and then use the BIST circuitry for applying a test algorithm, which uses the loaded data as test data.
  • a test access mechanism such as a scan path chain
  • test algorithm which uses the loaded data as test data.
  • the first technique considers the existence of a periodic structure in the data words used in many data backgrounds.
  • some backgrounds can use words having a period of k bits.
  • we transfer through the scan path k bits in the place of each word of m bits, and we expend these k bits into a word of m bits, similarly to the expansion shown in figure 1 . This reduces by a factor of m/k the number of bits to be transferred through the scan chain.
  • Fig. 4 illustrates an embodiment of the present invention, using an auxiliary memory 501 composed of q words of k bits.
  • the auxiliary memory is loaded with a set of q words of k bits each, by means of a test access mechanism 102 (e.g. a scan path).
  • a counter 502 generates repetitively all the q addresses of the auxiliary memory 501, and a read operation is performed over each address of the auxiliary memory 501 generated by the counter 502.
  • the k bits of the data read are expended to form words of m bits.
  • the BIST hardware 302 generates all the addresses of the memory under test 200, and at each cycle the expended form of the data read form the auxiliary memory 501 during the previous cycle is written in the memory under test 200.
  • the counter 502 generates repetitively the addresses of the auxiliary memory as many times as necessary for loading all the locations of the memory under test 200 with the data read from the auxiliary memory.
  • Mb is the maximum number of words including at any of these backgrounds.
  • the words of the auxiliary memory can be placed within the background in a rather arbitrary manner. In this case we will use the scan path to address the auxiliary memory, in order to read the words of this memory in the order required for writing them in the memory under test. With this scheme we will need a number of [log 2 q] shifts for writing each word of the background in the memory under test. This scheme is illustrated in figure 5 .
  • Fig. 5 illustrates another embodiment of the present invention, using an auxiliary memory 601 composed of q words of k bits.
  • the auxiliary memory is loaded with a set of q words of k bits each, by means of a test access mechanism 102 (e.g. a scan path).
  • a second access mechanism 103 e.g. a second scan path
  • a data is read from the address of the auxiliary memory 601 that is provided by the second access mechanism 103.
  • the k bits of the data read are expended to form a word of m bits.
  • the BIST hardware 302 generates all the addresses of the memory under test 200, and at each cycle the expended form of the data read form the auxiliary memory 601 during the previous cycle is written in the memory under test 200. The process is repeated as many times as necessary for loading all the locations of the memory under test 200 with the data read from the auxiliary memory.
  • the scheme using the scan path for writing the words of the background directly in the memory under test offers the highest flexibility, but requires the longest time for loading the backgrounds. This technique will be very desirable for debugging of new memory designs and for failure analysis, where the test time is not an important constraint and at the same time a high flexibility is required. On the other hand, test time reduction is a prime requirement in other situations such as manufacturing testing. The techniques proposed for reducing the loading time will be essential in this case. In order to be able to choose the highest flexibility of the one method or the lower test time of the others, we can implement several of the solutions in a given design.
  • a last problem concerns the verification of the data read from the memory during the test phase. For doing this verification, we can use a signature analyzer as for the scheme of Fig. 3 .
  • Another possibility is to use a comparator. In this case, during a read, we will also read the location of the auxiliary memory, in which we have stored the corresponding word, and we will use the comparator to compare the word read from the memory against the word read from the auxiliary memory, after expansion of the latter. This approach requires addressing the adequate location of the auxiliary memory at each clock cycle.
  • One option is to use a dedicated address generator. This generator can be quite simple if the address generator of the main memory addresses the memory words in an order that results on a periodicity in the data values read from the memory.
  • Another option is to use some of the address bits generated by the address generator to address the auxiliary memory. These bits can be used directly or after some transformations. This option works efficiently in most situations using periodic data patterns in the memory, since a few column and row decoder address bits determine this periodicity. So, each value of these bits may determine words in the main memory and in the auxiliary memory storing the same data value.

Claims (7)

  1. Système d'autotest intégré, BIST, programmable pour tester une mémoire formée dans une puce, comprenant :
    un registre d'instruction (1) formé dans la même puce que la mémoire ;
    des moyens (101) externes à la puce adaptés pour charger directement ou indirectement ledit registre par des instructions successives, chaque instruction comprenant :
    - au moins un champ de commande d'adresse (u/d, @mode),
    - un premier nombre, m, de champs d'opération (00-Om-1),
    - un champ de nombre d'opérations (NO) spécifiant un deuxième nombre d'opérations successives t+1, avec t+1≤m ;
    des moyens (73) commandés par le champ de commande d'adresse pour déterminer des adresses successives ; et
    un contrôleur de cycle (30, 42-45) adapté pour exécuter, pour chaque adresse successive, le deuxième nombre d'opérations successives, chacune d'elle étant déterminée par l'un des t+1 premiers champs d'opération.
  2. Système BIST selon la revendication 1, dans lequel chaque instruction comprend en outre m champs de polarité (P0-Pm-1), et le système comprend des moyens pour inverser ou non les données exécutées pendant chaque opération conformément à la valeur du champ de polarité correspondant, chaque champ de polarité comprenant au moins un bit pour inverser ou non un ensemble de bits desdites données.
  3. Système BIST selon la revendication 1, dans lequel chaque instruction comprend en outre un champ de données (Data) pour déterminer les données à traiter à chaque opération.
  4. Système BIST selon la revendication 3, dans lequel le champ de données comprend un nombre de bits inférieur au nombre de bits d'un mot mémoire, comprenant en outre des moyens pour étendre les bits contenus dans le champ de données à la taille d'un mot mémoire.
  5. Système BIST selon la revendication 1, dans lequel chaque instruction comprend en outre un champ d'attente (W), et le système comprend des moyens pour suspendre ses opérations conformément aux données contenues dans le champ d'attente.
  6. Système BIST selon la revendication 1, dans lequel chaque instruction comprend en outre un champ de fin de test (TE) spécifiant une dernière instruction.
  7. Système BIST selon la revendication 1, dans lequel le champ de commande d'adresse contient une instruction de montée ou de descente (U/D) spécifiant un incrément ou un décrément d'un compteur d'adresse (73).
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US7203873B1 (en) 2004-06-04 2007-04-10 Magma Design Automation, Inc. Asynchronous control of memory self test
RU2455712C2 (ru) * 2009-12-24 2012-07-10 Государственное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" Способ тестирования оперативных запоминающих устройств
US9859019B1 (en) 2017-01-24 2018-01-02 International Business Machines Corporation Programmable counter to control memory built in self-test

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US5659551A (en) * 1995-05-31 1997-08-19 International Business Machines Corporation Programmable computer system element with built-in self test method and apparatus for repair during power-on

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US5173906A (en) * 1990-08-31 1992-12-22 Dreibelbis Jeffrey H Built-in self test for integrated circuits
US5790564A (en) * 1995-06-07 1998-08-04 International Business Machines Corporation Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor
US6874111B1 (en) * 2000-07-26 2005-03-29 International Business Machines Corporation System initialization of microcode-based memory built-in self-test

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