EP1340256A2 - Packaged electronic component and method for packaging an electronic component - Google Patents

Packaged electronic component and method for packaging an electronic component

Info

Publication number
EP1340256A2
EP1340256A2 EP01997846A EP01997846A EP1340256A2 EP 1340256 A2 EP1340256 A2 EP 1340256A2 EP 01997846 A EP01997846 A EP 01997846A EP 01997846 A EP01997846 A EP 01997846A EP 1340256 A2 EP1340256 A2 EP 1340256A2
Authority
EP
European Patent Office
Prior art keywords
gel
electronic component
chip
diepad
packaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01997846A
Other languages
German (de)
French (fr)
Inventor
Stefan Mueller
Frieder Haag
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1340256A2 publication Critical patent/EP1340256A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/296—Organo-silicon compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention is based on a packaged electronic component or a method for packaging an electronic component according to the type of the independent claims.
  • Packaged electronic components are already known in which a semiconductor chip is attached to an upper side of a die pad of a lead frame. In a subsequent step, the diepad and the chip and other parts of the leadframe are then enclosed in a plastic mass, so that a hermetic packaging for the chip is created.
  • the packaged electronic component according to the invention or the method according to the invention for packaging an electronic component has the advantage over the prior art that mechanical stresses resulting from the different thermal expansion coefficients of the plastic compound Diepads and the semiconductor chip result, can be reduced.
  • a silicone or fluorosilicone gel is used particularly advantageously.
  • the plastic mass from which the chip is enclosed is particularly simply a thermoplastic which can be processed by injection molding. The gel should then be appropriate
  • the gel can optionally be applied to a first side and subjected to curing before applying a gel to a second side. Almost all types of gel can be used in this way. Correspondingly viscous gels can also be applied on two sides and only then hardened. It is particularly easy to use gels that harden or are activated under the influence of ultraviolet light or that harden already at room temperature.
  • FIG. 1 shows a conventional packaged electronic component
  • FIG. 2 shows a packaged electronic component according to the invention.
  • FIG. 1 shows a cross section through a conventional electronic component.
  • the electronic component has a semiconductor chip 1, which is arranged on a metallic diepad 2.
  • the top of the Semiconductor chips 1 are electrically connected to interconnect elements 4 by bonding wires 5.
  • the semiconductor chip 1, the diepad 2, the bonding wires 5 and in some cases also the conductor track elements 4 are surrounded by a plastic compound 3, which is the actual packaging of the electronic
  • the electronic component thus consists of the plastic compound 3 from which the conductor track elements 4 lead out.
  • the conductor track elements 4 are mostly bent downwards to enable attachment to a circuit board.
  • a so-called lead frame is usually punched out of a metal strip, which has the conductor track elements 4 and the diepad 2.
  • the packaging is then done by the
  • Semiconductor chip 1 is attached to the diepad 2 by gluing, soldering or the like, and bonding wires are drawn between the upper side of the semiconductor chip 1 and the conductor track elements 4.
  • This device is then embedded in the plastic mass 3, which is usually carried out by injection molding.
  • the leadframe with the diepad 2 and, in part, the conductor track elements 4 with the semiconductor chip 1 arranged on the diepad 2 is brought into a mold and the mold is filled with a plastic compound.
  • a thermoplastic is used for this purpose, which is brought into a state by heating that it can be pressed into the mold in order to fill the cavity of the mold. After the plastic compound 3 has hardened, the electronic component is then removed from the mold.
  • the problem here is that different materials are used.
  • metallic materials can be used for the diepad 2 that have a thermal
  • FIG. 2 shows a cross section through a packaged electronic component according to the invention.
  • the same elements as in FIG. 1 are again designated by the reference numbers 1 to 5.
  • a gel 11, 12 is applied to the top of the semiconductor chip 1 and to the bottom of the diepad 2.
  • the gel 11, 12 is a material that is easily deformable and can therefore exert only very small forces on the semiconductor chip 1.
  • the gel 11, 12 is not suitable for transferring deformations of the plastic mass 3 to the semiconductor chip 1.
  • Plastic mass 3 relative to the semiconductor chip 1 can therefore not generate significant forces in the semiconductor chip 1. A decoupling of the thermal movements of the plastic mass 3 and the semiconductor chip 1 is thus achieved, as a result of which thermally induced stresses in the semiconductor chip 1 are avoided.
  • the gel 11, 12 is applied in a liquid state, and the viscosity of the gel can be adjusted accordingly when the gel is applied.
  • the gel 11, 12 undergoes a hardening step in which the elasticity of the gel is changed from a more fluid state when applied to a somewhat more viscous final state.
  • the gel 11 can first be applied to one side, for example on the upper side, of the semiconductor chip, and a curing step then takes place. After this hardening step, the lead frame can then be rotated so that the underside of the diepad 2 then points upward.
  • the gel 12 is then applied to the underside of the diepad with a subsequent hardening step.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

The invention relates to a packaged electronic component and to a method for packaging an electronic component, according to which a chip (1) is fastened to the top surface of a die pad (2). Said die pad (2) and the chip (1) are enclosed by a plastic material (3). A gel (11, 12) is disposed on the top surface of the chip (1) and on the bottom surface of the die pad (2).

Description

Verpacktes elektronisches Bauelement und Verfahren zur Verpackung eines elektronischen BauelementsPackaged electronic component and method for packaging an electronic component
Stand der TechnikState of the art
Die Erfindung geht aus von einem verpackten elektronischen Bauelement bzw. einem Verfahren zur Verpackung eines elektronischen Bauelements nach der Gattung der unabhängigen Patentansprüche .The invention is based on a packaged electronic component or a method for packaging an electronic component according to the type of the independent claims.
Es sind bereits verpackte elektronische Bauelemente bekannt, bei denen ein Halbleiterchip auf einer Oberseite eines Diepads eines Leadframes befestigt wird. In einem nachfolgenden Schritt wird dann der Diepad und der Chip und weitere Teile des Leadframes von einer Plastikmasse umschlossen, so dass eine hermetische Verpackung für den Chip geschaffen wird.Packaged electronic components are already known in which a semiconductor chip is attached to an upper side of a die pad of a lead frame. In a subsequent step, the diepad and the chip and other parts of the leadframe are then enclosed in a plastic mass, so that a hermetic packaging for the chip is created.
Vorteile der ErfindungAdvantages of the invention
Das erfindungsgemäße verpackte elektronische Bauelement bzw. das erfindungsgemäße Verfahren zur Verpackung eines elektronischen Bauelements hat demgegenüber den Vorteil, dass mechanische Spannungen, die aus den unterschiedlichen thermischen Ausdehnungskoeffizienten der Plastikmasse, des Diepads und des Halbleiterchips resultieren, verringert werden.The packaged electronic component according to the invention or the method according to the invention for packaging an electronic component has the advantage over the prior art that mechanical stresses resulting from the different thermal expansion coefficients of the plastic compound Diepads and the semiconductor chip result, can be reduced.
Weitere Vorteile und Verbesserungen ergeben sich durch die Maßnahmen der abhängigen Patentansprüche. Besonders vorteilhaft wird ein Silikon- oder Fluorsilikongel verwendet. Als Plastikmasse, von der der Chip umschlossen wird, wird besonders einfach ein thermoplastischer Kunststoff verwendet, der durch Spritzguß verarbeitet werden kann. Das Gel sollte dann eine entsprechendeFurther advantages and improvements result from the measures of the dependent claims. A silicone or fluorosilicone gel is used particularly advantageously. The plastic mass from which the chip is enclosed is particularly simply a thermoplastic which can be processed by injection molding. The gel should then be appropriate
Temperaturbeständigkeit aufweisen. Das Gel kann wahlwei.se erst auf eine erste Seite aufgebracht werden und vor dem Aufbringen eines Gels auf einer zweiten Seite einer Aushärtung unterzogen werden. Es können so nahezu alle Gelarten verwendet werden. Entsprechend dickflüssige Gele können auch auf zwei Seiten aufgebracht werden und erst danach einer Aushärtung unterzogen werden. Besonders einfach können dabei Gele verwendet werden, die unter Einfluß von Ultraviolett-Licht härten oder aktiviert werden oder bereits bei Raumtemperatur aushärten.Have temperature resistance. The gel can optionally be applied to a first side and subjected to curing before applying a gel to a second side. Almost all types of gel can be used in this way. Correspondingly viscous gels can also be applied on two sides and only then hardened. It is particularly easy to use gels that harden or are activated under the influence of ultraviolet light or that harden already at room temperature.
Zeichnungendrawings
Ausführungsbeispiele der Erfindung werden in den Zeichnungen dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigen die Figur 1 ein herkömmliches verpacktes elektronisches Bauelement und Figur 2 ein erfindungsgemäßes verpacktes elektronisches Bauelement.Embodiments of the invention are shown in the drawings and explained in more detail in the following description. FIG. 1 shows a conventional packaged electronic component and FIG. 2 shows a packaged electronic component according to the invention.
Beschreibungdescription
In der Figur 1 wird ein Querschnitt durch ein herkömmliches elektronisches Bauelement gezeigt. Das elektronische Bauelement weist einen Halbleiterchip 1 auf, der auf einem metallischen Diepad 2 angeordnet ist. Die Oberseite des Halbleiterchips 1 ist elektrisch durch Bonddrähte 5 mit Leiterbahnelementen 4 verbunden. Der Halbleiterchip 1, der Diepad 2, die Bonddrähte 5 und teilweise auch die Leiterbahnelemente 4 sind von einer Plastikmasse 3 umgeben, die die eigentliche Verpackung des elektronischenFIG. 1 shows a cross section through a conventional electronic component. The electronic component has a semiconductor chip 1, which is arranged on a metallic diepad 2. The top of the Semiconductor chips 1 are electrically connected to interconnect elements 4 by bonding wires 5. The semiconductor chip 1, the diepad 2, the bonding wires 5 and in some cases also the conductor track elements 4 are surrounded by a plastic compound 3, which is the actual packaging of the electronic
Bauelements bildet. Das elektronische Bauelement besteht von außen betrachtet somit aus der Plastikmasse 3, aus der die Leiterbahnelemente 4 herausführen. Die Leiterbahnelemente 4 sind meistens nach unten abgebogen, um die Befestigung auf einer Leiterplatte zu ermöglichen.Component forms. Viewed from the outside, the electronic component thus consists of the plastic compound 3 from which the conductor track elements 4 lead out. The conductor track elements 4 are mostly bent downwards to enable attachment to a circuit board.
Zur Herstellung derartiger Bauelemente wird üblicherweise aus einem Metallband ein sogenannter Leadframe herausgestanzt, der die Leiterbahnelemente 4 und den Diepad 2 aufweist. Die Verpackung erfolgt dann, indem derTo produce such components, a so-called lead frame is usually punched out of a metal strip, which has the conductor track elements 4 and the diepad 2. The packaging is then done by the
Halbleiterchip 1 durch Kleben, Löten oder dergleichen auf dem Diepad 2 befestigt wird und Bonddrähte zwischen der Oberseite des Halbleiterchips 1 und den Leiterbahnelementen 4 gezogen werden. Danach erfolgt dann die Einbettung dieser Vorrichtung in die Plastikmasse 3, welches üblicherweise durch Spritzgießen erfolgt. Dazu wird der Leadframe mit dem Diepad 2 und teilweise den Leiterbahnelementen 4 mit dem auf dem Diepad 2 angeordneten Halbleiterchip 1 in eine Form gebracht und die Form wird mit einer Plastikmasse gefüllt. Üblicherweise wird dazu ein thermoplastischer Kunststoff verwendet, der durch Erwärmen in einen Zustand gebracht wird, dass er in die Form gepresst werden kann, um den Hohlraum der Form auszufüllen. Nach dem Erhärten der Plastikmasse 3 wird dann das elektronische Bauelement aus der Form genommen.Semiconductor chip 1 is attached to the diepad 2 by gluing, soldering or the like, and bonding wires are drawn between the upper side of the semiconductor chip 1 and the conductor track elements 4. This device is then embedded in the plastic mass 3, which is usually carried out by injection molding. For this purpose, the leadframe with the diepad 2 and, in part, the conductor track elements 4 with the semiconductor chip 1 arranged on the diepad 2 is brought into a mold and the mold is filled with a plastic compound. Usually, a thermoplastic is used for this purpose, which is brought into a state by heating that it can be pressed into the mold in order to fill the cavity of the mold. After the plastic compound 3 has hardened, the electronic component is then removed from the mold.
Problematisch ist dabei, dass unterschiedliche Materialien verwendet werden. Der thermische Ausdehnungskoeffizient von den üblichen Halbleitermaterialien, beispielsweise Silizium, unterscheidet sich deutlich von den thermischen Ausdehnungskoeffizienten der meisten Metalle und von den thermischen Ausdehnungskoeffizienten der Plastikmaterialien" für die Verpackung von Halbleiterchips. Zur Minimierung der Spannungen zwischen dem Halbleiterchip und dem Material des Diepads 2 können für den Diepad 2 metallische Materialien verwendet werden, die einen thermischenThe problem here is that different materials are used. The coefficient of thermal expansion of the usual semiconductor materials, for example silicon, differs significantly from the thermal ones Expansion coefficients of most metals and the thermal expansion coefficients of plastic materials " for the packaging of semiconductor chips. To minimize the stresses between the semiconductor chip and the material of the diepad 2, metallic materials can be used for the diepad 2 that have a thermal
Ausdehnungskoeffizienten aufweisen, der nahe bei Silizium liegt (z.B. FeNi 42%). Es stehen jedoch keine Materialien für die Plastikmasse 3 zur Verfügung die von ihrem thermischen Ausdehnungskoeffizienten an den thermischen Ausdehnungskoeffizienten des Halbleiterchips 1 angepasst sind.Have expansion coefficients that are close to silicon (e.g. FeNi 42%). However, there are no materials available for the plastic compound 3 whose thermal expansion coefficient is matched to the thermal expansion coefficient of the semiconductor chip 1.
In der Figur 2 wird nun ein Querschnitt durch ein erfindungsgemäßes verpacktes elektronisches Bauelement gezeigt. Mit den Bezugszahlen 1 bis 5 sind wieder die gleichen Elemente wie in der Figur 1 bezeichnet. Auf der Oberseite des Halbleiterchips 1 und auf der Unterseite des Diepads 2 ist jedoch im Unterschied zur Figur 1 ein Gel 11, 12 aufgebracht. Bei dem Gel 11, 12 handelt es sich um ein Material, welches leicht verformbar ist und somit nur sehr geringe Kräfte auf den Halbleiterchip 1 ausüben kann. Insbesondere ist das Gel 11, 12 nicht geeignet, um Verformungen der Plastikmasse 3 auf den Halbleiterchip 1 zu übertragen. Die thermisch bedingte Verformung derFIG. 2 shows a cross section through a packaged electronic component according to the invention. The same elements as in FIG. 1 are again designated by the reference numbers 1 to 5. In contrast to FIG. 1, however, a gel 11, 12 is applied to the top of the semiconductor chip 1 and to the bottom of the diepad 2. The gel 11, 12 is a material that is easily deformable and can therefore exert only very small forces on the semiconductor chip 1. In particular, the gel 11, 12 is not suitable for transferring deformations of the plastic mass 3 to the semiconductor chip 1. The thermal deformation of the
Plastikmasse 3 relativ zum Halbleiterchip 1 kann somit nicht nennenswerte Kräfte im Halbleiterchip 1 erzeugen. Es wird somit eine Entkopplung der thermischen Bewegungen der Plastikmasse 3 und des Halbleiterchips 1 erreicht, wodurch thermisch bedingte Verspannungen im Halbleiterchip 1 vermieden werden.Plastic mass 3 relative to the semiconductor chip 1 can therefore not generate significant forces in the semiconductor chip 1. A decoupling of the thermal movements of the plastic mass 3 and the semiconductor chip 1 is thus achieved, as a result of which thermally induced stresses in the semiconductor chip 1 are avoided.
Das Aufbringen des Gels 11, 12 erfolgt in einem flüssigen Zustand, wobei die Viskosität des Gels beim Aufbringen entsprechend eingestellt werden kann. Nach dem Aufbringen des Gels 11, 12 erfolgt ein Ausharteschritt, bei dem die Elastizität des Gels von einem dünnflüssigeren Zustand beim Aufbringen zu einem etwas zähflüssigerem Endzustand verändert wird. Alternativ kann zunächst auf einer Seite, beispielsweise auf der Oberseite, des Halbleiterchips das Gel 11 aufgebracht werden und es erfolgt dann ein Aushartschritt. Nach diesem Aushartschritt kann dann das Leadframe gedreht werden, so dass dann die Unterseite des Diepad 2 nach oben weist. Es erfolgt dann das Aufbringen des Gels 12 auf der Unterseite des Diepad mit einem anschließenden Aushartschritt. Alternativ ist es aber auch möglich beide Seiten, d.h. sowohl die Oberseite des Halbleiterchips 1 wie auch die Unterseite des Diepad 2, mit einem etwas dünnflüssigerem Gel zu beschichten und erst danach durch einen Aushartschritt den Endzustand der Gelschichten 11, 12 einzustellen. Dazu ist es jedoch erforderlich, dass bereits im nichtausgeharteten Zustand das Gel ausreichend zähflüssig ist und eine ausreichende Haftung aufweist. Es können Gele verwendet werden, die bei Raumtemperatur ausharten, oder die unter UV-Licht ausharten oder bei denen die Aushärtung durch UV-Licht aktiviert wird. The gel 11, 12 is applied in a liquid state, and the viscosity of the gel can be adjusted accordingly when the gel is applied. After applying The gel 11, 12 undergoes a hardening step in which the elasticity of the gel is changed from a more fluid state when applied to a somewhat more viscous final state. Alternatively, the gel 11 can first be applied to one side, for example on the upper side, of the semiconductor chip, and a curing step then takes place. After this hardening step, the lead frame can then be rotated so that the underside of the diepad 2 then points upward. The gel 12 is then applied to the underside of the diepad with a subsequent hardening step. Alternatively, it is also possible to coat both sides, ie both the top of the semiconductor chip 1 and the bottom of the diepad 2, with a somewhat thinner gel and only then to set the final state of the gel layers 11, 12 by means of a hardening step. However, this requires that the gel is sufficiently viscous and has sufficient adhesion even in the uncured state. Gels that cure at room temperature or that cure under UV light or that are activated by UV light can be used.

Claims

Ansprüche Expectations
1. Verpacktes elektronisches Bauelement bei dem ein Chip (1) auf einer Oberseite eines Diepad (2) eines Leadframe befestigt ist und der Diepad (2) und der Chip (1) von einer Plastikmasse (3) umschlossen sind, dadurch gekennzeichnet, dass auf einer Oberseite des Chips (1) und auf einer Unterseite des Diepads (2) ein Gel (11, 12) angeordnet ist.1. Packaged electronic component in which a chip (1) is attached to an upper side of a diepad (2) of a leadframe and the diepad (2) and the chip (1) are enclosed by a plastic compound (3), characterized in that a gel (11, 12) is arranged on an upper side of the chip (1) and on an underside of the diepad (2).
2. Bauelement nach Anspruch 1, dadurch gekennzeichnet, dass für das Gel (11, 12) ein Silikongel oder Floursilikongel verwendet wird.2. Component according to claim 1, characterized in that a silicone gel or fluorosilicone gel is used for the gel (11, 12).
3. Bauelement nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass für die Plastikmasse (3) ein thermoplastischer Kunststoff verwendet wird.3. Component according to one of the preceding claims, characterized in that a thermoplastic is used for the plastic mass (3).
4. Bauelement nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass das Gel (11, 12) bei einer4. Component according to one of the preceding claims, characterized in that the gel (11, 12) at a
Temperaturbeständigkeit, bei der die Plastikmasse (3) mittels Spritzguß verarbeitet werden kann.Temperature resistance at which the plastic mass (3) can be processed by injection molding.
5. Bauelement nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass der Chip ein mikromechanisches Bauelement aufweist.5. Component according to one of the preceding claims, characterized in that the chip has a micromechanical component.
6. Verfahren zum Verpacken eines elektronischen Bauelements, bei dem ein Chip (1) auf einem Diepad (2) eines Leadframe aufgebracht wird und in einer Plastikmasse (3) eingebettet wird, dadurch gekennzeichnet, dass vor dem Einbetten auf einer Oberseite des Chip (1) und auf einer Unterseite des Diepad (2) ein Gel (11, 12) aufgebracht wird.6. A method for packaging an electronic component, in which a chip (1) is applied to a diepad (2) of a lead frame and embedded in a plastic mass (3) is characterized in that a gel (11, 12) is applied to an upper side of the chip (1) and an underside of the diepad (2) before embedding.
7. Verfahren nach Anspruch 6, dadurch gekennzeichnet, dass das Gel (11, 12) zuerst auf einer Seite aufgebracht wird, danach ein Aushartschritt für das Gel (11, 12) erfolgt und dass erst danach Gel (11, 12) auf einer anderen Seite aufgebracht wird.7. The method according to claim 6, characterized in that the gel (11, 12) is first applied to one side, then a hardening step for the gel (11, 12) takes place and that only then gel (11, 12) on another Side is applied.
8. Verfahren nach Anspruch 6, dadurch gekennzeichnet, dass Gel (11, 12) sowohl auf der Oberseite des Chip (1) wie auch auf der Unterseite des Diepad (2) aufgebracht wird und danach ein Aushartschritt für das Gel (11, 12) erfolgt.8. The method according to claim 6, characterized in that gel (11, 12) is applied both on the top of the chip (1) and on the underside of the diepad (2) and then a hardening step for the gel (11, 12) he follows.
9. Verfahren nach Anspruch 7 oder 8, dadurch gekennzeichnet, dass ein Gel (11, 12) verwendet wird, welches bei Raumtemperatur aushärtet, unter UV-Licht aushärtet, oder bei dem die Aushärtung durch UV-Licht aktiviert; wird. 9. The method according to claim 7 or 8, characterized in that a gel (11, 12) is used, which cures at room temperature, cures under UV light, or in which the curing is activated by UV light; becomes.
EP01997846A 2000-11-25 2001-11-21 Packaged electronic component and method for packaging an electronic component Withdrawn EP1340256A2 (en)

Applications Claiming Priority (3)

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DE10058593 2000-11-25
DE10058593A DE10058593A1 (en) 2000-11-25 2000-11-25 Packaged electronic component and method for packaging an electronic component
PCT/DE2001/004394 WO2002043142A2 (en) 2000-11-25 2001-11-21 Packaged electronic component and method for packaging an electronic component

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EP (1) EP1340256A2 (en)
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KR (1) KR20040014420A (en)
DE (1) DE10058593A1 (en)
WO (1) WO2002043142A2 (en)

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US20040084784A1 (en) 2004-05-06
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JP2004515060A (en) 2004-05-20
KR20040014420A (en) 2004-02-14

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