DE10243513A1 - Electrical and / or micromechanical component and method - Google Patents
Electrical and / or micromechanical component and method Download PDFInfo
- Publication number
- DE10243513A1 DE10243513A1 DE10243513A DE10243513A DE10243513A1 DE 10243513 A1 DE10243513 A1 DE 10243513A1 DE 10243513 A DE10243513 A DE 10243513A DE 10243513 A DE10243513 A DE 10243513A DE 10243513 A1 DE10243513 A1 DE 10243513A1
- Authority
- DE
- Germany
- Prior art keywords
- layer
- chip
- cap
- gel
- packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0058—Packages or encapsulation for protecting against damages due to external chemical or mechanical influences, e.g. shocks or vibrations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Health & Medical Sciences (AREA)
- General Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Computer Hardware Design (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Es wird ein elektronisches und/oder mikromechanisches Bauelement und ein Verfahren zur Herstellung eines solchen Bauelements vorgeschlagen, wobei auf eine Oberfläche (120) eine Schicht (31) aufgetragen wird, wobei die Schicht (31) eine gleichmäßige Dicke aufweist.An electronic and / or micromechanical component and a method for producing such a component are proposed, a layer (31) being applied to a surface (120), the layer (31) having a uniform thickness.
Description
Aus der deutschen Offenlegungsschrift
Das erfindungsgemäße elektronische und/oder mikromechanische Bauelement und das Verfahren mit den Merkmalen der nebengeordneten Ansprüche hat demgegenüber den Vorteil, dass ein Einzelchipverfahren durch ein Batchverfahren ersetzt wird. Weiterhin weist die Schicht des erfindungsgemäßen Bauelements eine bessere Homogenität auf. Insbesondere ist kein Gelbuckel vorhanden und das Gel kann auch nicht über den Chiprand hinausfließen. Weiterhin ist eine einfachere Prozesskontrolle, insbesondere durch den Nachweis der Schicht und die Schichtdicke, möglich. Weiterhin ist keine Einzelchipinspektion notwendig. Weiterhin gibt es keine Abhängigkeit von den Fließeigenschaften. Weiterhin ist es erfindungsgemäß vorteilhaft möglich, dass Bauelemente nicht mehr vergelt werden müssen, weil die Beschichtung im Prozess noch auf dem Waferlevel stattfindet, d. h. im Gegensatz zum Vergelen im Einzelchipverfahren wird die Beschichtung eines gesamten Wafers in einem Schritt vorgenommen.The electronic and / or micromechanical according to the invention Component and the method with the features of the independent claims In contrast, the advantage that a single chip process by a batch process is replaced. Furthermore, the layer of the component according to the invention better homogeneity on. In particular, there is no yellow jelly and the gel can also not about flow out the chip edge. Furthermore, a simpler process control, especially through the detection of the layer and the layer thickness possible. Furthermore, there is none Single chip inspection necessary. There is also no dependency of the flow properties. It is also advantageous according to the invention possible, that components no longer have to be retaliated because of the coating the process is still at the wafer level, d. H. in contrast the coating of a entire wafer in one step.
Durch die in den Unteransprüchen aufgeführten Maßnahmen sind vorteilhafte Weiterbildungen und Verbesserungen des in den nebengeordneten Ansprüchen angegebenen Bauelements und des Verfahrens möglich. Besonders vorteilhaft ist, dass die Schicht als Gel oder als Schutzlack vorgesehen ist. Dadurch ist es mit besonders einfachen und bewährten Mitteln möglich, kostengünstig die erfindungsgemäße Schicht herzustellen. Weiterhin ist es vorteilhaft, dass die Schicht wasserfest und/oder temperaturstabil hinsichtlich einer Mold- und/oder Löttemperatur und/oder elektrisch nicht leitend vorgesehen ist. Dadurch hält die Schicht den nachfolgenden Prozessen stand, insbesondere Sägeprozessen zur Vereinzelung der Chips, bei denen beispielsweise Wasser Verwendung findet, Löt- bzw. Moldvorgänge zur Befestigung bzw. Verpackung von Chips. Weiterhin ist es dadurch möglich, dass die Beschichtung auch im Bereich von elektrischen Kontakten vorgesehen sein kann, wenn die Schicht nicht leitend vorgesehen ist. Weiterhin ist es von Vorteil, dass die Schicht lediglich auf der Oberfläche vorgesehen ist und seitlich kein Material der Schicht vorliegt. Dadurch gibt es keine Probleme mit überfließendem Gel. Weiterhin ist es von Vorteil, dass als Druckverfahren ein Siebdruck- oder ein Stempeldruckverfahren verwendet wird. Dadurch ist es mit einfachen und beherrschten Techniken kostengünstig möglich, die erfindungsgemäße Schicht aufzubringen. Weiterhin ist es von Vorteil, dass die Schicht auf Waferlevel aufgebracht wird. Dadurch kann die Schicht für sehr viele Bauelemente auf einmal aufgetragen werden, was Produktionszeit und Produktionskosten einspart.By the measures listed in the subclaims are advantageous developments and improvements in the secondary claims specified component and the method possible. Particularly advantageous is that the layer is provided as a gel or as a protective lacquer. This makes it possible with particularly simple and proven means, the cost-effective layer according to the invention manufacture. It is also advantageous that the layer is waterproof and / or temperature stable with regard to a mold and / or soldering temperature and / or electrically non-conductive is provided. This will keep the layer going the subsequent processes, especially sawing processes for separating the chips, for example using water finds solder or molding processes for fastening or packaging chips. Furthermore, it is possible, that the coating also in the area of electrical contacts can be provided if the layer is provided in a non-conductive manner is. It is also advantageous that the layer is only on the surface is provided and there is no material on the side of the layer. This means there are no problems with overflowing gel. Furthermore it is It is advantageous that a screen printing or stamp printing process is used as the printing process is used. This makes it easy with mastered techniques economical possible, the layer according to the invention applied. It is also advantageous that the layer is on Wafer level is applied. This allows the layer for a great many Components can be applied at once, what production time and Saving production costs.
Ausführungsbeispiele der Erfindung sind in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigenEmbodiments of the invention are shown in the drawing and in the description below explained in more detail. It demonstrate
Beschreibung der AusführungsbeispieleDescription of the embodiments
In
In
Bekannte mikromechanische Systeme,
wie beispielsweise mikroelektromechanische Systeme, müssen nicht
zuletzt wegen der kleinen Strukturen mit Dimensionen im Mikrometerbereich
vor Umwelteinflüssen
geschützt
werden. Insbesondere bei den weiterverarbeitenden Prozessen ist
ein Schutz der empfindlichen Strukturen gegen Partikel und Prozessmedien
erforderlich. Dieser Schutz kann z. B. durch die Kappe
Erfindungsgemäß erfolgt die Beschichtung der
Kappe
In
Die Schicht
Claims (7)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10243513A DE10243513A1 (en) | 2002-09-19 | 2002-09-19 | Electrical and / or micromechanical component and method |
PCT/DE2003/000705 WO2004028958A2 (en) | 2002-09-19 | 2003-03-06 | Electrical and/or micromechanical component and method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10243513A DE10243513A1 (en) | 2002-09-19 | 2002-09-19 | Electrical and / or micromechanical component and method |
Publications (1)
Publication Number | Publication Date |
---|---|
DE10243513A1 true DE10243513A1 (en) | 2004-04-01 |
Family
ID=31969267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10243513A Ceased DE10243513A1 (en) | 2002-09-19 | 2002-09-19 | Electrical and / or micromechanical component and method |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE10243513A1 (en) |
WO (1) | WO2004028958A2 (en) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60119757A (en) * | 1983-12-01 | 1985-06-27 | New Japan Radio Co Ltd | Manufacture of semiconductor device |
US5087658A (en) * | 1988-12-29 | 1992-02-11 | Hitachi Chemical Company, Ltd. | Heat-resistant resin paste and integrated circuit device produced by using the heat-resistant resin paste |
JP2712618B2 (en) * | 1989-09-08 | 1998-02-16 | 三菱電機株式会社 | Resin-sealed semiconductor device |
SE0003050D0 (en) * | 2000-08-30 | 2000-08-30 | Abb Ab | composite |
DE10051053A1 (en) * | 2000-10-14 | 2002-05-02 | Bosch Gmbh Robert | Process for protecting electronic or micromechanical components |
DE10058593A1 (en) * | 2000-11-25 | 2002-06-06 | Bosch Gmbh Robert | Packaged electronic component and method for packaging an electronic component |
-
2002
- 2002-09-19 DE DE10243513A patent/DE10243513A1/en not_active Ceased
-
2003
- 2003-03-06 WO PCT/DE2003/000705 patent/WO2004028958A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2004028958A2 (en) | 2004-04-08 |
WO2004028958A3 (en) | 2004-07-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8110 | Request for examination paragraph 44 | ||
R002 | Refusal decision in examination/registration proceedings | ||
R003 | Refusal decision now final |
Effective date: 20120201 |