EP1335294A2 - Schnell-aus- und langsam-einschaltende Arbitrierungsvorrichtung zur Verringerung von Leistungsverlusten in Tristate-Treibern auf einem verteilten Bus - Google Patents

Schnell-aus- und langsam-einschaltende Arbitrierungsvorrichtung zur Verringerung von Leistungsverlusten in Tristate-Treibern auf einem verteilten Bus Download PDF

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Publication number
EP1335294A2
EP1335294A2 EP03250548A EP03250548A EP1335294A2 EP 1335294 A2 EP1335294 A2 EP 1335294A2 EP 03250548 A EP03250548 A EP 03250548A EP 03250548 A EP03250548 A EP 03250548A EP 1335294 A2 EP1335294 A2 EP 1335294A2
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EP
European Patent Office
Prior art keywords
bus
access request
request signal
bus access
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03250548A
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English (en)
French (fr)
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EP1335294A3 (de
Inventor
Srikanth R. Muroor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
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STMicroelectronics lnc USA
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Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of EP1335294A2 publication Critical patent/EP1335294A2/de
Publication of EP1335294A3 publication Critical patent/EP1335294A3/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention is directed generally to data processors and other circuits that operate on a shared address or data bus driven by buffers having tri-state outputs.
  • ASIC application specific integrated circuit
  • RAM random access memory
  • UP microprocessor
  • SOC system-on-a-chip
  • Minimizing power consumption reduces the cost of operating an electronic component and also reduces the heat dissipation requirements of the device in which the electronic component is disposed.
  • Buffer circuits i.e., line drivers
  • tristate outputs allow multiple hardware resources (e.g., any generalized processing system) to share a common bus (address or data) in a time-multiplexed fashion.
  • one hardware resource has exclusive access to the bus, while other resources await their turn to gain access to the bus.
  • Requests for the bus from hardware resources are sent to an arbitrator, which resolves these requests, and grants exclusive access to one resource.
  • the hardware resources send bus access requests to a bus arbitrator circuit.
  • the arbitrator resolves these requests and grants exclusive access to one resource by means of enable signals. These enable signals establish a connection between the bus and the requesting resource by means of tri-state buffer circuits.
  • Dynamic power dissipation in the tristate buffers consists of two components:
  • FIGURE 2 illustrates bus arbitrator 210 and tristate line drivers 230A and 230B associated with shared data bus 240 according to an exemplary embodiment of the prior art.
  • FIGURE 3 is a timing diagram illustrating the operation of bus arbitrator 210 and tristate line driver 230A and 230B in FIGURE 2.
  • bus arbitrator 210 provides enable signals EN1 and EN2 to tristate line drivers 230A and 230B, respectively.
  • Tristate line drivers 230A and 230B are connected to Data Bit Line 1 of exemplary shared data bus 240.
  • Arbitrator 210 implements a simple static priority-based arbitration mechanism.
  • AS FIGURE 3 illustrates, the REQ1 line is turned ON and the REQ2 line is turned OFF simultaneously.
  • arbitrator 210 activates the EN1 enable signal, which takes line driver 230A out of a high-impedance state and allows line driver 230A to write Data Bit 1 (DB1) from a first hardware source to Date Bit Line 1 of shared bus 240.
  • REQ2 is turned OFF, arbitrator 210 de-activates the EN2 enable signal, which puts line driver 230B into a high-impedance state and prevents line driver 230B from writing Data Bit 1 (DB1) from a second hardware source to Date Bit Line 1 of shared bus 240.
  • the EN1 enable signal does not turn ON after or simultaneously with the EN2 enable signal turning OFF.
  • the EN1 enable signal and the EN2 enable signal are both ON during the period T1 in FIGURE 3.
  • Line driver 230A is being driven by a data bit, DB1, equal to Logic 1 from a first hardware source.
  • Line driver 230B is being driven by a data bit, DB1, equal to Logic 0 from a second hardware source.
  • line driver 230A tries to drive Data Bit Line 1 of shared bus 240 high at the same time that line driver 230B pulls Data Bit Line 1 of shared bus 240 low by sinking current.
  • This present invention provides an improved bus arbitrator that completely eliminates bus contentions.
  • the enable signal to every tristate line driver (buffer) is generated so that the turn-off (i.e., logic level state to high impedance state) time of the line driver is significantly lower than the turn-on (high impedance state to logic state) time with respect to the hardware resource requesting access to the shared bus.
  • a primary object of the present invention to provide, for use in a shared bus system comprising a plurality of bus devices capable of requesting access to a shared bus, a bus arbitrator operable to slowly activate and rapidly de-activate tristate line drivers coupled to the shared bus.
  • the bus arbitrator comprises: 1) an input interface capable of receiving a first bus access request signal from a first of the plurality of bus devices; 2) a delay circuit capable of receiving the first bus access request signal from the input interface and generating therefrom a time-delayed first bus access request signal; and 3) a comparator circuit capable of receiving the first bus access request signal from the input interface and the time-delayed first bus access request signal from the delay circuit and generating a line driver enable signal only if both of the first bus access request signal and the time-delayed first bus access request signal are enabled.
  • the comparator circuit disables the line driver enable signal if either of the first bus access request signal and the time-delayed first bus access request signal is disabled.
  • a time delay of the delay circuit is greater than a maximum de-activation delay period associated with the tri-state line drivers.
  • the comparator circuit comprises an AND gate having a first input for receiving the first bus access request and a second input for receiving the time-delayed first bus access request signal.
  • the delay circuit is an asynchronous delay circuit.
  • the delay circuit comprises an even number of inverters connected in series, wherein a first of the even number of inverters receives the first bus access request signal from the input interface and a last of the even number of inverters generates the time-delayed first bus access request signal.
  • the delay circuit is a synchronous delay circuit.
  • the delay circuit comprises a flip-flop having an input capable of receiving the first bus access request signal from the input interface and an output coupled to the comparator circuit that generates the time-delayed first bus access request signal.
  • FIGURES 1 through 6, discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention.
  • Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged data processor or other circuit that uses a shared bus that is driven by tri-state buffers.
  • FIGURE 1 illustrates exemplary shared bus system 100, which implements fast turn-off, slow turn-on bus arbitrator 110 according to the principles of the present invention.
  • Shared bus system 100 comprises bus keeper 105, bus arbitrator 110, and N processing systems 120, including exemplary processing systems 120A, 120B, and 120C, which are labeled Processing System 1, Processing System 2, and Processing System N, respectively.
  • Shared bus system 100 further comprises N tristate line drivers 130, including exemplary line drivers 130A, 130B, and 130C, which are switched between logic states and high-impedance states by the enable signals EN1, EN2, and ENn, respectively.
  • the N tristate line drivers 130 are capable of driving shared (address or data) bus 140.
  • Bus keeper 105 is used to hold the lines of shared data bus 140 at particular logic levels if all line drivers are in high-impedance states.
  • N processing systems 120 are generic representations of any type of hardware resource (data processor, memory controller, input/output (I/O) interface, ASIC system, peripheral, or the like) that is capable of requesting access to shared bus 140.
  • Each processing system 120 sends an access request (REQ) signal to arbitrator 110, which responds by activating an enable signal for a tristate line driver associated with the requesting processing system 120 and deactivating any other enable signal.
  • REQ access request
  • arbitrator 110 responds by activating the EN1 signal for tristate line driver 130A and deactivating any other enable signal (i.e., EN2).
  • Line driver 130A then writes the data from processing system 120A onto shared bus 140.
  • arbitrator 110 provides a fast turn-off, slow turn-on mechanism for preventing bus contentions on shared bus 140.
  • FIGURE 4 illustrates improved bus arbitrator 110 for use with exemplary shared address or data bus 140 according to an exemplary embodiment of the present invention.
  • FIGURE 5 is a timing diagram illustrating the operation of exemplary bus arbitrator 110 in FIGURE 4 according to one embodiment of the present invention.
  • Bus arbitrator 110 comprises inverter 405, AND gate 410, and fast turn-off, slow turn-on controller 420.
  • Controller 420 comprises inverters 421 and 31, D-gate flip-flops (FF) 422 and 432, and AND gates 423 and 433. Controller 420 is clocked by the CLOCK signal, which causes D-gate flip-flops 422 and 423 to change state on the falling edges of the CLOCK signal.
  • controller 420 introduces a one-half clock cycle delay into the bus due to its sequential behavior. This is acceptable in situations in which the hardware resources are synchronous to the system clock and have sufficient timing slack to accommodate this delay. However, in cases where such delay is not acceptable, a combinational delay may be used as illustrated in FIGURE 6, to achieve fast turn-off and slow turn-on times.
  • FIGURE 6 illustrates selected portions of improved bus arbitrator 610 according to an alternate embodiment of the present invention.
  • Arbitrator 610 is similar to arbitrator 110 in FIGURE 4 except that the synchronous delay elements (i.e., D-gate flip-flops) in fast turn-off, slow turn-on controller 420 have been replaced in fast turn-off, slow turn-on controller 620 by an even number (2N) inverters 622 that introduce the delay.
  • synchronous delay elements i.e., D-gate flip-flops

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
EP03250548A 2002-01-30 2003-01-29 Schnell-aus- und langsam-einschaltende Arbitrierungsvorrichtung zur Verringerung von Leistungsverlusten in Tristate-Treibern auf einem verteilten Bus Withdrawn EP1335294A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60454 1993-05-10
US10/060,454 US7203779B2 (en) 2002-01-30 2002-01-30 Fast turn-off slow turn-on arbitrator for reducing tri-state driver power dissipation on a shared bus

Publications (2)

Publication Number Publication Date
EP1335294A2 true EP1335294A2 (de) 2003-08-13
EP1335294A3 EP1335294A3 (de) 2007-05-09

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EP03250548A Withdrawn EP1335294A3 (de) 2002-01-30 2003-01-29 Schnell-aus- und langsam-einschaltende Arbitrierungsvorrichtung zur Verringerung von Leistungsverlusten in Tristate-Treibern auf einem verteilten Bus

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US (1) US7203779B2 (de)
EP (1) EP1335294A3 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1304973C (zh) * 2003-11-14 2007-03-14 威盛电子股份有限公司 取得一总线操控的装置与方法

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US8127309B1 (en) * 2006-11-10 2012-02-28 Marvell International Ltd. Secure digital input/output interface system
US7962670B2 (en) * 2007-06-06 2011-06-14 Lantiq Deutschland Gmbh Pin multiplexing
EP2302519B1 (de) * 2009-09-09 2013-01-16 ST-Ericsson SA Dynamische Frequenzspeicherkontrolle
US10079049B2 (en) 2016-06-08 2018-09-18 Micron Technology, Inc. Stack access control for memory device
US10282264B1 (en) 2017-11-09 2019-05-07 Micron Technology, Inc. Apparatus and methods for repairing memory devices including a plurality of memory die and an interface
US12255644B2 (en) * 2022-11-28 2025-03-18 Texas Instruments Incorporated Audio interface physical layer

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US3886543A (en) * 1973-11-29 1975-05-27 Teletype Corp Debounce logic for keyboard
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US5029076A (en) * 1986-01-29 1991-07-02 Digital Equipment Corporation Apparatus and method for providing a settling time cycle for a system bus in a data processing system
ES2002950A6 (es) * 1986-01-29 1988-10-01 Digital Equipment Corp Un aparato y un metodo para proporcionar senales de control de la transferencia de grupos de senales logicas en un sistema de proceso de datos y sistema correspondiente
JPH06101227B2 (ja) * 1986-11-29 1994-12-12 三菱電機株式会社 半導体メモリ装置
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US6566907B1 (en) * 2001-11-08 2003-05-20 Xilinx, Inc. Unclocked digital sequencer circuit with flexibly ordered output signal edges

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1304973C (zh) * 2003-11-14 2007-03-14 威盛电子股份有限公司 取得一总线操控的装置与方法

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EP1335294A3 (de) 2007-05-09
US7203779B2 (en) 2007-04-10
US20030145145A1 (en) 2003-07-31

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