EP1325410A2

EP1325410A2 - Method for producing computer-assisted real-time systems

Info

Publication number: EP1325410A2
Application number: EP01969264A
Authority: EP
Inventors: Ralf MÜNZENBERGER; Frank Slomka; Matthias DÖRFEL; Oliver Bringmann
Original assignee: Friedrich Alexander Univeritaet Erlangen Nuernberg FAU
Current assignee: Inchron GmbH
Priority date: 2000-09-06
Filing date: 2001-09-03
Publication date: 2003-07-09
Also published as: WO2002021261A2; US7085198B2; US20040027924A1; AU2001289575A1; WO2002021261A3

Abstract

The invention relates to a method for producing a computer-assisted real-time system that comprises at least one processing unit. Data exchange between said processing unit and the environment or one or more additional processing units is synchronous or asynchronous. At least one real clock is allocated to the processing unit to correlate data exchange, said clock being defined by the following relation (a).

Description

description

Process for the production of computerized real-time systems

The invention relates to a method for producing computer-based real-time systems with at least one processing unit according to the preamble of claim 1. It also relates to a computer system which has been designed to carry out the method.

Real-time systems are generally understood to be systems which have to deliver a specific computing result at a predetermined point in time and / or after a predetermined period of time has elapsed. For example, the time required to convert speech into digital signals and their transmission and the subsequent reconversion of the digital signals into an analog audio signal is approximately 250 ms, i.e. communication via mobile telephone devices takes place with a time delay of 250 ms. If the time delay is greater than 250 ms, the transmitted language is no longer understandable.

Computer-based real-time systems with several processing units, so-called distributed real-time systems, are widely used in the prior art. For example, mobile phones, their switching systems and networks are such a distributed real-time system.

A distributed real-time system can consist of several processing units. They can be components of one and the same device. However, it may also be the case that processing units, such as a mobile telephone and a switching system, are spatially separated from one another. Distributed real-time systems are produced on the basis of abstract specifications, such as, for example, the "Specification and Description Language" known under the abbreviation "SDL" (ITU-T. Z. 100, Appendix I. ITU, SDL Methodology Guidelines, ITU, 1993 ). SDL is based on the technical principle that a queue is assigned to each processing unit or process. It is imperative that the data exchange or communication between the processing units, which usually takes place via a bus, takes place exclusively via the queue, with all processes running in parallel.

In order to correlate the data exchange, each processing unit is also assigned at least one so-called timer module. It is a numerical counter. Its counting period is not standardized; it can be derived from the processor clock. It depends on the hardware selected and / or the respective program. As a result, it has so far not been reliably possible to automatically implement an abstract specification of hardware and software for the real-time-dependent layers of a communication system. The implementations are either too slow or they do not meet the time constraints. In order to counteract this disadvantage, the hardware is specified using circuit diagrams or using hardware description languages and then implemented. The software is mostly implemented using programming languages. The known method is time-consuming and costly and prone to errors.

In addition to SDL, there are other implementation languages in which clocks can be integrated as components. For example, with the unified modeling known under the abbreviation "UML" Language can be accessed on clocks. Another implementation language is the Very High speed integrated circuit hardware description language known under the abbreviation "VHDL". Both UML and WHDL do not require queues.

From Kopetz, H., Ochsenreiter, W.: Clock Synchronization in Distributed Real-Time Systems; in IEEE Trans, on Computers, Vol. C-36, No.8, August 1987, a generic method for the production of a computer-based real-time system is known. A specification of a real watch which eliminates the aforementioned disadvantages from the prior art is not known from the aforementioned document.

The object of the invention is to eliminate the disadvantages of the prior art. In particular, a method is to be specified with which real-time systems can be produced simply, quickly and inexpensively. An automatic implementation of an abstract specification of real-time systems should be made possible. Another object of the invention is to avoid errors in the manufacture of real-time systems.

This object is solved by the features of claims 1 and 10. Appropriate configurations result from the features of claims 2 to 9.

According to the invention, a method for producing a computer-based real-time system with at least one processing unit is provided, in which the real clock is defined by the following relationship: (T)

(t; G mod R „where C _r (t) e R in [sec]

T r

in which

R _v : range of values, R _v GR ⁺ in [sec],

G _r : granularity, G _r C (R ⁺ in [sec],

where G _r and R _v are normalized to the smallest occurring value,

T: clock period, TGR ⁺ in [sec], where

C _c (t) = [1 + g] • Ci (t) + G (p ^→ , t) + S ₀ , where C _c (t) 6 R in [sec]

(t) = t; t G R in [sec]

g: accuracy of the clock, g e R, e.g. the quartz accuracy in ppm.

g (p ^→ , t): Accuracy change of the clock over time depending on physical quantities, represented by the vector p ^→ , e.g. the temperature, g (p ^→ , t) G IR * 2

G (p ^"* '. # Tt)) == J j cg (p ^{" *} , t) dt as effective change of accuracy in a time interval (t - ti), G (p ^→ , t) G IR in [sec]

S ₀ : start offset, S _Q G IR in [sec]

The method according to the invention makes it possible to mark data, data packets or data streams in a computer system with a precise time stamp that is independent of the system logic. This opens up completely new freedom in the specification, especially of distributed real-time systems. With a specification produced according to the method according to the invention, the implementation problems according to the prior art are eliminated. The real time can already be taken into account when analyzing the functional and temporal behavior and the subsequent specification. The proposed method makes it possible to specify a universal design pattern which is suitable for the production, in particular of distributed real-time systems, in a very wide variety of application areas. The formal consideration of time requirements possible with the method according to the invention also makes it possible to specify the real-time-dependent layers of a communication system and to automatically derive efficient implementations therefrom.

Furthermore, it is possible to define relationships between the clocks in distributed real-time systems that are not implemented in a device. For example, the offset of two clocks at time t results from the relationship: 0 ^1D (t) = C ^x (t) - C ^D (t)

Using this model e.g. Synchronization algorithms are specified and validated.

A numerical counter assigned to the processing unit can be controlled by means of the clock. When using several of the clocks, one of the clocks advantageously serves as a reference clock for synchronizing the other clocks. This enables an orderly data exchange between the processing units.

The term "environment" is understood here to mean a technical process. To control or regulate a technical

Processes, the data exchange with the processing units can expediently be carried out in real time-controlled manner. In this context, the technical processes can e.g. to control a chemical factory, an anti-lock braking system of a motor vehicle, a mobile radio network and the like. act.

A data stream received by a processing unit and formed from a sequence of data packets and a transmitted data stream can expediently be decoupled, so that the transmitted data stream can have a sequence of data packets that is different from the received data stream. This makes it possible to manage various real-time-dependent data streams on the Internet. The transmission speed can be increased drastically for certain data streams. It is no longer necessary to process the sequence of data packets arriving at the processing unit sequentially and to send them again in the same order. A queue can be assigned to the processing unit. The queue is advantageously time-controlled, preferably with the further clock according to the invention serving as a reference clock. In this way, time-controlled data can be written to the queue or read from the queue.

According to a further design feature, the data packets are provided with a real time stamp generated by the clock. Marking by means of real time stamps makes it possible to send a predefined sequence of data packets, the sequence being changed for transmission and the predefined sequence of data packets subsequently being restored. This can increase the transmission speed.

It is particularly advantageous to use the clock to define time limits, in particular time conditions or time requirements. Time conditions are understood to mean conditions under which the system carries out a specified action at a specified time. Time requirements, on the other hand, are system requirements that a specific event has occurred after a specified time has elapsed. This can also be an external event.

According to a further provision of the invention, a computer system is provided which is suitable for carrying out the method according to the invention. With such a computer system, a precise automatic implementation of abstract specifications of software and hardware for real-time systems can be carried out quickly and easily. Preferred exemplary embodiments of the method according to the invention are explained in more detail below. Show it:

1 is a graph for the definition of the real clock,

2 schematically shows the SDL process with a real clock,

3 shows a synchronized distributed real-time system in SDL,

4a the specification of clocks and access via abstract data types,

4b the specification of time barriers and access via abstract data types,

5 the specification of time requirements and access via abstract data types,

6 shows the implementation of a design pattern,

Fig. 7 the specification of a switching computer with traffic monitoring and

8 shows the structure of the outputs of the switching computer according to FIG. 7.

9a-d the specification with different architecture variants,

1 explains the differences between an ideal, a continuously real, a discrete real and one derived counter. An ideal watch is defined by a linear function.

Ideal watch:

The solid line in Fig. 1 represents the function of the ideal clock according to the following formula:

Ci (t) = t; t e R in [sec]

The continuous real clock requires further parameters. The continuous real clock has a constant accuracy. This accuracy is usually given in parts per million (ppm).

In addition, it must be taken into account that the cycle period of a continuous real clock can fluctuate due to fluctuations in physical parameters such as temperature. This is expressed by a function g (p ^→ , t). Where p ^{→ is} a vector with the required physical parameters depending on their changes over time. However, the function g (p ^→ , t) is not used in the equation of the continuous, real clock, but because it can be periodic fluctuations, the function

^fc 2

G (p ^"* , t) = J gg ((pp ^{" *} V, t) dt of the effective change in accuracy t 1

G (p ^→ , t) G IR in [sec] If, for example, periodic fluctuations occur, it can happen that the inaccuracies of the clock are averaged out over a time interval (t ₂ - ti). With these definitions, the continuous real clock is described by the following equation:

C _c (t) = [1 + g] ^■ Ci (t) + G (p ^→ , t) + S ₀ , where C _c (t) G IR in [sec]

d (t) = t; t G IR in [sec] where

g: accuracy of the clock, g G IR, e.g. the quartz accuracy in ppm.

g (p ^→ , t) Accuracy change of the clock over time as a function of physical quantities, represented by the vector p ^→ , e.g. the temperature, g (p ^→ , t) G IR

G (p ^"* ,, tt)) ₌ = JJ g (p ^{" *} , t) dt as an effective change in accuracy

in a time interval (t ₂ - ti) G (p ^→ , t) G IR in [sec]

S ₀ : start offset, S _Q G IR in [sec]

A technical process cannot be broken down into infinitely small periods. Every technical watch vibrates with a finite frequency. The frequency correlates to the clock period T of the clock. The smallest readable interval of the discrete real clock is defined as granularity G. The formal Mapping the ideal clock to the discrete real clock is given by the following relationship:

Discrete real clock:

(t)

(t) = mod R _v , where C _r (t) G IR in [sec]

T

in which

C _r (t) G IR

R _v : range of values, R _v G IR ⁺ in [sec],

G _A : Granularity, GG IR ⁺ in [sec], where G and R _v are normalized to the smallest unit that occurs.

Clock period, T 6 R ⁺ in [sec]

C _c (t)

The discretization of time is described by OperationL T. R _v describes the range of values of the discrete real clock. After R _v time units, the discrete real clock shows 0 again. This is described in the equation by the modulo operation. The inaccuracy G (p ^→ , t) does not appear directly here. The cycle period T, the granularity G _r, the start offset S _Q and the value range R _v are to be specified in seconds.

C _c (t)

A controlled by the discrete clock T.

Counter is described by the following relationship C _c (t-

(t) = TG _A mod R _A

N _A

in which

C _A (t) G 2

T: clock period of the discrete real clock, TG IR ⁺ in [sec],

N _A : number of changes, N _A GN ⁺

G _A : granularity of the derived counter, G _A GN ⁺ ,

R _A : Range of values of the derived counter, R _A G IM ⁺ ,

T: delay time, TG IR ⁺ {o} in [sec]

The delay time for setting the derived counter is T. N _A is the number of ad changes in the discrete th real pm until the meter is again changed. The granularity G _A indicates the interval change of the display. R _A describes the range of values of the derived counter.

Fig. 2 shows schematically the structure of a processing unit in SDL or a so-called "SDL process". According to the invention, one or more timers provided according to the conventional SDL concept are connected to a real clock. How from 3 can be seen, it is thus possible to synchronize the timers of different SDL processes.

An incoming signal shown in FIGS. 2 and 3 can be provided with a time stamp, which is a real time stamp.

4a shows the definition of a set of abstract data types in SDL, with which it is possible to access the display of the real clocks, to reset the real clocks or to reset them to predetermined values at certain real times.

With the method according to the invention, design patterns for the automatic derivation of hardware and software from embedded, distributed real-time systems can be specified. A useful part of such a design pattern is the formulation of time barriers. For this purpose, it is particularly necessary that the programming language used can generate time stamps. This can e.g. by querying the system time. Possible time requirements for such a design pattern - such as shown in Fig. 5 are:

a) A first time requirement for the periodic occurrence of the READ state, ie for the execution of the control branch and a state transition 1. The first time requirement results from the rate of the received data stream. It stipulates that on average, as many data words can be read from the queue as the maximum number of words that can be written into them. The first time request only applies if data words are in the queue. b) The second time requirement stipulates that in the case of a medium supporting the data rate R, a signal “output” must be generated for the utilization of the medium every 1 / R time units. The second time requirement only applies if data words are stored in the memory of the design pattern.

The data type "Eventclass" shown in FIG. The following operations are available that are suitable for defining time conditions and time requirements:

Append: enters the current system time in a list of time stamps;

Durationevent Calculates the duration between two time stamps entered in the list and

Monitor: In the event of an error, records the results of the time check and writes them to an appropriate output device.

ThrowException: Calls exception processing in the event of an error in order to e.g. to drive to a safe state.

Examples of building blocks using the pattern:

The respective functionality of the pattern in different applications or as a module is ultimately determined by the functions Sortinto () and SortOut (). If the design pattern is used in communication systems, eg to implement scheduling algorithms, time or frequency multiplexers or bandwidth allocations, the Sortinto () function each data word with a time stamp. SortOut () then reads the data words in a defined order according to their time stamp. It is also possible to carry out traffic monitoring (policy) in the Sortinto () function. It is determined whether the sender of a data stream complies with an agreed quality of service (QoS: Quality of Service). At this point, the route information (address, telephone number, or path number in ATM) of the packet can be evaluated and the destination of the sending function can be determined.

When implementing control or regulation algorithms, on the other hand, the respective manipulated variable calculation is carried out in the SortOut () function, while the Sortinto () function stores the sensor values (controlled variables).

In this way, several values can first be collected before the actual calculation is carried out.

Automatic derivation of mixed HW / SW systems:

The design pattern described in the previous section can be easily implemented in an implementation. For this purpose, state transition 1 and state transition 2 are considered separately. Decoupling makes it possible to define a separate software or hardware module for each state transition. The respective Einzw. Output module again represent a mixed HW / SW implementation. The module's input and output transitions can be overlapped (pipelining), since synchronization between the two state transitions can take place via the shared memory of the internal buffer. Such an approach allows the Reduce implementation effort drastically and increase execution speed significantly. 6 shows an example of how the design pattern can be implemented. Each part of the pattern can be implemented either in hardware or in software. The following combinations are possible during implementation:

All modules are implemented in hardware and software, state transition 1 and Sortinto () are implemented in hardware, while state transition 2 and SortOut () are implemented in software, state transition 1 and Sortinto () are implemented in software, while state transition 2 and SortOut () are implemented in hardware, • Sortinto () is implemented in hardware, all others

Parts in software,

SortOut () is implemented in hardware, all others

Parts in software,

Sortinto () and SortOut () are implemented in hardware, the rest of the process is implemented in software.

A great advantage is that different synthesis techniques can be used for all four subtasks. Suitable synthesis techniques are from 0. Bringmann et al. , Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping, 10 ^th IEEE International Workshop on Rapid System Prototyping, Clearwater, June 1999. Since the functions Sortinto () and SortOut () usually have a high algorithmic component, the architecture synthesis lends itself to them, ie for the functions a special, application-specific processor is generated with the help of a tool. If the two state transitions are implemented in hardware, they can be used directly without the use of optimizing drive (synthesis) into a simple hardware description at the register transfer level (RTL: register transfer level). This conceptual separation also considerably simplifies the hardware / software partitioning of the respective state transition.

The pipelining of the two modules is possible if both modules do not want to access the same memory cell of the memory at the same time. The semantics of the design pattern are always preserved, since if one is accessed at the same time, one of the two functions is stopped and waits until the other function is finished.

Design of complex systems with the building blocks:

The construction of a more complex system using components that can be derived from the described design pattern is explained using the example of a switching computer for data services with QoS requirements. The basic building blocks traffic monitoring (policy) and bandwidth allocation (scheduler) are realized by instances of the design pattern.

The left side of Fig. 7 shows the basic structure of the system. The incoming data streams, in the example these are 2, are analyzed with the help of a traffic monitoring (policy). Traffic monitoring is implemented using the design pattern (right side in Fig. 7). For this purpose, the Sortinto () function, as shown in Fig. 7, has been defined.

In such a switching computer, a distinction is still made between control information and user data. Does the data contain tenstrom control information, this is sent to the control module Control. The usual telecommunications protocols are then processed in this module. The information that describes the data flow (mediation) through the system is generated in Control. To do this, the OutPID variable is set in Control's traffic monitoring. The switching is realized in that there are several instances of the scheduler module (FIG. 8), for example one for each output line, and the data words are sent from the traffic monitoring to the corresponding bandwidth allocator. The addressing (using the OutPID variable) of the corresponding bandwidth allocator (scheduler) assigns a data stream to an output channel.

In principle, it is possible for there to be several traffic monitors at the entrance (n entrances) and several scheduler-type modules (m exits) at the exit.

Determining which bandwidth-limited channel is implemented at this point depends on the cost and system requirements. In principle, the bandwidth of the connecting channel is infinite. Some possible variants are described in the following section as examples.

Automatic derivation of a complex system

9a shows the basic structure of the switching computer on the specification level. Various architectures can now be derived from this. Software modules are implemented on processors (abbr. CPU), while hardware modules are "cast" in ASICs (application specific integrated circuits). In the picture, a filled circle is supposed to be one instance of each Represent design patterns, using abbreviations P for Policy or S for Scheduler, C for Control. Communication channels can be mapped to buses or switching modules.

The implementation in FIG. 9b has a processor for processing the two traffic monitoring entities [policy], three hardware modules for the bandwidth allocation modules (scheduler), a bus for the transmission of data words and a bus for control information. In contrast to this, the architecture in FIG. 9c consists of three processors for the control and traffic monitoring instances and a hardware module for implementing the schedulers.

In contrast, in FIG. 9d, the switching functionality is not implemented with the aid of a common bus, but rather via a switching module (space multiplexer).

Of course, all other combinations of software and hardware modules are also conceivable. e.g. only part of the scheduler could be implemented in hardware and the rest in software. Except for the Control module for implementing the telecommunication protocols, all components of the switching computer can be implemented by different instances of the design pattern.

Claims

claims

1. Method for producing a computer-aided real-time system with at least one processing unit (Via, Vlb, ...),

wherein data exchange between the processing unit Via, Vlb, ...) and the environment or one or more further processing units (V2a, V2b, ...) is carried out synchronously or asynchronously, and

at least one real clock being assigned to correlate the data exchange taking place in a computer system (Via, Vlb, ...), characterized in that the real clock is defined by the following relationship:

C _c (t)

(t) = G mod R _v r

in which

C _r (t) GR in [sec]

R _v : range of values, R _v G IR ⁺ in [sec],

G _r : granularity, GG IR ⁺ in [sec], where G _r and R _v are normalized to the smallest unit occurring.

T: clock period, TG IR ⁺ , in [sec], C _c (t) = [1 + g] d (t) + G (p-, t) + S _o; where C _c (t) G IR in [sec]

Ci (t) = t; t G IR, in [sec] g: accuracy of the clock, g G IR, e.g. the quartz accuracy in ppm.

g (p ^→ , t) Accuracy change of the clock over time depending on physical quantities, represented by the vector p ^→ e.g. the temperature, g (p ^→ , t) G IR

G (p ^* , t) (p ^"* , t) dt, as an effective change in accuracy in a time interval (t ₂ - ti)

S ₀ : start offset, S ₀ G IR in [sec]

2. The method according to claim 1, wherein a numerical counter assigned to the processing unit (Via, Vlb, ...) is controlled by means of the clock according to the following relationship.

in which

(t): G Z

T: clock period of the discrete real clock, TG IR ⁺ in [sec] N _A : number of changes, N _A GM ⁺

G _A : granularity of the derived counter, G _A GN ⁺ , R _A : range of values of the derived counter, R _A GN ⁺ ,

T: delay time, r 6 IR ⁺ {o} in [sec].

3. The method according to any one of the preceding claims, wherein one of the clocks serves as a reference clock for synchronizing the other clocks.

4. The method according to any one of the preceding claims, wherein to control or regulate a technical process, the data exchange with the processing units (Via, Vlb, ... V2a, V2b, ...) is carried out in real time.

5. The method according to any one of the preceding claims, wherein a data stream received from a processing unit (Via, Vlb, ... V2a, V2b, ...) formed from a sequence of data packets and a transmitted data stream are decoupled, so that the sent data stream has a different sequence of data packets from the received data stream.

6. The method according to any one of the preceding claims, wherein the processing unit (Via, Vlb, ...) is assigned a queue.

7. The method according to claim 6, wherein the queue with the clock, preferably with the clock serving as a reference clock, is time-controlled.

8. The method according to any one of the preceding claims, wherein the data packets are provided with a real time stamp generated by the clock.

9. The method according to any one of the preceding claims, wherein time limits, in particular time conditions or time requirements, are defined with the clock.

10. Computer system prepared for carrying out the method according to one of the preceding claims