EP1320877A2 - Silicon oxide patterning using cvd photoresist - Google Patents

Silicon oxide patterning using cvd photoresist

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Publication number
EP1320877A2
EP1320877A2 EP01964510A EP01964510A EP1320877A2 EP 1320877 A2 EP1320877 A2 EP 1320877A2 EP 01964510 A EP01964510 A EP 01964510A EP 01964510 A EP01964510 A EP 01964510A EP 1320877 A2 EP1320877 A2 EP 1320877A2
Authority
EP
European Patent Office
Prior art keywords
layer
silicon oxide
substrate
hydrocarbon
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01964510A
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German (de)
French (fr)
Inventor
Gill Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies North America Corp
Original Assignee
Infineon Technologies North America Corp
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Filing date
Publication date
Application filed by Infineon Technologies North America Corp filed Critical Infineon Technologies North America Corp
Publication of EP1320877A2 publication Critical patent/EP1320877A2/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6506—Formation of intermediate materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
    • H10P14/6519—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being oxygen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6536—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light
    • H10P14/6538—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light by exposure to UV light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6548—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by forming intermediate materials, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/6903—Inorganic materials containing silicon
    • H10P14/6905—Inorganic materials containing silicon being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H

Definitions

  • the present invention relates generally to integrated circuits ("IC”s) and their fabrication, and more particularly to silicon oxide patterning using chemical vapor deposition ("CVD”) photoresist .
  • IC integrated circuits
  • CVD chemical vapor deposition
  • Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today's semiconductor products. For example, it is not uncommon for there to be millions of semiconductor devices or more on a single semiconductor product.
  • a patterned layer may be formed on an integrated circuit through the use of photolithography.
  • a 600 nm thick spin-on photoresist is typically applied to a substrate over a layer to be patterned (e.g., silicon dioxide) .
  • the thickness of the photoresist may vary from 300-1500 nm, although other thicknesses may be used.
  • Portions of the photoresist may then be exposed to some form of radiation (e.g., light, electrons, ions) through a photolithographic mask.
  • the photoresist is then chemically developed, wherein either the exposed portion or unexposed portion of the photoresist may be removed, depending on whether a positive or negative resist is used, respectively.
  • the photoresist should provide adequate etch resistance or selectivity so that the unexposed portions of the underlying layer are protected while the exposed portions of the layer are etched away during the subsequent etching process. Therefore, a sufficient thickness of photoresist is typically required to perform a successful etch.
  • the vertical to horizontal aspect ratio of the patterned photoresist continues to increase.
  • the higher the aspect ratio the less mechanically stable the photoresist.
  • an aspect ratio above 4:1 may not be workable for many applications.
  • a 0.15um minimum feature size would limit the photoresist thickness to less than 0.6um.
  • thinner photoresists with sufficient etch selectivity are generally needed to enlarge the photolithographic process window, and to provide stable mechanical masks during the subsequent etching step.
  • CVD photoresists generally avoid the problems associated with spin-on photoresists.
  • CVD photoresist may be formed in a thinner layer than a spin-on photoresist, thus providing mechanical stability and a larger process window.
  • a CVD photoresist layer may have a typical thickness of 150 nm, with a thickness range of 30-500 nm, although other thicknesses may be used.
  • CVD photoresist may provide superior etch mask properties, such as high selectivity to silicon oxide, aluminum and its compounds, tungsten and its compounds, polysilicon, and so on.
  • CVD photoresist is plasma polymerized met ylsilane ("PPMS").
  • PPMS is a photosensitive material which is transformed into CH 3 -contained silicon oxide (PPMS oxide (“PPMSO”)) after being exposed to ultraviolet ( "UV” ) light in air .
  • PPMSO plasma polymerized met ylsilane
  • hydrocarbon e.g., methyl
  • etch masks there are generally several problems, however, with using hydrocarbon (e.g., methyl) contained silicon oxides, as etch masks.
  • hydrocarbon e.g., methyl
  • these materials are effectively silicon oxide with CH 3 bonds, they generally do not have sufficient etch selectivity with respect to other silicon oxides.
  • the application of PPMSO or equivalent CVD photosensitive materials is generally limited to non-oxide patterning.
  • photosensitive methyl-contained silicon oxides generally do not provide as high a quality silicon oxide as conventional plasma enhanced CVD ("PECVD") processes.
  • PECVD plasma enhanced CVD
  • these materials are susceptible to moisture absorption. Therefore these materials by themselves generally cannot be left on the substrate to function as an oxide layer, and they generally have to be removed from the substrate after the subsequent etching process that uses their hard mask properties .
  • CVD photoresist e.g., PPMS
  • silicon oxide e.g., PPMSO
  • a high quality cap layer e.g., PECVD silicon oxide or nitride
  • PECVD silicon oxide or nitride may then be formed over the lower quality silicon oxide layer (e.g., PPMSO) utilizing a maskless etch process.
  • an additional high quality silicon oxide layer may also be formed on the substrate prior to formation of the CVD photoresist layer.
  • the cap layer may be used to protect the lower quality silicon oxide layer from moisture absorption.
  • a method of forming a patterned silicon oxide layer in an integrated circuit comprises forming a patterned hydrocarbon-contained silicon oxide layer on a first layer of a substrate; and forming a insulating cap layer encasing the patterned hydrocarbon-contained silicon oxide layer.
  • a method of forming a patterned silicon oxide layer in an integrated circuit comprises depositing a chemical vapor deposition (CVD) photoresist layer on a first layer of a substrate; exposing first regions of the CVD photoresist layer to radiation, wherein the exposing converts the CVD photoresist in the first regions into hydrocarbon-contained silicon oxide; removing unexposed second regions of the CVD photoresist layer from the substrate, thereby exposing the first layer in the second regions; depositing a conformal insulating layer on the substrate, wherein the conformal layer is thicker on an upper horizontal surface of the hydrocarbon-contained silicon oxide than on other surfaces on the substrate; and removing the conformal layer from the second regions, thereby exposing the first layer in the second regions, and thereby forming an insulating cap layer encasing the hydrocarbon-contained silicon oxide .
  • CVD chemical vapor deposition
  • an integrated circuit comprises a patterned hydrocarbon-contained silicon oxide layer overlying a first layer of a substrate; and a cap layer encasing the patterned hydrocarbon-contained silicon oxide layer.
  • the hydrocarbon- contained silicon oxide is preferably plasma polymerized methylsilane oxide, and the cap layer is preferably selected from the group consisting of silicon oxide, silicon nitride, and combinations thereof.
  • An advantage of a preferred embodiment of the present invention is that it provides a simplified oxide patterning technique. Overall process steps may be reduced from the number of steps in prior art techniques. In addition, raw process time in the oxide etching step may be reduced.
  • Another advantage of a preferred embodiment of the present invention is that a thinner photoresist may be used because the technique does not require etch resistance or selectivity.
  • the thickness may generally be determined solely by the requirement of the thickness of the oxide layer being patterned.
  • Another advantage of a preferred embodiment of the present invention is that the thinner photoresist layer permits a larger lithographic process window and increased depth of focus, enabling a more robust process than that used in the prior art.
  • FIGURES 1-6 are cross-sectional views of a prior art integrated circuit structure at various stages of fabrication
  • FIGURES 7-10 are cross-sectional views of an integrated circuit structure in accordance with a preferred embodiment of the present invention at various stages of fabrication;
  • FIGURES 11-15 are cross-sectional views of an integrated circuit structure in accordance with another preferred embodiment of the present invention at various stages of fabrication.
  • FIGURES 16-19 are cross-sectional views of an integrated circuit structure in accordance with another preferred embodiment of the present invention at various stages of fabrication.
  • the invention relates to integrated circuits, including memory ICs, microprocessor ICs, logic ICs, analog and mixed signal ICs, or other ICs comprising a patterned oxide layer.
  • the invention also relates to semiconductor processes and structures, including insulating layers such as capacitor dielectrics, field oxides, or gate oxides, or other processes and structures comprising an oxide layer.
  • Figures 1-6 illustrate cross-sectional views of a well known conventional prior art method of patterning a silicon oxide layer.
  • a silicon oxide layer 102 is formed on silicon substrate 100.
  • the substrate may be gallium arsenide or another form of silicon such as silicon on insulator.
  • Oxide layer 102 may be grown using a local oxidation of silicon process, or deposited using a PECVD silane based or tetraethyloxysilane ("TEOS”) based process.
  • TEOS tetraethyloxysilane
  • ARC anti-reflective coating
  • Spin-on photoresist layer 106 is then deposited on ARC layer 102 using a spin-on method.
  • portions of spin-on photoresist layer 106 are exposed to radiation through a photolithographic mask, followed by development of photoresist layer 106 using an appropriate chemical etch. As shown in Figure 3, the exposed (positive resist) or unexposed (negative resist) portions of spin-on photoresist layer 106 are removed from the substrate, resulting in patterned photoresist layer 108.
  • ARC layer 104 are etched using patterned photoresist layer 106 as a mask to form patterned ARC layer 110.
  • Exposed portions of silicon oxide layer 102 are then etched, again using patterned photoresist layer 106 as a mask.
  • patterned photoresist layer 108 may have etch characteristics similar to that of silicon oxide layer 102, patterned photoresist layer 108 must generally be of sufficient thickness so that a portion of it remains after the etching of silicon oxide layer 102 is complete.
  • the resulting structure is illustrated in Figure 5, with patterned silicon oxide layer 114 shown underlying patterned ARC layer 116 and etched photoresist layer 108.
  • photoresist layer 108 and ARC layer 116 are stripped off the substrate, leaving patterned silicon oxide layer 114 formed on substrate 100, as illustrated in Figure 6.
  • the thicker photoresist required for the silicon oxide etching step narrows the lithographic process window and reduces process robustness due to the decrease in the depth of focus along with the decrease in minimum feature size.
  • FIG. 7 illustrates 150 nm thick CVD photoresist PPMS layer 202 deposited on silicon substrate 200 using a vacuum CVD system.
  • Typical process parameters for the PPMS deposition process are a temperature of 150° C, a pressure of 8 Torr, and an RF power of 300 W.
  • the temperature may vary between 0°-300° C
  • the pressure may vary between 1-20 Torr
  • the RF power may vary between 100-1000 , although other parameter ranges may be used.
  • the thickness of PPMS layer 202 may be 100-300 nm, although other thicknesses may be used.
  • the resist may be formed using any carbon-containing or hydrocarbon- containing silane gas, such as mono-methylsilane, bi- methylsilane, 3-methylsilane or 4-methylsilane (all of which are referred to herein simply as methylsilane) .
  • the substrate may be gallium arsenide or another form of silicon such as silicon on insulator.
  • portions of PPMS layer 202 are exposed to ultraviolet light (e.g., 248 nm, 193 nm or 157 nm wavelengths) through a photolithographic mask in an air atmosphere.
  • ultraviolet light e.g., 248 nm, 193 nm or 157 nm wavelengths
  • the exposed portions of PPMS layer 202 are converted into PPMSO, a CH 3 -contained silicon oxide.
  • the unexposed portions of layer 202 are then removed from the substrate using an appropriate chemical etch, leaving patterned PPMSO layer 204, as shown in Figure 8.
  • a PPMSO layer generally could not be used as a mask to pattern a silicon oxide layer because it does not possess sufficient etch selectivity.
  • cap layer 206 overlying PPMSO layer 204.
  • the thickness of cap layer 206 may be 10-100 nm, although other thicknesses may be used.
  • Cap layer 206 is preferably silicon oxide, but alternatively another insulator such as a silicon nitride cap layer may be used. The capping process prevents moisture absorption into PPMSO layer 204.
  • cap layer 206 is about twice as thick in region 208 directly overlying PPMSO layer 204 as it is in region 210 directly overlying substrate 200. This is generally because the PECVD silane based oxide process produces about 40% bottom step coverage relative to top step coverage, and the TEOS based oxide process produces about 50% to 60% bottom step coverage, depending on the aspect ratio of the step structure .
  • a maskless or self-aligned etch process may be used to punch through the portions of cap layer 206 covering the substrate in region 210, in order to clear the insulator from the contact area. Because cap layer 206 is much thinner in region 210 than in region 208, a conventional anisotropic silicon oxide etch process may be used to open the contact area without re-exposing PPMSO layer 204 underlying the thicker portions of cap layer 206.
  • the resulting structure is illustrated in Figure 10, with cap layer 212 encasing PPMSO layer 204, and substrate 200 exposed in region 214.
  • CVD photoresist is not used as a mask to etch an underlying silicon oxide layer, a thinner CVD photoresist layer may be used.
  • the thickness of the CVD photoresist may be determined solely by the final desired thickness of the oxide layer being patterned.
  • FIG. 11-15 cross-sectional views are illustrated of another preferred embodiment method of forming a patterned silicon oxide layer using CVD photoresist.
  • a high quality oxide liner on the substrate to provide a buffer between the substrate and the PPMSO layer, and to completely encircle the PPMSO layer with a high quality oxide. Therefore, in this embodiment, as shown in Figure 11, a 50 nm thick silicon oxide liner 302 is deposited on substrate 300 prior to the deposition of CVD photoresist PPMS layer 304.
  • the thickness of oxide liner may be 10-100 nm, although other thicknesses may be used.
  • Oxide liner 302 may be formed using any high quality oxide formation process, such as LOCOS, or those used to form the cap layer in the previous embodiment. Alternatively, another insulator such as silicon nitride may be used as the liner.
  • portions of PPMS layer 304 are exposed to ultraviolet light through a photolithographic mask in an air atmosphere.
  • the exposed portions of PPMS layer 304 are converted into PPMSO, a CH 3 -contained silicon oxide.
  • the unexposed portions of layer 304 are then removed from the substrate using an appropriate chemical etch, leaving patterned PPMSO layer 306 overlying silicon oxide liner 302, as shown in Figure 12.
  • an anisotropic etch process may be used to remove the exposed portions of oxide liner 302. This process will generally also etch the PPMSO layer 306 because of the similarity of the materials. Therefore PPMSO layer 306 should generally be of sufficient thickness to permit removal of the exposed oxide layer 302.
  • the resulting structure comprises PPMSO layer 310 overlying patterned oxide liner 308.
  • cap layer 312 is preferably silicon oxide, but alternatively a silicon nitride cap layer may be used.
  • cap layer 312 is about twice as thick in the region directly overlying PPMSO layer 310 as it is in the region directly overlying substrate 300. Therefore, a maskless or self-aligned etch process may be used to punch through the portions of cap layer 312 directly overlying the substrate, in order to clear the insulator from the contact area.
  • a conventional anisotropic silicon oxide etch process may be used to open the contact area without re-exposing PPMSO layer 310 underlying the thicker portions of cap layer 312.
  • the resulting structure is illustrated in Figure 15, with cap layer 314 and oxide liner 308 encompassing PPMSO layer 310, and with substrate 300 exposed in the remaining regions.
  • Cap layer 314 and oxide liner 308 together provide a high quality oxide completely surrounding PPMSO layer 310.
  • FIG. 16-19 cross-sectional views are illustrated of another preferred embodiment method of forming a patterned silicon oxide layer using CVD photoresist.
  • a high quality oxide liner is again deposited on the substrate, but it is etched at a different point in the process.
  • silicon oxide liner ,.402 is deposited on substrate 400 prior to the deposition of CVD photoresist PPMS layer 404.
  • Oxide liner 402 may be formed using any high quality oxide formation process, such as LOCOS, or those used to form the cap layer in the previous embodiment .
  • another insulator such as silicon nitride may be used as the liner.
  • portions of PPMS layer 404 are exposed to ultraviolet light through a photolithographic mask in an air atmosphere.
  • the exposed portions of PPMS layer 404 are converted into PPMSO, a CH 3 -contained silicon oxide.
  • the unexposed portions of layer 404 are then removed from the substrate using an appropriate chemical etch, leaving patterned PPMSO layer 406 overlying silicon oxide liner 402, as shown in Figure 17.
  • cap layer 408 is preferably silicon oxide, but alternatively a silicon nitride cap layer may be used. Similar to the previous embodiments, and as can be seen in Figure 18, cap layer 408 is about twice as thick in the region directly overlying PPMSO layer 406 as it is in the region directly overlying oxide liner 402. Therefore, a maskless or self-aligned etch process may be used to punch through the portions of both cap layer 408 and oxide liner 402 directly overlying the substrate, in order to clear the insulators from the contact area.
  • a conventional anisotropic silicon oxide etch process may be used to open the contact area without re-exposing PPMSO layer 406 underlying the thicker portions of cap layer 408, as long as the thick top step of cap layer 408 is thick enough to withstand the etching of both the thin bottom step of cap layer 408 and oxide layer 402.
  • the resulting structure is illustrated in Figure 19, with cap layer 410 and oxide liner 412 encompassing PPMSO layer 406, and with substrate 400 exposed in the remaining regions. Cap layer 410 and oxide liner 412 together provide a high quality.oxide completely surrounding PPMSO layer 406.
  • the remainder of an integrated circuit may be formed using conventional IC processing techniques.
  • the resulting IC may then be employed in a variety of commercial and consumer electronics devices, including computers.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

An integrated circuit, and method of forming thereof, in which a CVD photoresist (e.g., PPMS) is formed on a substrate (e.g., silicon 200), patterned and converted into silicon oxide, and is left on the substrate to function as a silicon oxide layer (e.g., PPMSO 204). A high quality cap layer (e.g., PECVD silicon oxide 206) may then be formed over the lower quality silicon oxide layer utilizing a maskless etch process. A high quality silicon oxide layer may be formed on the substrate prior to formation of the CVD photoresist layer to provide a buffer underneath the lower quality silicon oxide. Because etch selectivity is generally not required for the photoresist layer, a thinner photoresist may be used than that of prior art techniques, permitting a larger lithographic process window, increased depth of focus, and a more robust process.

Description

SILICON OXIDE PATTERNING USING CVD PHOTORESIST
TECHNICAL FIELD
The present invention relates generally to integrated circuits ("IC"s) and their fabrication, and more particularly to silicon oxide patterning using chemical vapor deposition ("CVD") photoresist .
BACKGROUND
The semiconductor industry is continuously trying to decrease the size of the semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today's semiconductor products. For example, it is not uncommon for there to be millions of semiconductor devices or more on a single semiconductor product.
As is well known in the art, a patterned layer may be formed on an integrated circuit through the use of photolithography. A 600 nm thick spin-on photoresist is typically applied to a substrate over a layer to be patterned (e.g., silicon dioxide) . The thickness of the photoresist may vary from 300-1500 nm, although other thicknesses may be used. Portions of the photoresist may then be exposed to some form of radiation (e.g., light, electrons, ions) through a photolithographic mask. The photoresist is then chemically developed, wherein either the exposed portion or unexposed portion of the photoresist may be removed, depending on whether a positive or negative resist is used, respectively.
Generally, the photoresist should provide adequate etch resistance or selectivity so that the unexposed portions of the underlying layer are protected while the exposed portions of the layer are etched away during the subsequent etching process. Therefore, a sufficient thickness of photoresist is typically required to perform a successful etch.
On the other hand, as the minimum feature size continues to shrink in semiconductor technology, the vertical to horizontal aspect ratio of the patterned photoresist continues to increase. Generally, the higher the aspect ratio, the less mechanically stable the photoresist. For example, an aspect ratio above 4:1 may not be workable for many applications. As a specific example, a 0.15um minimum feature size would limit the photoresist thickness to less than 0.6um.
In addition, as the minimum feature size shrinks, a thicker photoresist narrows the process window and reduces process robustness due to the decrease in the depth of focus.
Therefore, thinner photoresists with sufficient etch selectivity are generally needed to enlarge the photolithographic process window, and to provide stable mechanical masks during the subsequent etching step.
One alternative to using a spin-on photoresist process is to use a CVD photoresist process. CVD photoresists generally avoid the problems associated with spin-on photoresists. For example, CVD photoresist may be formed in a thinner layer than a spin-on photoresist, thus providing mechanical stability and a larger process window. A CVD photoresist layer may have a typical thickness of 150 nm, with a thickness range of 30-500 nm, although other thicknesses may be used. In addition, CVD photoresist may provide superior etch mask properties, such as high selectivity to silicon oxide, aluminum and its compounds, tungsten and its compounds, polysilicon, and so on.
One example of CVD photoresist is plasma polymerized met ylsilane ("PPMS"). PPMS is a photosensitive material which is transformed into CH3-contained silicon oxide (PPMS oxide ("PPMSO")) after being exposed to ultraviolet ( "UV" ) light in air .
There are generally several problems, however, with using hydrocarbon (e.g., methyl) contained silicon oxides, as etch masks. For example, because these materials are effectively silicon oxide with CH3 bonds, they generally do not have sufficient etch selectivity with respect to other silicon oxides. Thus, the application of PPMSO or equivalent CVD photosensitive materials is generally limited to non-oxide patterning. As another example, photosensitive methyl-contained silicon oxides generally do not provide as high a quality silicon oxide as conventional plasma enhanced CVD ("PECVD") processes. For example, these materials are susceptible to moisture absorption. Therefore these materials by themselves generally cannot be left on the substrate to function as an oxide layer, and they generally have to be removed from the substrate after the subsequent etching process that uses their hard mask properties .
SUMMARY OF THE INVENTION
These problems are generally solved or circumvented, and technical advantages are generally achieved, by a preferred embodiment of the invention in which CVD photoresist (e.g., PPMS) is formed on a substrate, patterned and converted into silicon oxide (e.g., PPMSO), and is left on the substrate to function as a silicon oxide layer. A high quality cap layer (e.g., PECVD silicon oxide or nitride) may then be formed over the lower quality silicon oxide layer (e.g., PPMSO) utilizing a maskless etch process. Depending on the underlying layer material an additional high quality silicon oxide layer may also be formed on the substrate prior to formation of the CVD photoresist layer. The cap layer may be used to protect the lower quality silicon oxide layer from moisture absorption.
In accordance with a preferred embodiment of the present invention, a method of forming a patterned silicon oxide layer in an integrated circuit comprises forming a patterned hydrocarbon-contained silicon oxide layer on a first layer of a substrate; and forming a insulating cap layer encasing the patterned hydrocarbon-contained silicon oxide layer.
In accordance with a preferred embodiment of the present invention, a method of forming a patterned silicon oxide layer in an integrated circuit comprises depositing a chemical vapor deposition (CVD) photoresist layer on a first layer of a substrate; exposing first regions of the CVD photoresist layer to radiation, wherein the exposing converts the CVD photoresist in the first regions into hydrocarbon-contained silicon oxide; removing unexposed second regions of the CVD photoresist layer from the substrate, thereby exposing the first layer in the second regions; depositing a conformal insulating layer on the substrate, wherein the conformal layer is thicker on an upper horizontal surface of the hydrocarbon-contained silicon oxide than on other surfaces on the substrate; and removing the conformal layer from the second regions, thereby exposing the first layer in the second regions, and thereby forming an insulating cap layer encasing the hydrocarbon-contained silicon oxide .
In accordance with a preferred embodiment of the present invention, an integrated circuit comprises a patterned hydrocarbon-contained silicon oxide layer overlying a first layer of a substrate; and a cap layer encasing the patterned hydrocarbon-contained silicon oxide layer. The hydrocarbon- contained silicon oxide is preferably plasma polymerized methylsilane oxide, and the cap layer is preferably selected from the group consisting of silicon oxide, silicon nitride, and combinations thereof.
An advantage of a preferred embodiment of the present invention is that it provides a simplified oxide patterning technique. Overall process steps may be reduced from the number of steps in prior art techniques. In addition, raw process time in the oxide etching step may be reduced.
Another advantage of a preferred embodiment of the present invention is that a thinner photoresist may be used because the technique does not require etch resistance or selectivity. The thickness may generally be determined solely by the requirement of the thickness of the oxide layer being patterned.
Another advantage of a preferred embodiment of the present invention is that the thinner photoresist layer permits a larger lithographic process window and increased depth of focus, enabling a more robust process than that used in the prior art.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims .
BRIEF DESCRIPTION OF THE DRAWING
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
FIGURES 1-6 are cross-sectional views of a prior art integrated circuit structure at various stages of fabrication;
FIGURES 7-10 are cross-sectional views of an integrated circuit structure in accordance with a preferred embodiment of the present invention at various stages of fabrication;
FIGURES 11-15 are cross-sectional views of an integrated circuit structure in accordance with another preferred embodiment of the present invention at various stages of fabrication; and
FIGURES 16-19 are cross-sectional views of an integrated circuit structure in accordance with another preferred embodiment of the present invention at various stages of fabrication.
DETAILED DESCRIPTION
The making and use of the presently preferred embodiments are discussed below in detail. However, it should be appreciated that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. The figures are drawn so as to clearly illustrate the relevant aspects of the preferred embodiments, and are not necessarily drawn to scale.
The invention relates to integrated circuits, including memory ICs, microprocessor ICs, logic ICs, analog and mixed signal ICs, or other ICs comprising a patterned oxide layer. The invention also relates to semiconductor processes and structures, including insulating layers such as capacitor dielectrics, field oxides, or gate oxides, or other processes and structures comprising an oxide layer.
Figures 1-6 illustrate cross-sectional views of a well known conventional prior art method of patterning a silicon oxide layer. Referring to Figure 1, a silicon oxide layer 102 is formed on silicon substrate 100. Alternatively, the substrate may be gallium arsenide or another form of silicon such as silicon on insulator. Oxide layer 102 may be grown using a local oxidation of silicon process, or deposited using a PECVD silane based or tetraethyloxysilane ("TEOS") based process. Referring now to Figure 2, anti-reflective coating ("ARC") layer 104 is formed on silicon oxide layer 102. Spin-on photoresist layer 106 is then deposited on ARC layer 102 using a spin-on method.
Using photolithography, portions of spin-on photoresist layer 106 are exposed to radiation through a photolithographic mask, followed by development of photoresist layer 106 using an appropriate chemical etch. As shown in Figure 3, the exposed (positive resist) or unexposed (negative resist) portions of spin-on photoresist layer 106 are removed from the substrate, resulting in patterned photoresist layer 108.
Referring now to Figure 4, the exposed portions of ARC layer 104 are etched using patterned photoresist layer 106 as a mask to form patterned ARC layer 110. Exposed portions of silicon oxide layer 102 are then etched, again using patterned photoresist layer 106 as a mask. Because patterned photoresist layer 108 may have etch characteristics similar to that of silicon oxide layer 102, patterned photoresist layer 108 must generally be of sufficient thickness so that a portion of it remains after the etching of silicon oxide layer 102 is complete. The resulting structure is illustrated in Figure 5, with patterned silicon oxide layer 114 shown underlying patterned ARC layer 116 and etched photoresist layer 108.
To complete the prior art process, photoresist layer 108 and ARC layer 116 are stripped off the substrate, leaving patterned silicon oxide layer 114 formed on substrate 100, as illustrated in Figure 6. As discussed hereinabove, the thicker photoresist required for the silicon oxide etching step narrows the lithographic process window and reduces process robustness due to the decrease in the depth of focus along with the decrease in minimum feature size.
Referring now to Figures 7-10, cross-sectional views are illustrated of a preferred embodiment method of forming a patterned silicon oxide layer using CVD photoresist instead of spin-on photoresist. Figure 7 illustrates 150 nm thick CVD photoresist PPMS layer 202 deposited on silicon substrate 200 using a vacuum CVD system. Typical process parameters for the PPMS deposition process are a temperature of 150° C, a pressure of 8 Torr, and an RF power of 300 W. The temperature may vary between 0°-300° C, the pressure may vary between 1-20 Torr, and the RF power may vary between 100-1000 , although other parameter ranges may be used. The thickness of PPMS layer 202 may be 100-300 nm, although other thicknesses may be used. The resist may be formed using any carbon-containing or hydrocarbon- containing silane gas, such as mono-methylsilane, bi- methylsilane, 3-methylsilane or 4-methylsilane (all of which are referred to herein simply as methylsilane) . In addition, the substrate may be gallium arsenide or another form of silicon such as silicon on insulator.
Using photolithography, portions of PPMS layer 202 are exposed to ultraviolet light (e.g., 248 nm, 193 nm or 157 nm wavelengths) through a photolithographic mask in an air atmosphere. In this process, the exposed portions of PPMS layer 202 are converted into PPMSO, a CH3-contained silicon oxide. The unexposed portions of layer 202 are then removed from the substrate using an appropriate chemical etch, leaving patterned PPMSO layer 204, as shown in Figure 8. As discussed hereinabove, a PPMSO layer generally could not be used as a mask to pattern a silicon oxide layer because it does not possess sufficient etch selectivity.
Referring now to Figure 9, a conventional PECVD silane based or TEOS based deposition process is used to form 30 nm thick cap layer 206 overlying PPMSO layer 204. The thickness of cap layer 206 may be 10-100 nm, although other thicknesses may be used. Cap layer 206 is preferably silicon oxide, but alternatively another insulator such as a silicon nitride cap layer may be used. The capping process prevents moisture absorption into PPMSO layer 204.
As can be seen in Figure 9, cap layer 206 is about twice as thick in region 208 directly overlying PPMSO layer 204 as it is in region 210 directly overlying substrate 200. This is generally because the PECVD silane based oxide process produces about 40% bottom step coverage relative to top step coverage, and the TEOS based oxide process produces about 50% to 60% bottom step coverage, depending on the aspect ratio of the step structure .
Therefore, a maskless or self-aligned etch process may be used to punch through the portions of cap layer 206 covering the substrate in region 210, in order to clear the insulator from the contact area. Because cap layer 206 is much thinner in region 210 than in region 208, a conventional anisotropic silicon oxide etch process may be used to open the contact area without re-exposing PPMSO layer 204 underlying the thicker portions of cap layer 206. The resulting structure is illustrated in Figure 10, with cap layer 212 encasing PPMSO layer 204, and substrate 200 exposed in region 214.
Because the CVD photoresist is not used as a mask to etch an underlying silicon oxide layer, a thinner CVD photoresist layer may be used. The thickness of the CVD photoresist may be determined solely by the final desired thickness of the oxide layer being patterned.
Referring now to Figures 11-15, cross-sectional views are illustrated of another preferred embodiment method of forming a patterned silicon oxide layer using CVD photoresist. In some cases it may be desirable to initially deposit a high quality oxide liner on the substrate to provide a buffer between the substrate and the PPMSO layer, and to completely encircle the PPMSO layer with a high quality oxide. Therefore, in this embodiment, as shown in Figure 11, a 50 nm thick silicon oxide liner 302 is deposited on substrate 300 prior to the deposition of CVD photoresist PPMS layer 304. The thickness of oxide liner may be 10-100 nm, although other thicknesses may be used. Oxide liner 302 may be formed using any high quality oxide formation process, such as LOCOS, or those used to form the cap layer in the previous embodiment. Alternatively, another insulator such as silicon nitride may be used as the liner.
The method then generally proceeds as described in the previous embodiment. Using photolithography, portions of PPMS layer 304 are exposed to ultraviolet light through a photolithographic mask in an air atmosphere. In this process, the exposed portions of PPMS layer 304 are converted into PPMSO, a CH3-contained silicon oxide. The unexposed portions of layer 304 are then removed from the substrate using an appropriate chemical etch, leaving patterned PPMSO layer 306 overlying silicon oxide liner 302, as shown in Figure 12.
Referring now to Figure 13, an anisotropic etch process may be used to remove the exposed portions of oxide liner 302. This process will generally also etch the PPMSO layer 306 because of the similarity of the materials. Therefore PPMSO layer 306 should generally be of sufficient thickness to permit removal of the exposed oxide layer 302. The resulting structure comprises PPMSO layer 310 overlying patterned oxide liner 308.
Referring now to Figure 14, a conventional PECVD silane based or TEOS based deposition process is used to form cap layer 312 overlying PPMSO layer 310 and oxide liner 308. Cap layer 312 is preferably silicon oxide, but alternatively a silicon nitride cap layer may be used.
As with the previous embodiment, and as can be seen in Figure 14, cap layer 312 is about twice as thick in the region directly overlying PPMSO layer 310 as it is in the region directly overlying substrate 300. Therefore, a maskless or self-aligned etch process may be used to punch through the portions of cap layer 312 directly overlying the substrate, in order to clear the insulator from the contact area.
A conventional anisotropic silicon oxide etch process may be used to open the contact area without re-exposing PPMSO layer 310 underlying the thicker portions of cap layer 312. The resulting structure is illustrated in Figure 15, with cap layer 314 and oxide liner 308 encompassing PPMSO layer 310, and with substrate 300 exposed in the remaining regions. Cap layer 314 and oxide liner 308 together provide a high quality oxide completely surrounding PPMSO layer 310.
Referring now to Figures 16-19, cross-sectional views are illustrated of another preferred embodiment method of forming a patterned silicon oxide layer using CVD photoresist. In this embodiment, a high quality oxide liner is again deposited on the substrate, but it is etched at a different point in the process. In this embodiment, as shown in Figure 16, silicon oxide liner ,.402 is deposited on substrate 400 prior to the deposition of CVD photoresist PPMS layer 404. Oxide liner 402 may be formed using any high quality oxide formation process, such as LOCOS, or those used to form the cap layer in the previous embodiment . Alternatively, another insulator such as silicon nitride may be used as the liner.
The method then generally proceeds as described in the previous embodiments. Using photolithography, portions of PPMS layer 404 are exposed to ultraviolet light through a photolithographic mask in an air atmosphere. In this process, the exposed portions of PPMS layer 404 are converted into PPMSO, a CH3-contained silicon oxide. The unexposed portions of layer 404 are then removed from the substrate using an appropriate chemical etch, leaving patterned PPMSO layer 406 overlying silicon oxide liner 402, as shown in Figure 17.
Referring now to Figure 18, a conventional PECVD silane based or TEOS based deposition process is used to form cap layer 408 overlying PPMSO layer 406 and oxide liner 402. Cap layer 408 is preferably silicon oxide, but alternatively a silicon nitride cap layer may be used. Similar to the previous embodiments, and as can be seen in Figure 18, cap layer 408 is about twice as thick in the region directly overlying PPMSO layer 406 as it is in the region directly overlying oxide liner 402. Therefore, a maskless or self-aligned etch process may be used to punch through the portions of both cap layer 408 and oxide liner 402 directly overlying the substrate, in order to clear the insulators from the contact area.
A conventional anisotropic silicon oxide etch process may be used to open the contact area without re-exposing PPMSO layer 406 underlying the thicker portions of cap layer 408, as long as the thick top step of cap layer 408 is thick enough to withstand the etching of both the thin bottom step of cap layer 408 and oxide layer 402. The resulting structure is illustrated in Figure 19, with cap layer 410 and oxide liner 412 encompassing PPMSO layer 406, and with substrate 400 exposed in the remaining regions. Cap layer 410 and oxide liner 412 together provide a high quality.oxide completely surrounding PPMSO layer 406.
The remainder of an integrated circuit may be formed using conventional IC processing techniques. The resulting IC may then be employed in a variety of commercial and consumer electronics devices, including computers.
There are many alternative materials and processes which could be substituted for those disclosed in the above embodiments by one of ordinary skill in the art, and all such alternatives are considered to be within the scope of the present invention. For example, other layers may be interposed between the layers illustrated in the accompanying drawing, such as one or more layers disposed between the substrate and the insulating layer formed in accordance with the preferred embodiments. In addition, the order of process steps may be rearranged by one of ordinary skill in the art, yet still be within the scope of the present invention.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

WHAT IS CLAIMED IS:
1. A method of forming a patterned silicon oxide layer in an integrated circuit, said method comprising: forming a patterned hydrocarbon-contained silicon oxide layer on a first layer of a substrate; and forming a insulating cap layer encasing said patterned hydrocarbon-contained silicon oxide layer.
2. The method of claim 1, wherein said forming said patterned hydrocarbon-contained silicon oxide layer comprises: depositing a chemical vapor deposition (CVD) photoresist layer on a first layer of a substrate; exposing first regions of said CVD photoresist layer to radiation, wherein said exposing converts said CVD photoresist in said first regions into hydrocarbon-contained silicon oxide; and removing unexposed second regions of said CVD photoresist layer from said substrate, thereby exposing said first layer in said second regions .
3. The method of claim 2, wherein said forming said insulating cap layer comprises: depositing a conformal layer on said substrate, wherein said conformal layer is thicker on an upper horizontal surface of said patterned hydrocarbon-contained silicon oxide than on other surfaces on said substrate; and removing said conformal layer from said second regions, thereby exposing said first layer in said second regions, and thereby forming said cap layer encasing said patterned hydrocarbon-contained silicon oxide.
4. The method of claim 3 , wherein said removing said conformal layer from said second regions further comprises using an anisotropic etch process .
5. The method of claim 2, wherein said CVD photoresist is plasma polymerized methylsilane, and wherein said hydrocarbon- contained silicon oxide is plasma polymerized methylsilane oxide .
6. The method of claim 1, wherein said forming said insulating cap layer comprises: depositing a conformal layer on said substrate, wherein said conformal layer is thicker on an upper horizontal surface of said patterned hydrocarbon-contained silicon oxide than on other surfaces on said substrate; and removing said conformal layer from regions of said substrate where said conformal layer is not in contact with said patterned hydrocarbon-contained silicon oxide layer, thereby exposing said first layer in said regions, and thereby forming said cap layer encasing said patterned hydrocarbon-contained silicon oxide.
7. The method of claim 1, wherein said hydrocarbon- contained silicon oxide is methyl-contained silicon oxide.
8. The method of claim 1, wherein said first layer is said substrate.
9. The method of claim 1, wherein said cap layer is selected from the group consisting of: silicon oxide, silicon nitride, and combinations thereof.
10. The method of claim 9, wherein said forming said insulating cap layer further comprises using a plasma enhanced CVD (PECVD) silane based or tetraethyloxysilane (TEOS) based deposition process.
11. The method of claim 1, further comprising: forming a buffer layer on said first layer prior to said forming said patterned hydrocarbon-contained silicon oxide layer.
12. The method of claim 11, further comprising removing said buffer layer from regions not underlying said hydrocarbon- contained silicon oxide layer.
13. The method of claim 11, wherein said buffer layer is silicon oxide formed by a process selected from the group consisting of: PECVD silane based, TEOS based, LOCOS, and combinations thereof.
14. An integrated circuit (IC) comprising: a patterned hydrocarbon-contained silicon oxide layer overlying a first layer of a substrate; and a cap layer encasing said patterned hydrocarbon-contained silicon oxide layer.
15. The integrated circuit of claim 14, wherein said hydrocarbon-contained silicon oxide is plasma polymerized methylsilane oxide.
16. The integrated circuit of claim 14, wherein said first layer is said substrate.
17. The integrated circuit of claim 14, wherein said cap layer is selected from the group consisting of: silicon oxide, silicon nitride, and combinations thereof.
18. The integrated circuit of claim 14, further comprising a buffer layer disposed between said first layer and said patterned hydrocarbon-contained silicon oxide layer.
19. The integrated circuit of claim 18, wherein said buffer layer is silicon oxide.
20. A method of forming a patterned silicon oxide layer in an integrated circuit, the method comprising: depositing a chemical vapor deposition (CVD) photoresist layer on a first layer of a substrate; exposing first regions of said CVD photoresist layer to radiation, wherein said exposing converts said CVD photoresist in said first regions into hydrocarbon-contained silicon oxide; removing unexposed second regions of said CVD photoresist layer from said substrate, thereby exposing said first layer in said second regions; depositing a conformal insulating layer on said substrate, wherein said conformal layer is thicker on an upper horizontal surface of said hydrocarbon-contained silicon oxide than on other surfaces on said substrate; and removing said conformal layer from said second regions, thereby exposing said first layer in said second regions, and thereby forming an insulating cap layer encasing said hydrocarbon-contained silicon oxide.
EP01964510A 2000-09-27 2001-08-30 Silicon oxide patterning using cvd photoresist Withdrawn EP1320877A2 (en)

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US6001747A (en) * 1998-07-22 1999-12-14 Vlsi Technology, Inc. Process to improve adhesion of cap layers in integrated circuits
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