EP1303956A2 - Appareil et procede de transmission de donnees - Google Patents

Appareil et procede de transmission de donnees

Info

Publication number
EP1303956A2
EP1303956A2 EP01963744A EP01963744A EP1303956A2 EP 1303956 A2 EP1303956 A2 EP 1303956A2 EP 01963744 A EP01963744 A EP 01963744A EP 01963744 A EP01963744 A EP 01963744A EP 1303956 A2 EP1303956 A2 EP 1303956A2
Authority
EP
European Patent Office
Prior art keywords
transmitting
current
data
line
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01963744A
Other languages
German (de)
English (en)
Inventor
James Norman Andersen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lynk Labs Inc
Original Assignee
Lynk Labs Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lynk Labs Inc filed Critical Lynk Labs Inc
Publication of EP1303956A2 publication Critical patent/EP1303956A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H04L25/0282—Provision for current-mode coupling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end
    • H04L25/0294—Provision for current-mode coupling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices

Definitions

  • the present invention generally relates to a method and device for transmitting data over a transmission medium at high speeds. More specifically, the present invention relates to using variations in electrical current for representing and conveying data over a transmission medium or a wireless connection.
  • Background of the Invention There are many modems on the market today for high speed data bit transmission on a twisted-pair of copper telephone lines. Constant demand for increased amounts of data bit transmission has generated the continual need for faster modems capable of transmitting and receiving greater amounts of data.
  • the amount of data that can be transmitted is directly related to the number of quantization levels that a transmitter utilizes. Random distortion noise directly affects the amount of quantization levels. Attempting to increase a transmission rate by merely increasing the amount of quantization levels beyond that in which the data bits can be determined is not useful. To date, the limitations on quantization caused by random distortion noise has prevented conventional modems and transmission techniques from meeting the demand for higher data transmission speed.
  • This invention relates to data communication equipment (DCE), more specifically, a modem or wireless device capable of high speed transmission of electronic data between data terminal equipment (DTE).
  • DCE data communication equipment
  • this invention sets forth a method and a device for transmitting data as a series of current pulses onto a transmission medium such as a communication line or a wireless transmission medium. The method requires converting an input signal waveform to a current signal waveform and transmitting the resulting current pulses onto a communication line or an antenna wherein a predetermined bias voltage is maintained.
  • Transmitting data as current pulses is an improved method of transmitting data, as opposed to using voltage pulses, because current is not affected as much by capacitance.
  • this allows the transmission of data over greater distances because the signal is less attenuated by line capacitance.
  • voltage data pulses weaken. Therefore, bridge taps associated with the current phone line infrastructure will not degrade the signals transmitted according to the invention to the same degree as they degrade (divide) conventional voltage signal waveforms.
  • loading coils exist in the infrastructure, are resistant to voltage changes, hence, the loading coils present a significant impediment to voltage waveform signals.
  • Another embodiment of this invention includes a method of generating representative pulses of current from an input (either current or voltage) waveform and transmitting resulting current pulses onto a communication line. Another aspect of the invention includes receiving the current pulses, measuring the current pulses, and translating the measured current pulses into data.
  • a circuit for carrying out the method as it relates to transmitting standard voltage-based data includes a converter for receiving voltage waveform input and generating a series of current pulses in response to the input voltage signal.
  • a transmitter responsive to output of the converter is provided for transmitting the output onto a communication line terminated by a receiver.
  • Another embodiment of the invention provides an automatic system for adjusting series and shunt impedance of a transmitting system relative to changes in data and transmission medium by a circuit for measuring and correcting changes in series and shunt impedance of the line using references internal to the transmitter (voltage, current, impedance, and current range) .
  • a gain amplifier is used to control changes in impedance and signal current.
  • Output voltage is kept at a reference level while output current is varied thereby controlling the impedance of the transmitter.
  • the transmitter has a current source for supplying reference currents and a voltage source for supplying reference voltages and a gain controlling circuit for controlling a current signal within a range of values according to binary input data.
  • a common problem of other known modems is the deterioration of the transmission signal due to distortion effects over the transmission line. In effect, the transmission signal is not able to be identified because of the accompanying noise distortion.
  • This invention is able to transmit significantly greater amounts of data than previous methods because it discriminates transmitted data from random distortion noise existing on the communication line.
  • a primary advantage of this invention is the provision of significantly increased amounts of data by being able to transmit and receive a low voltage signal amidst the accompanying random distortion noise and interference that was generally thought to be indeterminable.
  • a further advantage of this invention is the provision of significantly increased lengths of transmission than currently thought capable without the use of repeaters or amplifiers.
  • Another aspect of this invention is to transmit data at a low voltage and to further maintain this low voltage by monitoring and adj usting the current associated with the data signal.
  • the transmitter step of monitoring and adjusting the current includes the step of transmitting at least one reference/calibration pulse over the communication line and measuring the effects of line impedance on the current pulse.
  • FIGURE 1 is a schematic diagram, in block diagram form, of a preferred embodiment of a device incorporating an automatic impedance tuner in accordance with the present invention coupled to a receiver via a communication line;
  • FIGURE 2 is a partial simplified schematic diagram of the embodiment depicted in FIGURE 1 including a converter, filter/regulator, amplifier and transmitter;
  • FIGURE 3 is a graphical depiction of the modulated output of the converter of FIGURE 2 after being partially modified by the filter/regulator;
  • FIGURE 4 is a partial schematic of an alternative embodiment of the transmitter of FIGURE 2
  • FIGURE 5 is a simplified block diagram of a system in accordance with the present invention including a data transmitter device, a transmission medium and a receiver;
  • FIGURE 6 is a schematic diagram of an embodiment of the transmission medium shown in FIGURE 5;
  • FIGURE 7 is a schematic diagram of an alternative embodiment of the transmission medium shown in FIGURE 5;
  • FIGURE 8 is an expanded block diagram of the data transmitter device of FIGURE 5 including a data generator connected to a transmitter;
  • FIGURE 9 is an expanded block diagram of the data generator shown in
  • FIGURE 8 comprising a bit generator and a modulator
  • FIGURE 10 is a schematic diagram of an embodiment of a bit generator shown in FIGURE 9;
  • FIGURE 11 is a schematic diagram of an alternative embodiment of a bit generator shown in FIGURE 9;
  • FIGURE 12 is a schematic diagram of the modulator shown in FIGURE 9;
  • FIGURE 13 is a schematic diagram of the transmitter shown in FIGURE 8.
  • FIGURE 14 is a schematic diagram of a receiver shown in FIGURE 5, the receiver comprising an input network, output network, amplifier ICl , amplifier IC2, and amplifier IC3;
  • FIGURE 15 is an expanded schematic diagram of the input network shown in FIGURE 14;
  • FIGURE 16 is an expanded schematic diagram of the output network shown in FIGURE 14;
  • FIGURE 17 is an expanded schematic diagram of amplifier ICl shown in
  • FIGURE 18 is an expanded schematic diagram of amplifier IC2 shown in FIGURE 14;
  • FIGURE 19 is an expanded schematic diagram of amplifier IC3 shown in FIGURE 14;
  • FIGURE 20 is a simplified diagram of a system in accordance with the present invention for transmitting and receiving data via a transmission medium;
  • FIGURE 21 is a waveform diagram depicting a preferred embodiment of a pair of signals transmitted across the tip and ring signal paths of FIGURE 20, each signal includes a carrier signal having a plurality of bit signals modulated thereon;
  • FIGURE 22 is a waveform diagram depicting a preferred embodiment of the carrier signal depicted in FIGURE 21;
  • FIGURE 23 is a simplified block diagram of another system in accordance with the present invention for transmitting and receiving data via a transmission medium;
  • FIGURE 24 is a simplified expanded block diagram of the system depicted in FIGURE 23, the system including both digital and analog circuit portions;
  • FIGURE 25 is a simplified expanded block diagram of the digital circuit portion shown in FIGURE 24;
  • FIGURE 26 is a circuit diagram of the data interface block shown in FIGURE 25;
  • FIGURE 27 is a circuit diagram of the address map control block shown in
  • FIGURE 25
  • FIGURE 28 is a circuit diagram of the memory block shown in FIGURE 25;
  • FIGURE 29 is a circuit diagram of the address map select block shown in FIGURE 25;
  • FIGURE 30 is a circuit diagram of the control block shown in FIGURE 25;
  • FIGURE 31 is a simplified expanded block diagram of the analog circuit portion shown in FIGURE 24;
  • FIGURE 32 is a circuit diagram of the modulator shown in FIGURE 31 ;
  • FIGURE 33 is a circuit diagram of the transmitter shown in FIGURE 31 ;
  • FIGURE 34 is a circuit diagram of the receiving input network shown in FIGURE 31;
  • FIGURE 35 is a circuit diagram of the analog circuit connected between the receiving input network and the receiving output network shown in FIGURE 31 ;
  • FIGURE 36 is a circuit diagram of the other analog circuit connected between the receiving input network and the receiving output network shown in FIGURE
  • FIGURE 37 is a circuit diagram of the receiving output network shown in
  • FIGURE 31
  • FIGURE 38 is a circuit diagram of the analog circuit connected to the receiving output network shown in FIGURE 31;
  • FIGURE 39 is a circuit diagram of the transmit/receive gate connected to the transmitter shown in FIGURE 31 ;
  • FIGURE 40 is a circuit diagram of the other transmit/receive gate connected to tip and ring signal transmission leads;
  • FIGURE 41 is a block diagram of an error correction system suitable for use with the present invention
  • FIGURE 42 is a block diagram of another embodiment of an error correction system suitable for use with the present invention
  • FIGURE 43 is a block diagram with tip and ring independently processed through a system and wherein a virtual ground provides for current differential measurements;
  • FIGURE 44 is a schematic diagram depicting a virtual direct connect system that establishes a series impedance mismatch to create a counterweight effect that is used for balancing;
  • FIGURE 45 is a graph of the counterweight effect and how the bits are effectively drawn towards the higher impedance at the receiver;
  • FIGURE 46 is a schematic diagram depicting the total series impedance of 2.4K prior to any changes occurring on the medium;
  • FIGURE 47 is a schematic diagram depicting how an embodiment of the present invention reacts to changes in the medium;
  • FIGURE 48 is a graph of an embodiment of a waveform transmitted over the medium
  • FIGURE 49 is a graph wherein impulses of current are encoded onto the wave of FIGURE 48;
  • FIGURE 50 is a graph depicting in an embodiment how the bits and entire waveform are sent in duplicate
  • FIGURE 51 is an embodiment of a line encoding scheme in accordance with the present invention
  • FIGURE 52 is a diagram comparing a data channel driven by a current source and a voltage source
  • FIGURE 53 are graphs comparing energy by driving data with a current source verses a voltage source
  • FIGURE 54 is a diagram depicting the output of a differential circuit for eliminating interference
  • FIGURE 55 is a chart depicting a one- insertion (X) on the RING;
  • FIGURE 56 is a preferred embodiment of a cell data transport frame
  • FIGURE 57 is a preferred embodiment of a bulk data transport frame
  • FIGURE 58 is a preferred embodiment of OAM management messages
  • FIGURE 59 is a preferred embodiment of an OAM startup message
  • FIGURE 60 is a preferred embodiment of an OAM termination message
  • FIGURE 61 is a diagram illustrating frame termination to TRUE silence
  • FIGURE 62 is a diagram illustrating signals between frames
  • FIGURE 63 and 64 are a preferred embodiment for performing slope detection
  • FIGURE 65 is a preferred embodiment of the counters to be kept for interrogation by network managing elements
  • FIGURE 66 is a simplified diagram of an antenna of a system in accordance with the present invention for transmitting and receiving data via a wireless connection;
  • FIGURE 67 is a simplified block diagram of a wireless transceiver in accordance with the present invention
  • FIGURE 68 is a simplified block diagram of the system shown in FIGURE
  • FIGURE 69 is a simplified block diagram of an analog circuit
  • FIGURE 70 is a circuit diagram of the modulator shown in FIGURE 68;
  • FIGURE 71 is a circuit diagram of the transmitter shown in FIGURE 68;
  • FIGURE 72 is a circuit diagram of the receiving input network shown in
  • FIGURE 68
  • FIGURE 73 is a circuit diagram of the analog circuit connected between the receiving input network and the receiving output network shown in FIGURE 68;
  • FIGURE 74 is a circuit diagram of the other analog circuit connected between the receiving input network and the receiving output network shown in FIGURE
  • FIGURE 75 is a circuit diagram of the receiving output network shown in FIGURE 68;
  • FIGURE 76 is a circuit diagram of the analog circuit connected to the receiving output network shown in FIGURE 68;
  • FIGURE 77 is a circuit diagram of the transmit/receive gate connected to the transmitter shown in FIGURE 68;
  • FIGURE 78 is a circuit diagram of the other transmit/receive gate comiected to the antenna of FIGURE 68;
  • FIGURE 79 is a block diagram of a system for controlling the system depicted in FIGURE 68; and FIGURES 80-84 are circuit level diagrams for implementing the system depicted in FIGURE 79.
  • an automatic impedance tuner 5 is depicted having a converter/filter 10, filter/regulator 12, amplifier 14, and transmitter 16.
  • the converter/filter 10 receives a digital voltage pulse signal 8 representing data.
  • the input signal 8 is transformed by the converter 10 into a phase modulated current output 40 that is received by the filter/regulator 12.
  • the filter/regulator 12 measures current change, limits the voltage range of the phase modulated current output 40, and dampens ringing on the signal. In addition, the filter/regulator 12 differentiates the phase modulated current output 40, adjusts for current gain and narrows the current pulses of the phase modulated current output 40. Before being received by the amplifier 14, the differentiated signal output 55 generated by the filter/regulator 12 is widened and returned to a timing similar to input data signal 8.
  • the transmitter 16 adjusts the amplified current signal 57 generated by the amplifier 14 in response to filter/regulator 12. Accordingly, the transmitter 16 provides a desired voltage and current for transmission to a receiver 20 via communication line 18. Receiver 20 deciphers the transmission by detecting variations in the current received from the transmitter 16.
  • FIGURE 2 a further defined schematic diagram of a preferred embodiment of an automatic impedance tuner 5 in accordance with the present invention is provided.
  • the tuner 5 includes the converter/filter 10, filter/regulator 12, amplifier 14, and transmitter 16 of Figure 1. Accordingly, the same reference numbers are used, where appropriate, within both FIGURES 1 and 2.
  • the converter/filter 10 includes a common emitter transistor 24, a filter capacitor 22, two coupling feedback capacitors 34, 38, and two current limiting resistors
  • the input voltage pulse signal 8 received by the converter/filter 10 is filtered by capacitor 22 connected to the base of the first common-emitter transistor 24.
  • the transistor operates as a cutoff circuit for keeping a sharp rise and fall time of the converter output 40, and thus the output of the tuner 5.
  • the first common-emitter transistor 24 provides a constant current reference through serially connected resistor 28 and adjustable resistor 26 wherein resistor 26 is coupled to a regulated power source 32 of about 8 volts and resistor 28 is attached to the collector 30 of the transistor.
  • the voltage potential at the collector 30 of the first common-emitter transistor 24 is approximately one-half the value of the voltage potential of the power source 32 with respect to ground, i.e., 4 volts.
  • the collector 30 of the first common-emitter transistor 24 is fedback to its base through the two capacitors 34, 38 which are coupled together in series and operably connected at the junction of the capacitors to the output of the tuner 5.
  • This internal feedback controls the automatic impedance tuner' s 5 current output relative to the load on the communication line 18 and the power source 32.
  • the coupling feedback capacitors 34 and 38 preferably are in a 2.2 to 1 ratio to modulate the input voltage signal 8 into a converted constant current signal received by the filter/regulator 12.
  • the magnitude of each current pulse provided by the output 40 of the converter/filter 10 quickly rises to a peak, then falls to a plateau that is maintained for a time duration before the current magnitudes falling off rapidly.
  • the filter/regulator 12 comprising an AC and DC load that includes the load of the communication line 18.
  • the filter/regulator 12 consists of a measuring resistor 36, a pair of clamping diodes, 44, 46, a filter capacitor 54 and a differentiator.
  • the measuring resistor 36 is coupled between a pair of clamping diodes 44, 46, preferably geranium.
  • the resistor 36 is connected to the cathode of diode 44 and the anode of diode 46.
  • the anode of diode 44 and the cathode of diode 46 are attached to ground.
  • diodes 44,46 are used to reduce noise on the converted output signal 40 by dampening voltage ringing and oscillations.
  • the diodes 44, 46 clamp the converted data signal to a voltage level between 0.2 and - 0.2 volts, or 0.4 volts peak-to-peak as shown in Figure 3.
  • a reference voltage range NR1 is maintained at the junction between the diodes 44 and 46.
  • the maj ority of the load provided by the filter/regulator 12 is AC .
  • Part of the DC load of the filter/regulator 12 is fixed by the measuring resistor 36 and the pair of diodes 44, 46. This fixed DC load is used as a reference load.
  • the data signal 40 also is differentiated within the filter/regulator 12 wherein the pulses of the received signal are narrowed.
  • the differentiator is preferably comprised of a capacitor 48 in series with an adjustable resistor 50 for adjusting the output AC current level of the automatic impedance tuner 5 relative to the power source 32.
  • the pulses of the data signal are widened and returned to a timing similar to the original signal 8 by filter capacitor 54.
  • resistor 50 provides for adjusting current gain.
  • the differentiated current signal 55 from the filter capacitor 54 of the filter/regulator 12 is received by the amplifier 14 which includes a second common-emitter transistor 52 for amplifying the differentiated current signal and a voltage limiting pull-up resistor 56 for limiting the voltage at the collector of the second common-emitter transistor 52.
  • the collector has a voltage of about 6 volts (i.e., close to the threshold turnoff) and is coupled to the transmitter 16.
  • the switching of shunt transistor 52 is effected by changes in the voltage at the tip transmitter 18 for maintaining a substantially constant voltage level at the tip transmitter.
  • the transmitter 16 includes a coupling capacitor 54, a pair of clamping diodes 58, 60 and a resistor-capacitor 62, 64 combination.
  • the coupling capacitor 54 at the input of the transmitter 16 is attached to the output of the amplifier 14.
  • the coupling capacitor 54 widens the pulses of the amplified current signal 57.
  • Coupled between the filter capacitor 54 and the adjustable resistor 62 are two clamping diodes, 58, 60, preferably of type silicon, for maintaining the amplified current signal 57 within a voltage range NR2 between 0.7 and - 0.7 volts, 1.4 volts peak-to-peak.
  • the adjustable resistor 62 controls the voltage level and the AC current through a capacitor 64 while the two clamping diodes 58, 60 control the DC offset relative to ground.
  • the adjustable resistor 62 and capacitor 64 adjust the voltage level on the communication line to approximately 1 volt, peak-to-peak.
  • a diode-capacitor combination Prior to reaching the communication line, a diode-capacitor combination filters the AC portion of the signal from negative going noise spikes and a diode-resistor combination filters the DC portion of the signal from positive going noise spikes.
  • the collector of the second common-emitter transistor 52 within the transmitter 14 is attached to two capacitors 54, 64 in series and then to a line-side select switch 80.
  • the system 110 includes a data transmitter device 112, a data transmission medium 114, and a data receiver 116.
  • the data receiver 116 receives data signals transmitted from the transmitter 112 across the transmission medium 114.
  • the transmission medium 114 is modeled to provide conventional characteristics found in telephone transmission cables or the like that do not include a significant amount of inductance.
  • the transmission medium receives input signal pair 132 and 172 and provides corresponding output signal pair 188 and 190.
  • the transmission medium 114 can be modeled to provide characteristics found in transmission mediums having, for example, about 15mH of inductance as found in many conventional preexisting transmission mediums.
  • the data transmitter 112 preferably includes a data generator 118 and a transmitter 120 operably coupled together.
  • the data generator 118 includes a bit generator 122 and a modulator 124.
  • the bit generator 122 provides a data signal 126 represented as a series of voltage pules preferably in the range of about 0 to 5 volts.
  • the bit generator 122 can consist of a counting circuit responsive to a digital reference clock signal 128 wherein a series of digital data signals 126 are provided corresponding to binary numeric values and increasing in binary numeric magnitude at a constant incremental rate.
  • the bit generator 122 can consist of a counting circuit responsive to a digital reference clock signal 128 for providing digital data signals 126 corresponding to numeric values and decreasing in binary numerical magnitude at a constant incremental rate.
  • the digital data signals 126 from the bit generator 122 along with digital reference clock signal 128 are received by the modulator 124.
  • the modulator 124 In response to these signals, the modulator 124 generates a modulated digital data signal 130 comprising the digital data signals 126 added to the clock signal 128.
  • the modulated digital signals 130 are received by the transmitter 124 for conversion and transmission across the transmission medium 114 to the receiver 116.
  • the transmitter 124 is similar to that shown in FIGURE 2 and described above.
  • the transmitter 124 receives the digital signals 130 and converts them into current pulses while maintaining a substantially constant voltage level on the output 132.
  • the voltage level is about 1 volt.
  • the digital signals 130 are fed to the capacitor 134 attached to the base of transistor 136.
  • This transistor 136 is a constant current reference through resistor 138 and adjustable resistor 139 to Ncc, preferably about +8N.
  • the transistor 136 has feedback from it's collector to it's base through two capacitors 140 and 142 in series. This controls the transmitter current relative to the load and Vcc.
  • At the junctions of capacitors 140 and 142 is an AC and DC load including the line, which the majority of the load being AC. Part of the DC load at this junction is fixed by a resistor 144 and diodes 146 and 148. The fixed DC load is used as a reference load.
  • the diodes 146 and 148 clamp the peaks to .7N positive and negative going resulting in a 1.4N peak to peak output.
  • the junction of 144, 146 and 148 goes to a capacitor 150 and then to an adjustable resistor 152.
  • This adjustable resistor 152 adjusts the output AC current level of the transmitter 124 relative to Ncc then goes to a capacitor 154 and then to the base of atransistor 156.
  • the transistor's collector goes to capacitor 158 coupled to diodes 160 and 162 for clamping the peaks to .7v positive and negative going resulting in a 1.4N peak to peak output 164.
  • Also attached to the output 164 is an adjustable resistor 166 for controlling the voltage level and the AC current through a capacitor 168.
  • the collector of transistor 154 also is coupled to a resistor 170 attached to Ncc for limiting the voltage that the transistor will reach when fully turned on. Furthermore, serial connected diode 172 and resistor 174 are coupled between ground and output 132 for filtering the DC portion of positive going noise spikes.
  • the receiver 116 includes an input network 178, an output network 180, and a plurality of integrated IF amplifiers 182, 184, and 186.
  • TIP and the RING signals 132 and 136 are transmitted across the transmission medium 144 and the input network 178 receives corresponding
  • TIP and RING signals 188 and 190 respectively.
  • the input network 178 filters out noise to provide filtered data output signal groups 192 and 194.
  • the filtered signal groups 192 and 194 are received by IF amplifiers 182 and 184, respectively, for amplifying the signals and passing them to the output network 180 where the signals are mixed together and amplified by amplifier 186 to produce a noise reduced digital data output signal 196 corresponding to the digital data input 126 from the data generator 122.
  • Twisted-pair phone lines are disclosed as a preferred embodiment only due to their prevalence in the global telecommunication infrastructure. It is contemplated that advantages may be had employing the basic concepts of the invention in transmission of data over shielded coaxial cable lines, category 5 lines, twisted-pair copper lines, etc. It is even contemplated that the present invention may be advantageously employed with wireless communication mediums such as broadcast in air, since signal attenuation, concerns also apply to this transmission medium.
  • Transmission medium relates to a communication line or an electromagnetic signal path from a first device to a second device being physically and spatially remote from the first.
  • Communication line as used herein relates only to one or more conductors and the like used for transmitting data from a first device to a second device being physically and spatially remote from the first.
  • Remote means, that neither the first nor the second device share the same chassis, housing, or support structure. In its most concrete and conventional form, remote would contemplate one modem communicating with another over conventional telecommunication lines, although it is not intended to be so limited.
  • the present invention addresses data transmission problems presently faced by telecommunications industry, Internet, and local area networks in communication between remote devices.
  • FIGURE 20 a simplified diagram of another embodiment of a system in accordance with the present invention is depicted.
  • the system includes a data transmitter device, a data receiver device, and a transmission medium connected therebetween.
  • the transmission medium can comprise a conventional telephone transmission cable having tip and ring transmission paths.
  • the transmission medium can comprise a single transmission path or communication line.
  • the transmitter provides a reference voltage potential of about 1.48 volts operably connected to a termination resistor of about 150 ohms.
  • the termination resistor is attached to a variable control impedance that is operably connected to the tip transmission path having a line impedance of about 750 ohms.
  • the receiver provides a reference voltage potential of about 1.25 volts operably connected to a variable impedance coupled to the tip transmission path.
  • the total serial impedance provided by the transmitter, tip transmission path, and the receiver is substantially constant and is maintained by automatic control of the receiver and transmitter variable control impedances.
  • signals corresponding to data are generated on the tip transmission path by the transmitter varying the impedance value of the transmitter's variable impedance in response to voltage control signals, such as data signals, received by the transmitter.
  • the changes in the impedance value result in corresponding changes in the magnitude of the current flowing from the transmitter, to the receiver, via the tip transmission path.
  • These current magnitude changes are detected by the receiver and converted into voltage signals corresponding to the data received.
  • changes in the current magnitude are detected by the receiver between the tip transmission path and the receiver's variable control impedance.
  • phase shifted error checking data or additional data can also be transmitted on the ring transmission path.
  • the transmitter provides a reference voltage potential of about .48 volts operably connected to a termination resistor of about 150 ohms.
  • the termination resistor is connected to a variable control impedance that is attached to the ring transmission path having a line impedance of about
  • the receiver provides a reference voltage potential of about .25 volts operably coupled to a variable impedance attached to the ring transmission path.
  • a reference voltage potential of about .25 volts
  • the total serial impedance provided by the transmitter, ring transmission path, and the receiver is substantially constant and is maintained by automatic control of the receiver and transmitter variable control impedances.
  • signals corresponding to voltage data signals received by the transmitter are generated on the ring transmission path by varying the impedance of the transmitter ' s variable impedance.
  • the changes in the impedance result in corresponding changes in the magnitude of the current flowing, via the ring transmission path, from the transmitter to the receiver.
  • These current magnitude changes are detected by the receiver and converted back into voltage data signals.
  • changes in the current magnitude are detected by the receiver between the ring transmission path and the receiver's variable control impedance.
  • a virtual direct connect system is provided for very low power optimum bandwidth utilization of a communication medium due to increasing demand for bandwidth.
  • the virtual direct connect system (“the system") is a signal transmission, reception, and processing technology that is the core technology within virtual direct connect transceivers.
  • the virtual direct connect system architecture is a transceiver technology which, when connected transceiver to transceiver by a communication medium, communicates in serial from Signal Transmit (Tip) to Signal Receive and Return Transmit (Ring) to Return Receive rather than using the conventional parallel prior art.
  • the system transmits impulses of AC current by varying impedances.
  • the transceivers are virtually connected directly together as long as the units are not factory set for very different medium impedance characteristics.
  • the transceivers are factor set according to basic medium characteristics.
  • the phrase factory set means the systems are preset at the manufacturer for a particular range of variation in the longitudinal impedance or resistance of a given communication medium. For example, for the majority of 24 or 26 gauge telephone lines, the transceiver is preset at the factory to operate within a range of
  • the virtual direct connect system's analog circuitry allows the electrical variations of the medium to change the system characteristics greater than the characteristics of the data transmission allowing for greater and more accurate throughput simultaneous to real time processing.
  • the virtual direct connect system provides constant compensation during the presence of data and/or electrical variations and distortions on the medium.
  • One component in achieving this is the automatic precision impedance measuring circuitry or "APIM" designed into each transceiver.
  • the automatic precision impedance measuring circuitry or "APIM" designed into each transceiver.
  • APIM is similar to a real time impedance reactive bridge.
  • a phone line is a bridge. Therefore, the virtual direct connect transciever has an intelligent bridge front end on each side of the line which individually responds in real time to electrical variations and imbalances of the transmission medium.
  • systems transmit voltage which is measured and/or processed in parallel across the signal and return (Tip & Ring) sides of the line to determine data.
  • the virtual direct connect system is a serial transmission system which transmits impulses of AC current and uses virtual grounds rather than a return line. This provides for parallel processing.
  • the transceivers transmit two individual signals, one on the signal side and one on the return side of the transmission medium and parallel processes the ratios of the signals.
  • the virtual direct connect system is a serial transmission parallel ratio processing communication system.
  • the virtual direct connect system transmits AC current by keeping a constant voltage drop over the line (i.e., signal transmit to signal receive and return transmit to return receive).
  • Conventional systems may be transmitting voltages along the line as a current, but they receive a voltage metallically across the line (i.e., tip to ring). Voltage wise, if two separate signals are transmitted (i.e., one signal on tip and one signal on ring), one signal will add or subtract to or from the other signal. Aside from performing high speed (real time analog) impedance variations according to the characteristics and electrical variations of the transmission medium, in an embodiment, virtual direct connect is doing these high speed impedance variations to generate impulses of AC current according to the bit stream. It is recognized that there are only two choices, one can vary voltage, or one can vary impedance.
  • impedance must be kept constant which is difficult to do because of characteristics and electrical variations in the line such as the frequencies being transmitted, ground bounce, and noise from voltage variations. All of which make it difficult to maintain a constant voltage.
  • Such as virtual direct connect if impedances are varied and a contant voltage drop is kept (tip to tip and/or ring to ring) then it is easier to transmit, maintain, and control impulses of current.
  • H y (x) is roughly the amount of additional information that must be supplied per second at the receiving point to correct the received message. For instance, in long sequences of received message M' and corresponding original message M, there will be logarithmically TH y (x) of the M's which could reasonably have produced each M'. Thus, there are TH y (x) binary digits to send each T seconds. This can be done with ⁇ frequency of errors on a channel of capacity H y (x).
  • x is identified as the output of the source, y as the received signal, and z as the signal sent over the correction channel, then the right-hand side is the equivocation less the rate of transmission over the correction channel. If the capacity of this channel is less than the equivocation the right-hand side will be greater than zero and H yz (x) > 0. But this is the uncertainty of what was sent, knowing both the received signal and the correction signal. If this is greater than zero the frequency of errors cannot be arbitrary small.
  • the rate of transmission R can be written in two other forms due to the identities noted above.
  • identities noted above.
  • the virtual direct connect system provides for maximum exploitation of communication infrastructures such as, for example, those utilizing copper or other metallic transmission leads.
  • copper communication mediums are built based on the universal electronic principle of signal and return (or tip and ring). Together, signal and return has provided for the ability to transport analog and digital information by measuring and/or determining a voltage differential between the two. This is referred to as the metallic or parallel voltage differential in which it is common to match impedance between signal and return. This metric suffers many limitations, not the least of which is severe attenuation of this voltage differential over long transmission lines.
  • the virtual direct connect system decodes data by determining a current differential between two independent measurement resultants as opposed to using a conventional method of measuring a voltage differential between the tip and ring sides of a line. Determining a current differential can be achieved in various ways depending on the virtual direct connect technology application. One technique isolates the tip and ring sides of the signal line from each other, creating a virtual break in the loop. Another technique provides an independent virtual ground to each (tip and ring) side of the line. In any case, the system has no direct return as shown in FIGURE
  • a virtual direct connect transmitter transmits bits represented as current pulses.
  • the waveform and bits are preferably shaped and controlled in various ways for optimum throughput as described below.
  • varying impedance and maintaining a constant voltage of about 1 volt generates the bits (impulses of current).
  • the system preferably operates on independent conductor series current differentials from transmitter to receiver (tip transmit to tip receiver & ring transmit to ring receive).
  • the system provides connected advantages.
  • the system generates bits by impedance variations.
  • a larger impedance is provided at the receiver.
  • virtual direct connect intentionally creates a series (longitudinal) imbalances as shown in FIGURE 44.
  • the counterweight effect is part of the Automatic Precision Impedance Measuring and Compensation Circuitry ("APIMC") used to counteract the attenuation effects longer transmission lines impose on transmitted signals.
  • APIMC Automatic Precision Impedance Measuring and Compensation Circuitry
  • This large impedance imbalance makes the line appear to be a very small load on the signal due to the percentage of change of voltage across the impedances (I*R). This is preferably done independently on each conductor.
  • An advantage is provided in low power transmission requirements.
  • the difference between the counterweight effect (FIGURE 44) and the APIMC as a whole is that the counterweight is a fixed impedance creating an imbalance and the APIMC uses variable impedances to keep balance within a range. This compensates for any negative effects caused by the line. This is additionally done independently on each conductor.
  • FIGURE 46 a total series impedance of a connected system on one conductor (i.e., Tip) is depicted. In this example, the total series impedance is 2.4 K prior to any changes occurring on the medium. In FIGURE 46, additional impedances that create the actual total impedance are not shown for simplicity.
  • FIGURE 47 an example is provided of how the APIMC circuitry reacts to changes in the transmission medium.
  • the medium' s impedance drops down to 250ohms and the total series impedance is reestablished to 2.4K by one or both ends of the virtual direct connect system. Additionally, this is done independently on each individual conductor.
  • FIGURE 48 in a embodiment a waveform is transmitted over tip that has a slope controlled asymmetric shape.
  • FIGURE 49 depicts the wave of FIGURE 48 encoded with impulses of current representing bits. The bits ride on the leading edge of the waveform and the trailing edge can be used as quiet space. These bits are not threshold dependent.
  • multiple bit representation can be achieved per bit by using thresholds.
  • the negative slope can be used for symmetric or inverted throughput increases.
  • This slope controlled asymmetric waveform is duplicated (i.e., shadowed) at different amplitudes and shifted prior to transmission over their independent lines.
  • FIGURE 50 depicts how the bits and entire waveform are sent in duplicate. The signal and its shadow are sent over their respective conductors. All of these factors provide for real time ratio processing and error correction at the receiver.
  • the virtual direct connect system enables a service provided to actually convert each individual connection of a tip and ring wire into two connections without laying cable.
  • This split utilization of a single twisted-pair provides flexibility and scalability to the service provides for keeping up with the growth of Internet appliances and other home networking and access devices. This may be beneficial in various cases and still provide more throughput than many conventional systems, however, this transformation in how the loop is used to communicate creates a paradigm shift in the overall approach to data transport and readies service providers for the bandwidth demands they face today and in the future.
  • CDDT current domain data transport
  • TWISTR two-wire independent signal transport
  • AU traveling wave phenomena such as waves on a string, sound waves, water waves, and even Maxwell' s plane wave equations satisfy the Helmholtz wave equation.
  • the TWISTR line-coding scheme can be compared to Ethernet encoding as depicted in FIGURE 51.
  • the 'S' stands for
  • TWISTR_S over Ethernet
  • the harmonics entering a lossy transmission are effectively "soften.”
  • the brick- wall effects of line inductance are reduced enabling the signal to transmit over a longer distance.
  • Another benefit of slow rising edges is the reduction of electromagnetic interference generated. This reduction of interference is further enhanced by the used of Current Domain techniques described later herein.
  • each cycle of a TWISTR_S line transmits 4 bits of information.
  • This is the identical channel capacity as a 16 QAM. Since two TWISTR_S signals (tip and ring) are used in parallel, this gives 8 bits of information per hertz. This is equivalent to the amount of information contained in a 256 QAM encoding; according to the 1999 xDSL report, the 64 QAM is the highest channel capacity in use and is limited to 4000 feet.
  • the higher QAM architectures have smaller inter-symbol margins and are therefore more susceptible to noise; consequently, they have shorter transmission distances.
  • the TWISTR_S does not suffer from tight symbol margins.
  • TWISTR_S transmission of the TWISTR_S is through a pair of digitally controlled current sources
  • the TWISTR data channel driven by a current source and a voltage source can be mathematic model wherein it is shown that the CDDT methodology produces less interference.
  • the energy coupled to the target due to inductive coupling and capacitive coupling between the data conduit and the target is calculated, then the results are collected for comparison.
  • Inductive coupling :
  • V(S) - s The above is a step.
  • the above equations, graphed in FIGURE 53 show that emissions from a current ramp are different from a voltage ramp.
  • the interference from a voltage ramp is a ramp.
  • the interference from a current ramp is a step function. If the interference occurs between tip and ring of the same pair, then the step interference will cause the least harm. This is because while one side of the pair is sloping, the other side is holding steady. A small step applied to the steady side will not hinder signal detection much.
  • CMRR complementary metal-oxide-semiconductor
  • judicious oversampling by the FPGA can be utilized. Since bit information in TWISTR_S overlaps, the signal preferably contains built in redundancy to allow simple error correction schemes.
  • the devices at each side of the communication line alternately send then listen.
  • the design uses digitally controlled current sources as line drivers, then switching between listen mode and transmit mode can easily be accomplished by one having ordinary skill in the art.
  • Foi ⁇ transmit send
  • the digital inputs are set to reflect the current to be transmitted.
  • listen mode the digital inputs are set to zero current. Because a current source is an open circuit by definition, there is no need to disconnect the drivers from the line.
  • a differential circuit can be used for eliminating interference.
  • FIGURE 54 provides a diagram depicting the output of a differential circuit with the input waveforms given.
  • the differential amplifier is constructed to subtract ring from tip. In so doing, the common mode interference is eliminated. Because the output of the differential amp is unconstrained by the switching limitations of the line, it is able to reconstruct a signal with all the originally transmitted information intact and extractable by digital signal processing means.
  • TWISTR__A which combines zero compression and other techniques, and yields a 2x increase in performance over TWISTR_S.
  • a FPGA performs DPLL synchronization on these detected edges.
  • the sampling points for slope detection will shift Vi bit period from the detected bit edges. To eliminate noise and increase sensitivity, oversampling is utilized.
  • the signal only transitions when there are ONEs to send. This means that transmitting data containing an excessive number of zeros may cause either/both outputs to maintain a constant level. This could cause a problem if the signal must pass through AC coupled circuits or across traditional twisted pair magnetics used in POTS.
  • a 1 is inserted into the bit-stream for every 7 zeros detected in a row on TIP or RING.
  • FIGURE 55 provides a chart depicting a one- insertion (X) on the RING.
  • Ones Insertion preferably occurs even if the lines are at zero potential. These transitions enable the DPLL to maintain synchronization. These transitions also prevent the receiver from falsely detecting silence (described in the next section) and dropping the current packet.
  • the One Insertion Counters start counting on the first bit of the ST byte.
  • OIC One Insertion Counters
  • the line is low for about 16 bit periods. This means that the lowest switching rate period is 32 bit cycles.
  • Twisted pair lines are typically lossy. This means that terminating a line with its characteristic impedance may not be as simple as terminating the line with a resistor.
  • the characteristic impedance of a lossy line is typically reactive. A reactive line will ultimately produce reflections if terminated by a real impedance.
  • Receive side reflections can be canceled by the Reflection cancellation algorithms as described above; however, this would not allow optimization of the line for full duplex operation (where both sides transmit at the same time).
  • Reflection cancellation algorithms as described above; however, this would not allow optimization of the line for full duplex operation (where both sides transmit at the same time).
  • all information that passes between near and far side is divided into “chunks” of 48 to 64 bytes each.
  • Each "chunk” is encapsulated in a frame. This process is called packetization.
  • the frame enables the system to determine what the type of information is (data or management/ control) being sent.
  • the frame provides a simple error check to determine system quality to enable the system to take measures to improve reliability.
  • the system encapsulates and sends OAM messages (Operation and Maintenance) as part of the normal chatter of operation. These are NOT ATM OAM cells.
  • OAM messages are specific to this system and are only a few bytes (Not an entire 53 byte CELL as with ATM).
  • the first byte of every frame is called the ST byte (SYNC/TYPE) it performs two functions.
  • the first function is to provide a start reference for the far side DPLL (Digital Phased locked loop).
  • the second function is to inform the far side what type of frame is being sent.
  • the Bytes in the system are transmitted MSB first.
  • the most significant bits of each ST byte contain the same pattern. This pattern is the sync pattern that provides a clean trapezoid on TIP for the far side to synchronize to.
  • the next 4 bits provide the frame type indicator.
  • FIGURE 56 depicts a cell data transport frame.
  • Cell data transport is the preferred transport method because it contains inherent information (such as cell size) that does not need to be enclosed in the transport.
  • cell size is an FPGA compile time constant and the cell size is optimized for ATM cell transport.
  • the Frame information is removed before the data is dumped into an FIFO.
  • the SOC flag is set on the first byte of the cell that enters the FIFO. Should a checksum error or the abrupt end of the cell be detected, the remainder of the cell is padded with zeros. The checksum error is logged as well as incomplete cells.
  • FIGURE 57 bulk data transport frames are depicts for supporting various interfaces and test platforms if needed. Preferably, however, this frame is not supported if not needed.
  • OAM management messages are depicted. The purpose of these messages is to allow the RISC processors to communicate to exchange operational information and control. There are many OM messages that fall into tins frame type. One such application of these messages is to place the system into line check mode where the system performs an iterative process to compensate for line changes.
  • FIGURE 59 an OAM startup message is depicted.
  • the purpose of this message is to negotiate the startup between the master and slave.
  • baud rate is in Kilobits per second. Although one embodiment can operate at operational speeds at or below 12.5 megabits per second, alternative embodiments of the system can have sampling at lOOmegasamples per second.
  • OAM termination messages are depicted that preferably serve two purposes. The first is to inform the far side that the current transmission session is complete and that it can start its transmission.
  • this message serves as a "heartbeat" when there is no information to be sent, these messages are constantly sent back and forth to check the integrity of the link.
  • the purpose of this message is the following: 1) To indicate that the session is complete; 2) To inform the other side how many cells in can receive ( how much space is left in its receive FIFO); and 3) To operate as a heartbeat/line-check message in the absence of data to transmit.
  • the OAM termination messages is automatically generated by FPGA.
  • the typical behavior of the system preferably includes a power-up mode, a seek mode, and an operational mode. On power-up the system performs a number of self diagnostics and then clears any counters and control variables. It will then place itself into the SEEK mode.
  • the board In seek mode the board will set lowest bandwidth mode. If the device is a slave, it will continually listen until it has received an OAM startup message (it will disregard all others. If the device is configured as a master, it will transit OAM startup messages.
  • the slave Once the slave has successfully received the startup message, it will reply with a startup reply messages. The Master will then send another startup message that instructs the slave to ascend to a given transmit rate (binary tree method to be used). At the new level, the slave will listen and the master will send the startup message again. If both sides receive the message without error, they will perform this operation until the highest baud rate is achieved. In later release, actual line test (such as impulse/step response) will be performed that will allow iterative processing in order to determine optimal frequency
  • the master When the master is done setting the operational frequency between the boards, it will issue the first OAM termination message that starts the Ping-Pong operation of the system.
  • a side receives a termination message it knows that it has control of the lines and it knows how many cells it can send. The number of data cells sent would be the lesser of the SpaceA byte just received or the number of cells it has in its FIFO.
  • a side When a side is finished sending (if it had any information to send) it will send a termination message with the amount of space remaining in its FIFO to the other side, and the process repeats.
  • HbtTimeout a configurable period of time
  • the period preferably should be no longer than 1.5 times the amount of time for a side to empty its buffer when the buffer is full.
  • Silence is preferably declared on a line (TIP or RING) when there are eight consecutive bit cycles without a transition.
  • the Silence State is maintained as long as there are no transitions on the line.
  • a TRUE silence condition is detected when the potential of the line is at a "zero volt" condition for the first eight bit cycles of the silence period.
  • the "zero volt" condition for TRUE silence is when the voltage is no more than 25% of the magnitude of the trapezoids.
  • True silence is used to delineate the space between frames (much the same way as Flag symbols in HDLC). Between Frames, TRUE silence is transmitted on one line only allowing the other line to provide synchronization. TRUE silence is transmitted on both lines when a transmitter relinquishes control of the lines to the opposite side. This occurs after the OAM termination message is sent. This technique provides redundant signaling.
  • a FALSE silence condition is detected when line is not at the "zero volt" conditions for the entire eight bit cycles of the silence declaration period.
  • FALSE silence is not sent during normal operation for any signaling purpose.
  • a condition of the lines similar to FALSE silence is used during line testing to measure the "Droop" of the line when a DC level is held. This measurement enables the TWISTR to determine the minimum switching rate of the line and, if desired, to pre-compensate for droop if needed at very long line lengths.
  • FIGURE 61 is a diagram illustrating the frame termination to
  • TRUE silence wherein 'S' denotes silence and 'T' denotes the termination cycle.
  • FIGURE 62 depicts an embodiment of signals between frames.
  • the inter-frame time is shorten by using a coding violation to force termination within 3 bit periods instead of 15.
  • Noise margin is a value used to determine if the change detected between two samples is significant. If the difference between two samples is less than or equal to the detected noise on the line than it can be said that there was no change on the line.
  • the system continually samples the Differential amplifier output to arithmetically determine the noise margin.
  • the noise margin is determined by reading samples over one bit period and computing the max-min of all the samples. This value is then saved. The process is completed for all the remaining bits in the silence period. The largest max-min of all the bit periods samples become the noise margin used for the next frame received.
  • the system preferably responds if the measured noise margin is larger than the expected slope difference.
  • signal averaging is used to reduce noise because of the amount of oversampling that can be performed.
  • slope detection is preferably by a sampling. However, other commonly know methods can be used.
  • a FPGA performs a minimum eight times oversampling of the differential amplifier output. That is, there will be at least eight samples taken within each bit period. Two samples ( A and B) are taken in the first half of the bit periods and two samples ( C and D) are taken in the second half of the bit period.
  • counters are kept by the PIC processor for interrogation network managing elements as depicted in FIGURE 65.
  • a two-wire system is created for a wireless system with different signals on each wire. This enables a parallel time shifted current modulation process.
  • the system provides for parallel time shifting because the peak of the two pulses are in different time position, the slope of the two pulses are different, the bits on the slopes are different in time positions but the start of the two pulses and the end of the two pulses are in the same time positions.
  • FIGURES 66-68 a simplified diagram and block diagrams are depicted of another embodiment of a system in accordance with the present invention.
  • the system includes a data transmitter device, a wireless data transmission medium such as air, and a data receiver.
  • the data receiver receives data signals transmitted from the transmitter across the wireless data transmission medium.
  • the single ended output of the transmitter is converted to a dual ended output by the transmitter output network (i.e., D5, D6, D7, D8, R22, and
  • the output 5 is connected through transgates 2 and 3 to the antenna and out 6 is connected through transgates 2 and 3 through an antenna return to C45 to ground.
  • the single ended input of the transmitter is converted to a dual ended input the recvinnet, antenna IN is connected through thrasgates 2 and 3 to the Antenna and Antenna Return IN is connected through transgates 2 and 3 through an Antenna Return to C45 to ground, the equivalent of a 2-wire system is created with a resultant current flow from Antenna through Antenna Return to C45 to ground.
  • a wireless transmission signal is received.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention, qui porte sur des équipements de communication de données (DCE), et plus spécifiquement de transmission de données électroniques entre équipements terminaux de données (DTE), propose un procédé et un dispositif de transmission d'un signal de tension converti en trains d'impulsions de courant, par exemple sur une ligne de communication, ce qui implique la conversion du signal de tension entrant en signal de courant, puis la transmission des impulsions de courant sur une ligne de communication soumise à une tension de polarisation prédéterminée.
EP01963744A 2000-07-27 2001-07-27 Appareil et procede de transmission de donnees Withdrawn EP1303956A2 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US22148200P 2000-07-27 2000-07-27
US22129600P 2000-07-27 2000-07-27
US221296P 2000-07-27
US221482P 2000-07-27
US22301500P 2000-08-04 2000-08-04
US223015P 2000-08-04
PCT/US2001/023646 WO2002011377A2 (fr) 2000-07-27 2001-07-27 Appareil et procede de transmission de donnees

Publications (1)

Publication Number Publication Date
EP1303956A2 true EP1303956A2 (fr) 2003-04-23

Family

ID=27396922

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01963744A Withdrawn EP1303956A2 (fr) 2000-07-27 2001-07-27 Appareil et procede de transmission de donnees

Country Status (4)

Country Link
EP (1) EP1303956A2 (fr)
CN (1) CN1466836A (fr)
AU (1) AU2001284670A1 (fr)
WO (1) WO2002011377A2 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005048889A1 (de) * 2005-10-12 2007-04-19 BSH Bosch und Siemens Hausgeräte GmbH Schnittstellenanordnung mit galvanischer Trennung für den Anschluss an ein elektrisches Gerät, insbesondere Hausgerät
JP5369010B2 (ja) * 2010-01-25 2013-12-18 パナソニック株式会社 通信システム
CN101814926B (zh) * 2010-04-01 2013-04-17 华为技术有限公司 一种信号传输装置和方法
CN102722109A (zh) * 2012-05-23 2012-10-10 常州芯奇微电子科技有限公司 高速接口终端负载的调节装置
CN108337010B (zh) * 2018-01-03 2020-02-18 浙江大学 一种基于载波加强技术的射频接收器
CN108563279A (zh) * 2018-07-11 2018-09-21 重庆线易电子科技有限责任公司 稳压滤波电路及信号检测电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4852160A (en) * 1987-03-03 1989-07-25 Kiko Frederick J Channel unit interface circuit
US5568064A (en) * 1995-01-23 1996-10-22 International Business Machines Corporation Bidirectional transmission line driver/receiver
US6760380B1 (en) * 1998-12-07 2004-07-06 Lynk Labs, Inc. Data transmission apparatus and method
DE19859178C1 (de) * 1998-12-21 2000-05-25 Siemens Ag Verfahren und System zum Übertragen von Daten in einem Kraftfahrzeug

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0211377A3 *

Also Published As

Publication number Publication date
WO2002011377A9 (fr) 2003-07-10
WO2002011377A2 (fr) 2002-02-07
WO2002011377A3 (fr) 2002-09-12
AU2001284670A1 (en) 2002-02-13
CN1466836A (zh) 2004-01-07

Similar Documents

Publication Publication Date Title
US20040124996A1 (en) Data transmission apparatus and method
US6618385B1 (en) High performance, high bandwidth, and adaptive local area network communications
US6094441A (en) Apparatus and method for controlling transmission parameters of home network stations transmitting on a telephone line medium
CA2266534C (fr) Technique de correction applicable a la derive de la ligne de base dans un emetteur
US5255287A (en) Transceiver apparatus and methods
US6236726B1 (en) Transmit power scaling for far-end crosstalk reduction
JPH09507978A (ja) 高速度伝送システム
US5715238A (en) Apparatus and method for detecting a loss of a telecommunications channel connection
US11228468B2 (en) Serdes equalization for short, reflective channels
RU2381627C1 (ru) Система для дуплексной передачи информации по двухпроводной линии связи
US5555277A (en) Technique for cancelling common mode switching noise to achieve reduced error rates in a local area network
US6965578B1 (en) Echo canceling method and apparatus for digital data communication system
EP0592747B1 (fr) Dispositif et procédé pour l'égalisation adaptive dans les systèmes de transmission en anneau à jeton utilisant des câbles à paires torsadées non-blindées
WO2002011377A2 (fr) Appareil et procede de transmission de donnees
EP0532717A1 (fr) Reseau rapide multisupport
US6956944B1 (en) Method and apparatus for compensating for an echo signal component in telecommunication systems
US6760380B1 (en) Data transmission apparatus and method
EP1675288A2 (fr) Dispositif pour transmettre un signal de données dans un réseau de télévision par cable
CN112565116B (zh) 一种信号处理方法、通信芯片以及通信装置
KR100367592B1 (ko) 적응형 전력선 통신 장치 및 통신 방법
US7463682B2 (en) Coding method for binary digits coding and its circuit for digits transmission
CN1655468B (zh) 用于全双工通信系统的可调式回音消除装置
US7408994B1 (en) AC coupling system for wide band digital data with dynamic AC load
US6584079B1 (en) Apparatus and method of implementing a home network by filtering ISDN-based signals within the customer premises
WO2001082545A2 (fr) Dispositif et procede d'echantillonnage de signal a multiples vitesses d'horloge

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20030206

AK Designated contracting states

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20050309