EP1298721A3 - Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices - Google Patents

Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices Download PDF

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Publication number
EP1298721A3
EP1298721A3 EP02256748A EP02256748A EP1298721A3 EP 1298721 A3 EP1298721 A3 EP 1298721A3 EP 02256748 A EP02256748 A EP 02256748A EP 02256748 A EP02256748 A EP 02256748A EP 1298721 A3 EP1298721 A3 EP 1298721A3
Authority
EP
European Patent Office
Prior art keywords
mask
applying
therethrough
forming
carrying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP02256748A
Other languages
German (de)
French (fr)
Other versions
EP1298721A2 (en
Inventor
Stephane Martel
Yan Riopel
Sebastien Michel
Luc Ouellet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teledyne Digital Imaging Inc
Original Assignee
Dalsa Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dalsa Semiconductor Inc filed Critical Dalsa Semiconductor Inc
Publication of EP1298721A2 publication Critical patent/EP1298721A2/en
Publication of EP1298721A3 publication Critical patent/EP1298721A3/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material. The sequence consists of the following steps:
  • (1) applying a first mask and forming at least one N-well in said p-type material therethrough;
  • (2) applying a second mask and forming an active region therethrough;
  • (3) applying a third mask and forming a p-type field region therethrough;
  • (4) applying a fourth mask and forming a gate oxide therethrough;
  • (5) applying a fifth mask and carrying out a p-type implantation therethrough;
  • (6) applying a sixth mask and forming polysilicon gate regions therethrough;
  • (7) applying a seventh mask and forming a p-base region therethrough;
  • (8) applying an eighth mask and forming a N-extended region therethrough;
  • (9) applying a ninth mask and forming a p-top region therethrough;
  • (10) applying a tenth mask and carrying out an N+ implant therethrough;
  • (11) applying an eleventh mask and carrying out a P+ implant therethrough;
  • (12) applying a twelfth mask and forming contacts therethrough;
  • (13) applying a thirteenth mask and depositing a metal layer therethrough;
  • (14) applying a fourteenth mask and forming vias therethrough;
  • (15) applying a fifteenth mask and depositing a metal layer therethrough; and
  • (16) applying a sixteenth mask and forming a passivation layer therethrough. Up to any three of mask steps 4, 7, 8, and 9 may be omitted depending on the type of integrated circuit.
    •
    EP02256748A 2001-09-28 2002-09-27 Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices Ceased EP1298721A3 (en)

    Applications Claiming Priority (2)

    Application Number Priority Date Filing Date Title
    US964472 2001-09-28
    US09/964,472 US6849491B2 (en) 2001-09-28 2001-09-28 Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices

    Publications (2)

    Publication Number Publication Date
    EP1298721A2 EP1298721A2 (en) 2003-04-02
    EP1298721A3 true EP1298721A3 (en) 2005-03-09

    Family

    ID=25508572

    Family Applications (1)

    Application Number Title Priority Date Filing Date
    EP02256748A Ceased EP1298721A3 (en) 2001-09-28 2002-09-27 Method of making high-voltage bipolar/CMOS/DMOS (BCD) devices

    Country Status (2)

    Country Link
    US (2) US6849491B2 (en)
    EP (1) EP1298721A3 (en)

    Families Citing this family (7)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    KR100437828B1 (en) * 2001-12-18 2004-06-30 주식회사 하이닉스반도체 method for manufacturing of BCD device
    TWI288241B (en) * 2005-11-30 2007-10-11 Ip Leader Technology Corp Probing apparatus, probing print-circuit board and probing system for high-voltage matrix-based probing
    US20100117153A1 (en) * 2008-11-07 2010-05-13 Honeywell International Inc. High voltage soi cmos device and method of manufacture
    CN102054785B (en) * 2010-11-04 2012-11-07 电子科技大学 Manufacturing method of high-voltage BCD semiconductor device
    CN102769028B (en) * 2011-05-03 2015-01-28 旺宏电子股份有限公司 Semiconductor structure and manufacturing method thereof
    US8912569B2 (en) * 2012-07-27 2014-12-16 Freescale Semiconductor, Inc. Hybrid transistor
    CN116306448B (en) * 2023-05-17 2023-08-11 深圳安森德半导体有限公司 Design method of digital-analog hybrid integrated circuit based on BCD (binary coded decimal) process

    Citations (10)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    DE2753704A1 (en) * 1977-12-02 1979-06-07 Bernd Prof Dr Rer Hoefflinger Combined transistor integrated circuit - has N-MOS, CMOS, D-MOS JFET and bipolar transistor on same silicon chip
    US4546370A (en) * 1979-02-15 1985-10-08 Texas Instruments Incorporated Monolithic integration of logic, control and high voltage interface circuitry
    EP0267882A1 (en) * 1986-11-10 1988-05-18 SGS MICROELETTRONICA S.p.A. Monolithic integration of isolated, high performance, power vdmos transistors and of high voltage p-channel mos transistors together with cmos, npn, pnp transistors and low leakage diodes
    EP0569204A2 (en) * 1992-05-08 1993-11-10 National Semiconductor Corporation Method of making N-channel and P-channel junction field-effect transistors and CMOS transistors using a CMOS or bipolar/CMOS process
    EP0708482A2 (en) * 1994-10-17 1996-04-24 SILICONIX Incorporated BiCDMOS process technology and structures
    US5556796A (en) * 1995-04-25 1996-09-17 Micrel, Inc. Self-alignment technique for forming junction isolation and wells
    US5856695A (en) * 1991-10-30 1999-01-05 Harris Corporation BiCMOS devices
    US5899714A (en) * 1994-08-18 1999-05-04 National Semiconductor Corporation Fabrication of semiconductor structure having two levels of buried regions
    US5917222A (en) * 1995-06-02 1999-06-29 Texas Instruments Incorporated Intergrated circuit combining high frequency bipolar and high power CMOS transistors
    US6130458A (en) * 1996-03-28 2000-10-10 Kabushiki Kaisha Toshiba Power IC having SOI structure

    Family Cites Families (8)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    US4795716A (en) 1987-06-19 1989-01-03 General Electric Company Method of making a power IC structure with enhancement and/or CMOS logic
    US5429959A (en) * 1990-11-23 1995-07-04 Texas Instruments Incorporated Process for simultaneously fabricating a bipolar transistor and a field-effect transistor
    US5798554A (en) 1995-02-24 1998-08-25 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno MOS-technology power device integrated structure and manufacturing process thereof
    US5578506A (en) 1995-02-27 1996-11-26 Alliedsignal Inc. Method of fabricating improved lateral Silicon-On-Insulator (SOI) power device
    EP0731504B1 (en) * 1995-03-09 2002-11-27 STMicroelectronics S.r.l. Process for the manufacturing of integrated circuits comprising lateral low-voltage and high-voltage DMOS-technology power devices and non-volatile memory cells
    JPH08335684A (en) 1995-06-08 1996-12-17 Toshiba Corp Semiconductor device
    US5681761A (en) 1995-12-28 1997-10-28 Philips Electronics North America Corporation Microwave power SOI-MOSFET with high conductivity metal gate
    US5854113A (en) 1996-11-01 1998-12-29 Electronics And Telecommunications Research Institute Method for fabricating power transistor using silicon-on-insulator (SOI) wafer

    Patent Citations (10)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    DE2753704A1 (en) * 1977-12-02 1979-06-07 Bernd Prof Dr Rer Hoefflinger Combined transistor integrated circuit - has N-MOS, CMOS, D-MOS JFET and bipolar transistor on same silicon chip
    US4546370A (en) * 1979-02-15 1985-10-08 Texas Instruments Incorporated Monolithic integration of logic, control and high voltage interface circuitry
    EP0267882A1 (en) * 1986-11-10 1988-05-18 SGS MICROELETTRONICA S.p.A. Monolithic integration of isolated, high performance, power vdmos transistors and of high voltage p-channel mos transistors together with cmos, npn, pnp transistors and low leakage diodes
    US5856695A (en) * 1991-10-30 1999-01-05 Harris Corporation BiCMOS devices
    EP0569204A2 (en) * 1992-05-08 1993-11-10 National Semiconductor Corporation Method of making N-channel and P-channel junction field-effect transistors and CMOS transistors using a CMOS or bipolar/CMOS process
    US5899714A (en) * 1994-08-18 1999-05-04 National Semiconductor Corporation Fabrication of semiconductor structure having two levels of buried regions
    EP0708482A2 (en) * 1994-10-17 1996-04-24 SILICONIX Incorporated BiCDMOS process technology and structures
    US5556796A (en) * 1995-04-25 1996-09-17 Micrel, Inc. Self-alignment technique for forming junction isolation and wells
    US5917222A (en) * 1995-06-02 1999-06-29 Texas Instruments Incorporated Intergrated circuit combining high frequency bipolar and high power CMOS transistors
    US6130458A (en) * 1996-03-28 2000-10-10 Kabushiki Kaisha Toshiba Power IC having SOI structure

    Non-Patent Citations (5)

    * Cited by examiner, † Cited by third party
    Title
    CHAN W W T: "A NOVEL CROSSTALK ISOLATION STRUCTURE FOR BULK CMOS POWER IC'S", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, vol. 45, no. 7, July 1998 (1998-07-01), pages 1580 - 1586, XP000776838, ISSN: 0018-9383 *
    FUJISHIMA N ET AL: "High packing density power Bi-CDMOS technology and its application for a motor driver LSI", POWER SEMICONDUCTOR DEVICES AND ICS, 1993. ISPSD '93., PROCEEDINGS OF THE 5TH INTERNATIONAL SYMPOSIUM ON MONTEREY, CA, USA 18-20 MAY 1993, NEW YORK, NY, USA,IEEE, US, 18 May 1993 (1993-05-18), pages 298 - 303, XP010116939, ISBN: 0-7803-1313-5 *
    HAMADA K ET AL: "A 60 V BiCDMOS device technology for automotive applications", INDUSTRY APPLICATIONS CONFERENCE, 1995. THIRTIETH IAS ANNUAL MEETING, IAS '95., CONFERENCE RECORD OF THE 1995 IEEE ORLANDO, FL, USA 8-12 OCT. 1995, NEW YORK, NY, USA,IEEE, US, vol. 2, 8 October 1995 (1995-10-08), pages 986 - 990, XP010193107, ISBN: 0-7803-3008-0 *
    LUDIKHUIZE A W: "A VERSATILE 700-1200-V IC PROCESS FOR ANALOG AND SWITCHING APPLICATIONS", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, vol. 38, no. 7, 1 July 1991 (1991-07-01), pages 1582 - 1589, XP000206654, ISSN: 0018-9383 *
    TSUI P G Y ET AL: "A VERSATILE HALF-MICRON COMPLEMENTARY BICMOS TECHNOLOGY FOR MICROPROCESSOR-BASED SMART POWER APPLICATIONS", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, vol. 42, no. 3, 1 March 1995 (1995-03-01), pages 564 - 570, XP000493964, ISSN: 0018-9383 *

    Also Published As

    Publication number Publication date
    US20030068844A1 (en) 2003-04-10
    US20050136599A1 (en) 2005-06-23
    EP1298721A2 (en) 2003-04-02
    US6849491B2 (en) 2005-02-01
    US7341905B2 (en) 2008-03-11

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