EP1296333A3 - Content addressable memory with power reduction technique - Google Patents

Content addressable memory with power reduction technique Download PDF

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Publication number
EP1296333A3
EP1296333A3 EP02021039A EP02021039A EP1296333A3 EP 1296333 A3 EP1296333 A3 EP 1296333A3 EP 02021039 A EP02021039 A EP 02021039A EP 02021039 A EP02021039 A EP 02021039A EP 1296333 A3 EP1296333 A3 EP 1296333A3
Authority
EP
European Patent Office
Prior art keywords
cam
generate
entry
clock signal
compare
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02021039A
Other languages
German (de)
French (fr)
Other versions
EP1296333A2 (en
Inventor
Georg Kong Yiu
Mark H. Pearce
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of EP1296333A2 publication Critical patent/EP1296333A2/en
Publication of EP1296333A3 publication Critical patent/EP1296333A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
  • Logic Circuits (AREA)

Abstract

A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that CAM cell match. A circuit is configured to logically AND the outputs to generate a hit output. A first compare line generator circuit is configured to generate a first pulse responsive to a clock signal and a data signal and a second compare line generator circuit is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. A CAM may include a circuit configured to generate a pulse indicating a hit in an entry of the CAM and a latch circuit configured to capture the pulse responsive to the first clock signal and configured to clear responsive to the second clock signal. A first CAM may store a value in each entry and may further store a compare result. A second CAM may include entries corresponding to the entries in the first CAM, and each entry may be coupled to receive the indication of the compare result from the corresponding entry of the first CAM and is configured to generate a second compare result which includes the first compare result.
EP02021039A 2001-09-21 2002-09-20 Content addressable memory with power reduction technique Withdrawn EP1296333A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/957,744 US6646899B2 (en) 2001-09-21 2001-09-21 Content addressable memory with power reduction technique
US957744 2001-09-21

Publications (2)

Publication Number Publication Date
EP1296333A2 EP1296333A2 (en) 2003-03-26
EP1296333A3 true EP1296333A3 (en) 2009-05-13

Family

ID=25500078

Family Applications (1)

Application Number Title Priority Date Filing Date
EP02021039A Withdrawn EP1296333A3 (en) 2001-09-21 2002-09-20 Content addressable memory with power reduction technique

Country Status (2)

Country Link
US (2) US6646899B2 (en)
EP (1) EP1296333A3 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650575B1 (en) * 2001-12-28 2003-11-18 Netlogic Microsystems, Inc. Programmable delay circuit within a content addressable memory
US6944040B1 (en) 2001-12-28 2005-09-13 Netlogic Microsystems, Inc. Programmable delay circuit within a content addressable memory
US7076635B1 (en) 2003-09-04 2006-07-11 Advanced Micro Devices, Inc. Method and apparatus for reducing instruction TLB accesses
US6944039B1 (en) * 2003-12-12 2005-09-13 Netlogic Microsystems, Inc. Content addressable memory with mode-selectable match detect timing
US7562179B2 (en) 2004-07-30 2009-07-14 Intel Corporation Maintaining processor resources during architectural events
US7085147B2 (en) * 2004-12-03 2006-08-01 Kabushiki Kaisha Toshiba Systems and methods for preventing malfunction of content addressable memory resulting from concurrent write and lookup operations
US7552275B1 (en) * 2006-04-03 2009-06-23 Extreme Networks, Inc. Method of performing table lookup operation with table index that exceeds CAM key size
US7606968B2 (en) * 2006-05-08 2009-10-20 Mcdata Corporation Multi-level content addressable memory
US8166239B2 (en) * 2007-06-21 2012-04-24 International Business Machines Corporation Translation lookaside buffer and related method and program product utilized for virtual addresses
WO2013101152A1 (en) 2011-12-30 2013-07-04 Intel Corporation Embedded branch prediction unit
US10064951B2 (en) * 2012-03-30 2018-09-04 Hanmi Science Co., Ltd. Liquid formulation of highly concentrated long-acting human growth hormone conjugate
US9007799B2 (en) * 2012-04-25 2015-04-14 Intel Corporation Low power content addressable memory system
US8654555B2 (en) * 2012-06-04 2014-02-18 Raytheon Company ROIC control signal generator
US9123438B2 (en) * 2013-10-15 2015-09-01 Nvidia Corporation Configurable delay circuit and method of clock buffering
CN110874332B (en) * 2016-08-26 2022-05-10 中科寒武纪科技股份有限公司 Memory management unit and management method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4894799A (en) * 1987-05-13 1990-01-16 Hitachi, Ltd. Content-addressable memory
US5689454A (en) * 1996-01-11 1997-11-18 Cyrix Corporation Circuitry and methodology for pulse capture
US5699288A (en) * 1996-07-18 1997-12-16 International Business Machines Corporation Compare circuit for content-addressable memories
US5754463A (en) * 1996-07-15 1998-05-19 Intel Corporation Multi-ported content addressable memory with precharge "non match"

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5446685A (en) * 1993-02-23 1995-08-29 Intergraph Corporation Pulsed ground circuit for CAM and PAL memories
US5541538A (en) * 1994-09-01 1996-07-30 Harris Corporation High speed comparator
US5999435A (en) * 1999-01-15 1999-12-07 Fast-Chip, Inc. Content addressable memory device
JP4748828B2 (en) * 1999-06-22 2011-08-17 ルネサスエレクトロニクス株式会社 Semiconductor memory device
US6166939A (en) * 1999-07-12 2000-12-26 Net Logic Microsystems Method and apparatus for selective match line pre-charging in a content addressable memory
US6266263B1 (en) 2000-10-02 2001-07-24 Integrated Device Technology, Inc. CAM array with minimum cell size

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4894799A (en) * 1987-05-13 1990-01-16 Hitachi, Ltd. Content-addressable memory
US5689454A (en) * 1996-01-11 1997-11-18 Cyrix Corporation Circuitry and methodology for pulse capture
US5754463A (en) * 1996-07-15 1998-05-19 Intel Corporation Multi-ported content addressable memory with precharge "non match"
US5699288A (en) * 1996-07-18 1997-12-16 International Business Machines Corporation Compare circuit for content-addressable memories

Also Published As

Publication number Publication date
US20030061434A1 (en) 2003-03-27
US6646899B2 (en) 2003-11-11
EP1296333A2 (en) 2003-03-26
US20040052133A1 (en) 2004-03-18
US6785152B2 (en) 2004-08-31

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