EP1292982A2

EP1292982A2 - Gate oxidation for vertical trench device

Info

Publication number: EP1292982A2
Application number: EP01948584A
Authority: EP
Inventors: Alexander Michaelis; Helmut Horst Tews; Stephan Kudelka; Ulrike Gruening; Jochen Beintner; Uwe Schroeder
Original assignee: Infineon Technologies North America Corp
Current assignee: Infineon Technologies North America Corp
Priority date: 2000-06-21
Filing date: 2001-06-21
Publication date: 2003-03-19
Also published as: WO2001099162A2; WO2001099162A3; TW526584B

Abstract

A method of using a selective etch to provide a desired crystal plane orientation on the sidewalls of a deep trench located in a semiconductor substrate, and the device formed therefrom. Preferably, a <100> crystal plane sidewall (212) is used for the channel region, and <110> crystal planes (216) are used in the corner regions of the trench. Gate oxidation may then be performed such that the oxide is thicker in the corner regions (222) than on the oxide (218, 220) on the primary sides of the trench, resulting in self isolation of the corner areas from the transistor channel/active area (224). In addition, the structure is relatively insensitive to active area/deep trench misalignment.

Description

SELF-ISOLATED GATE OXIDATION FOR AN INTEGRATED CIRCUIT VERTICAL

DEVICE

TECHNICAL FIELD

The present invention relates generally to an integrated circuit ("IC") and method of forming thereof, and more particularly to an integrated circuit vertical trench device and method of forming thereof.

BACKGROUND

The semiconductor industry is continuously trying to decrease the size of the semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today's semiconductor products. For example, it is not uncommon for there to be millions of semiconductor devices on a single semiconductor product.

Typically, the focus of miniaturization has been placed on the two-dimensional horizontal plane of a semiconductor device, and devices have approached sizes down to tenths of microns and less. There is some limit, however, as to how far a horizontally oriented semiconductor device can be shrunk, and as devices are made even smaller, it is generally becoming increasingly difficult to further miniaturize a device's horizontal dimensions. In addition, the decreasing horizontal dimensions of semiconductor devices generally tend to create problems in the operational characteristics of the semiconductor devices.

One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor memory is a dynamic random access memory ("DRAM"). A DRAM may include millions or billions of individual DRAM cells, each cell storing one bit of data. A DRAM memory cell typically includes an access field-effect transistor ("FET") and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.

Semiconductor memory density is typically limited by a minimum lithographic feature size that is imposed by lithographic processes used during fabrication. There is a continuing need in the art to provide even higher density memories in order to further increase data storage capacity and reduce manufacturing costs.

One way of increasing the data storage capacity of semiconductor memories is to reduce the amount of integrated circuit horizontal planar area consumed by each memory cell. For horizontally oriented devices, this may be done by decreasing the size of the access FET or the storage capacitor, or both. This approach has limits, however, due to minimum producible structure size in a given fabrication technology, and the problems associated with devices with small dimensions, such as hot carriers, punch through, and excess leakage.

Another way of providing planar area reduction is the use of a three-dimensional arrangement of the access FET and the storage capacitor. One such arrangement is a planar FET next to a deep trench capacitor. A trench typically has a depth of 5-8um and an oval top-down-view shape. The trench capacitor has plates which are located vertically along the walls of the trench instead of being parallel to the surface of the integrated circuit substrate. This permits a large capacitance per planar unit area of substrate, while at the same time allowing the device to be of a manageable size for purposes of operation.

To still further reduce the amount of planar area required for each cell, it has been proposed to use a vertical trench transistor in conjunction with a vertical trench capacitor in a memory cell. In a typical design, the vertical capacitor is generally fabricated in a trench, with one conductive plate being formed in the substrate, the dielectric being formed on the trench sidewalls, and the other conductive plate being formed in the interior of the trench. A vertical trench transistor is generally fabricated adjacent to an upper portion of the trench, with the source and drain being fabricated in the substrate, and the vertically-oriented gate being fabricated in the trench.

There are generally several problems, however, with prior art approaches to fabricating a vertical transistor in a DRAM cell. One difficult fabrication issue is related to formation of the vertically-oriented gate. Typically, the gate insulator is an oxide produced by thermal oxidation of the trench sidewall. The thickness of the gate insulator generally determines the threshold voltage required to turn on the device. Ideally, the gate insulator thickness should be uniform along the channel length and width.

The oxidation rate of the trench sidewall, however, is generally highly dependent upon the crystal plane orientation of the sidewall. In other words, different crystal planes may generate oxides of very different thicknesses when subjected to the same thermal oxidation process. In a trench formed in a substrate (e.g., a rounded (including oval) trench, top-down view), different crystal orientations are exposed to the oxidation process because the sidewalls cut through different crystal planes in the substrate. Thermal oxidation of the sidewalls thus results in different oxide thicknesses around the trench dependent upon crystal orientation. A non-uniform oxide thickness for the gate insulator may cause leakage and other device reliability problems. In addition, the non-uniformity may cause inconsistent threshold voltages from device to device. One proposal to alleviate this problem is a selective wet etch using, for example, an NH₄OH solution. This solution generally etches the <100> crystal planes faster than the <110> crystal planes, which may result in an octagonal trench shape with relatively longer <110> plane sides (4 of the 8 sides), and smaller <100> plane cut-off corners (the other 4 sides). The oxidation rate between the <110> planes and the <100> crystal planes is typically on the order of 2:1. Thus, when the sidewalls are oxidized, the primary <110> sides grow a thick oxide, while the < 100> corners grow a thinner oxide.

In a typical device, the active area of the vertical trench is formed adjacent to a <110> plane side with the thick oxide serving as a gate oxide. A potential problem with this approach, however, is that the structure is sensitive to active area/trench alignment. If there is misalignment in the active area/trench intersection, part of the active area may overlap the thin oxide in the <100> plane corner of the trench, which could significantly affect the characteristics or operability of the device. For example, the threshold voltage may be altered, or excess leakage could occur in the device.

One approach proposed to address this problem is the addition of extra process steps for the implantation of, for example, N₂ or Ar, along with specific oxidation parameters. Thus far, these proposed processes result in additional cost, and do not sufficiently alleviate the reliability issues.

SUMMARY OF THE INVENTION

These problems are generally solved or circumvented, and technical advantages are generally achieved, by a preferred embodiment of the invention in which a selective etch is used to provide a different crystal plane orientation on the trench sidewalls than that of prior art devices. Preferably, a <100> crystal plane sidewall is used for the channel region, and <110> crystal planes are used in the corner regions. Gate oxidation may then be performed such that the oxide is thicker in the corner regions than on the primary sides of the trench, resulting in self isolation of the corner areas from the transistor channel/active area.

In accordance with a preferred embodiment of the present invention, a DRAM IC comprises a deep trench located in a semiconductor substrate, the trench having an upper portion comprising primary sidewalls with a second crystal plane and comer sidewalls with a first crystal plane, a thin oxide on at least one primary sidewall, a thick oxide on two corner sidewalls adjacent the at least one primary sidewall, and an active area of a vertically oriented device located in the substrate adjacent the at least one primary sidewall. Preferably, the first crystal plane is a <110> crystal plane, and the second crystal plane is a <100> crystal plane. In accordance with another preferred embodiment of the present invention, a method of forming a vertically oriented device on a semiconductor substrate comprises forming a deep trench in the semiconductor substrate, wherein the trench has a rounded perimeter, and wherein the trench comprises sidewalls with first and second substrate crystal planes, selectively etching the first substrate crystal plane in at least an upper portion of the trench using a crystal plane dependent etch, thereby forming trench primary sidewalls comprising the second crystal plane, and smaller trench corner sidewalls comprising the first crystal plane, oxidizing at least one primary sidewall and two adjacent corner sidewalls using crystal plane dependent oxidation, wherein a thin oxide is formed on the at least one primary sidewall, and wherein a thick oxide is formed on the adjacent trench corner sidewalls, and forming an active area of the vertically oriented device in the substrate adjacent the thin oxide. Preferably, an HF/H₂O₂ wet solution is used for the selective etch. Also preferably, the oxidation is selective toward the first substrate crystal plane over the second substrate crystal plane by at least about a 2:1 ratio.

An advantage of a preferred embodiment of the present invention is that a DRAM, memory cell may be formed with a trench capacitor and a vertical transistor, thus using devices of manageable size yet occupying minimal horizontal planar area.

Another advantage of a preferred embodiment of the present invention is that the vertical gate oxide is substantially uniform across the channel width and length, providing reduced chance of leakage, and consistent threshold voltages from device to device.

Another advantage of a preferred embodiment of the present invention is that the corners of the trench provide a thick grown oxide for device isolation.

Another advantage of a preferred embodiment of the present invention is that the resulting structure is relatively insensitive to active area/deep trench misalignment, providing for a more robust process than those used in the prior art.

Another advantage of a preferred embodiment of the present invention is that the difference in the oxide thickness around the vertical trench surface/sidewall corner is minimized because the relatively thinner oxide is intended to coincidence with the transistor channel.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWING

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:

FIGURES 1A and 1B are plan and cross-sectional views, respectively, of a prior art round deep trench;

FIGURES 2-5 are plan views of the prior art structure of FIGURE 1 at various subsequent stages of fabrication;

FIGURES 6A and 6B are plan and cross-sectional views, respectively, of a round deep trench in accordance with a preferred embodiment; and

FIGURES 7-10 are plan views of the structure of FIGURE 6 at various subsequent stages of fabrication.

DETAILED DESCRIPTION

The making and use of the presently preferred embodiments are discussed below in detail. However, it should be appreciated that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. The figures are drawn so as to clearly illustrate the relevant aspects of the preferred embodiments, and are not necessarily drawn to scale.

The invention relates to integrated circuits, including memory ICs such as random access memories ("RAM"s), DRAMs, synchronous DRAMS ("SDRAM"s), merged DRAM- logic circuits ("embedded DRAM"s), or other circuits. The invention also relates to semiconductor processes and structures, including vertical capacitors, vertical transistors, trench capacitors and trench transistors, the connections between such semiconductor devices, or other processes and structures.

Referring now to Figs. 1A and 1 B, there are illustrated a top-down view and a cross- sectional view, respectively, of an initial fabrication stage of prior art device 100 comprising deep trench 102 etched into silicon substrate 104. Trench 102 typically has an oval shaped with rounded sidewalls. Sides 106 and 108 of trench 102 have a <110> crystal plane orientation, while corners 110 of trench 102 have a <100> crystal plane orientation. In the prior art, the sidewalls of trench 102 are further etched, for example, to provide a flatter surface on which to form a gate oxide. As shown in Fig. 2, a selective wet etch using NH₄OH is selective to the <100> crystal planes over the <110> crystal planes, thus forming a trench with primarily <110> crystal plane sidewalls 112 and 114, and <100> crystal plane corners 116.

Referring now to Fig. 3, the etched sidewalls of the trench are thermally oxidized to form a gate oxide for the vertical trench transistor. The thermal oxidation process is crystal plane dependent, and is selective to the <110> crystal plane over the <100> crystal plane, typically by a ratio of about 2:1. Therefore a thin oxide 122 is formed in the trench corners, and a thick oxide 118, 120 is formed on the trench primary sides. In Fig. 3, thick oxide 118 is intended to be a gate oxide for the transistor.

Referring to Fig. 4, active area 124 for the transistor is formed in substrate 104 adjacent thick gate oxide 118. Using this design, the threshold voltage for the transistor is determined by the thickness of thick oxide 118. A problem may exist however, with the thin oxide 122 at the corners of the trench. If the <100> crystal plane overlaps with active area 124, then active area 124 will intersect with a thinner oxide over at least a portion of the active area. This may detrimentally affect the threshold voltage of the device, device leakage, and device reliability. As shown in Fig. 5, the device is also susceptible to process variations. Active area 126 is misaligned with thick gate oxide 118, causing it to intersect with thin oxide 122, with the same potential device problems as discussed above.

The above problems are solved or circumvented by a preferred embodiment of the invention as shown in Figs. 6-10. Referring first to Figs. 6A and 6B, there are illustrated a top-down view and a cross-sectional view, respectively, of an initial fabrication stage of vertical device 200 comprising deep trench 202 etched into silicon substrate 204. In Trench 202 preferably has ah oval shaped with rounded sidewalls. In contrast to the prior art device illustrated in Figs. 1A-1 B, sides 206 and 208 of trench 202 have a <100> crystal plane orientation, while corners 210 of trench 202 have a <110> crystal plane orientation. In other words, the design or wafer notch orientation has been rotated, for example, about 45° from that shown in Figs. 1A-1 B.

It should be noted that several process steps, known to those of ordinary skill in the art, but unnecessary to an understanding of the present invention, are not described in detail herein. For example, several process steps may be performed on the device in arriving at the process stage illustrated in Fig. 7. A trench capacitor may be formed in a lower portion of trench 202, comprising an outer plate formed in the substrate (e.g., by doping), a node dielectric (e.g., silicon dioxide) formed on the trench sidewalls and an inner plate (e.g., polysilicon) formed in trench 202. An isolation collar (e.g., silicon dioxide) may also be formed around the perimeter of an upper portion of trench 202. In addition, a buried strap connection may be formed between the trench capacitor inner electrode and the region of the substrate which will contain the transistor active area.

Referring now to Fig. 7, a selective etch is performed on the exposed substrate sidewalls. The selective etch may be performed on the whole trench, or more preferably on just an upper portion of the trench. In addition, the selective etch may be performed on the entire upper portion of the trench, or more preferably on one section of the trench upper portion. Most preferably, an H₂O/HF/H₂O₂ solution, with a ratio of 200:1 :4, respectively, is used to perform the wet etch, although other etching solutions and concentrations may be used. This solution etches the <110> crystal planes faster than the <100> crystal planes, allowing the formation of a trench with primarily <100> crystal plane sides and smaller <110> crystal plane comers, which is effectively opposite the crystal plane orientations of the prior art device shown in Fig. 2. Thus, as shown in Fig. 7, primary sidewalls 212 and 214 have <100> crystal planes, and corners sidewalls 216 have <110> crystal planes.

A trench top oxide may be formed in the trench overlying the polysilicon capacitor inner plate and the polysilicon buried strap. The trench top oxide is preferably silicon dioxide, but may be silicon nitride or any other suitable insulator material. A sacrificial oxidation/etching may also be performed to remove excess polysilicon material from the trench. In addition, dopant implantation may be performed to change the conductivity of particular layers.

Referring to Fig. 8, the exposed sidewalls of trench 200 are subjected to thermal oxidation to form the transistor gate oxide. A conventional thermal gate oxidation with well known reliability parameters is preferably used. The <100> crystal planes on primary sidewalls 212 and 214 generally oxidize only about half as fast as the <110> crystal planes on corner sidewalls 216. The slower growing oxidation permits better thickness and uniformity control of the gate oxide formed on primary sidewall 212 than prior art approaches. Thus thin oxides 218 and 220 are formed on the primary sidewalls of the trench, while thick oxides 222 are formed on the corner sidewalls. The difference in the <110>:<100> oxidation rate is now a beneficial process characteristic because the thick oxides on the <110> planes provide self-isolation of the corner areas.

Referring to Fig. 9, thin oxide 218 is used as the gate oxide for the vertical trench transistor. A transistor active area 224 is implanted in the substrate adjacent gate oxide 218. Only the <100> crystal plane trench sidewall is used for the transistor channel region, instead of the <110> crystal plane used in the prior art. The thickness of thin gate oxide 218 is well-controlled and is uniform across the channel region, providing improved device reliability and consistent threshold voltages from device to device. An example demonstrating the improved robustness of the process is illustrated in Fig. 10. The structure is generally less sensitive to active area/trench misalignment than structures in the prior art. As shown in Fig. 10, active area 226 is misaligned with the gate oxide 218, and actually overlaps corner sidewall thick oxide 222. Introducing a thick oxide into the active area/gate oxide interface, however, does not significantly degrade the performance of the transistor, because the thin oxide still primarily determines the device is characteristics.

The remainder of a DRAM cell, including connections to word and bit lines, may be completed using conventional DRAM processing techniques. The resulting DRAM may then be employed in a variety of cpmmercial and consumer electronics devices, including computers.

There are many alternative materials and processes which could be substituted for those disclosed in the above embodiments by one of ordinary skill in the art, and all such alternatives are considered to be within the scope of the present invention. For example, various other types of etches, sμch as a dry etch, may be used in accordance with the present invention to selectively etch specific crystal planes in the trench sidewalls. As another example, p-type materials or doping may be substituted for n-type materials and doping, and vice versa. As another example, the transistor active area may be formed at an angle to the primary sidewall of the deep trench, or may intentionally overlap with the thick oxide in the corner sidewalls. As yet another example, the vertical transistor is preferably a single side transistor, but may be implemented in other ways. In addition, the order of process steps may be rearranged by one of ordinary skill in the art, yet still be within the scope of the present invention. As used herein, devices, layers, materials, etc. may be described, for example, as being "in" a trench, or formed "on" a trench sidewall surface, and all such descriptions are generally intended to include such devices, layers, and materials extending into regions proximate the trench or sidewall surface where appropriate.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

WHAT IS CLAIMED IS:

1. A method of forming a vertically oriented device on a semiconductor substrate, said method comprising: forming a deep trench in said semiconductor substrate, wherein said trench has a rounded perimeter, and wherein said trench comprises sidewalls with first and second substrate crystal planes; selectively etching said first substrate crystal plane in at least an upper portion of said trench using a crystal plane dependent etch, thereby forming trench primary sidewalls comprising said second crystal plane, and smaller trench corner sidewalls comprising said first crystal plane; oxidizing at least one primary sidewall and two adjacent corner sidewalls using crystal plane dependent oxidation, wherein a thin oxide is formed on said at least one primary sidewall, and wherein a thick oxide is formed on said adjacent trench corner sidewalls; and forming an active area of said vertically oriented device in said substrate adjacent said thin oxide.

2. The method of claim 1 , wherein said first crystal plane is a <110> crystal plane, and said second crystal plane is a <100> crystal plane.

3. The method of claim 1 , wherein multiple <110> crystal plane surfaces in said trench are etched.

4. The method of claim 1 , wherein said selective etching is highly selective toward said first substrate crystal plane over said second substrate crystal plane, and wherein said selective etching only minimally etches said sidewalls in said second substrate crystal plane directions.

5. The method of claim 1 , wherein said selectively etching comprises a selective wet etch.

6. The method of claim 5, wherein said substrate is silicon, and wherein said selectively etching comprises using an H₂O/HF/H₂O₂ solution.

7. The method of claim 1 , wherein said oxidizing is selective toward said first substrate crystal plane over said second substrate crystal plane by at least about a 2:1 ratio.

8. The method of claim 1 , wherein said vertically oriented device is a transistor, and said thin oxide is a gate oxide of said transistor.

9. A dynamic random access memory (DRAM) integrated circuit (IC) comprising: a deep trench located in a semiconductor substrate, said trench having an upper portion comprising primary sidewalls with a second crystal plane and corner sidewalls with a first crystal plane; a thin oxide on at (east one primary sidewall; a thick oxide on two corner sidewalls adjacent said at least one primary sidewall; and an active area of a vertically oriented device located in said substrate adjacent said at least one primary sidewall.

10. The DRAM IC of claim 9, further comprising a trench capacitor located in a lower portion of said deep trench.

11. The DRAM IC of claim 10, further comprising a trench top oxide in said trench overlying said trench capacitor.

12. The DRAM IC of claim 10, further comprising an electrical connection from an interior plate of said capacitor to said active area of said vertically oriented device.

13. The DRAM IC of claim 9, wherein said vertically oriented device is a transistor, and wherein said thin oxide is a gate oxide of said transistor.

14. The DRAM IC of claim 13, wherein said transistor is a single side vertical transistor.

15. The DRAM IC of claim 9, wherein said substrate is silicon, said first crystal plane is a <110> crystal plane, and said second crystal plane is a <100> crystal plane.

16. The DRAM IC of claim 9, wherein said thin and thick oxides are silicon dioxide.

17. The DRAM IC of claim 9, wherein a thickness ratio of said thick oxide to said thin oxide is at least about 2:1.

18. A method of forming a dynamic random access memory (DRAM) integrated circuit, said method comprising: forming a deep trench in said semiconductor substrate, wherein said trench has a rounded perimeter, and wherein said trench comprises sidewalls with first and second substrate crystal planes; forming a trench capacitor in a lower portion of said deep trench, said capacitor comprising a first plate in said substrate, a dielectric formed on said sidewalls, and an inner plate formed in said trench; forming an buried strap between said capacitor inner plate and said substrate; selectively etching said first substrate crystal plane in an upper portion of said trench using a crystal plane dependent etch, thereby forming trench primary sidewalls comprising said second crystal plane, and smaller trench corner sidewalls comprising said first crystal plane; oxidizing at least one primary sidewall and two adjacent corner sidewalls using crystal plane dependent oxidation, wherein a thin vertical transistor gate oxide is formed on said at least one primary sidewall, and wherein a thick isolation oxide is formed on said adjacent trench corner sidewalls; and forming an active area of said transistor in said substrate adjacent said gate oxide and electrically connected to said buried strap.

20. The method of claim 19, wherein said first crystal plane is a <1 0> crystal plane, and said second crystal plane is a <100> crystal plane.

21. The method of claim 19, wherein said selectively etching comprises a selective wet etch.

22. The method of claim 21 , wherein said substrate is silicon, and wherein said selectively etching comprises using an H₂O/HF/H₂O₂ solution.

23. The method of claim 19, wherein said oxidizing is selective toward said first substrate crystal plane over said second substrate crystal plane by at least about a 2:1 ratio.