EP1256175A1 - Preparation de donnees destinees a un decodeur reed-solomon - Google Patents

Preparation de donnees destinees a un decodeur reed-solomon

Info

Publication number
EP1256175A1
EP1256175A1 EP00987387A EP00987387A EP1256175A1 EP 1256175 A1 EP1256175 A1 EP 1256175A1 EP 00987387 A EP00987387 A EP 00987387A EP 00987387 A EP00987387 A EP 00987387A EP 1256175 A1 EP1256175 A1 EP 1256175A1
Authority
EP
European Patent Office
Prior art keywords
data
buffer
address
ecc
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP00987387A
Other languages
German (de)
English (en)
Inventor
Lothar Freissmann
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Priority to EP00987387A priority Critical patent/EP1256175A1/fr
Publication of EP1256175A1 publication Critical patent/EP1256175A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1806—Pulse code modulation systems for audio signals
    • G11B20/1809—Pulse code modulation systems for audio signals by interleaving

Definitions

  • the present invention relates to a method and an arrangement for a preparation of data for a Reed - Solomon decoder and more particulariv to a method and an arrangement for an intelligent buffer in front of a Reed - Solomon decoder that needs less RAM and ensures high performance
  • a conventional pre-processmg buffer and Reed - Solomon use a common RAM to handle corrupted data
  • Such an arrangement and processmg is for example used to correct data stored on an optical information media like a DVD for reproduction purposes It is desirable to avoid to feed corrupted data to the Reed - Solomon decoder or to use a RAM to store the ECC block or to read defect parts several times what decreases the speed of the data path DVD is an acronym for Digital Versatile Disc and ECC is an acronym for Error Correction Code - an electronic method of checkmg the integrity of data
  • the data of the ECC is hierarchically organized in pieces of the data stream
  • the highest unit is an ECC - block that is divided into a number of sectors Each sector is built up by a number of rows with a fixed length
  • the number of the additional bytes determines the number of correctable faults per row
  • the same calculation is performed vertically over all bytes of an ECC - block which are at the same position of a row. the result is organized m additional rows of the ECC - block
  • the first bytes contain identification information
  • the blocks in front of the buffer and Reed - Solomon part get the stream m frames two of which building a ro .
  • an identification of the frame order is evaluated and the result made available to the buf er by approp ⁇ ate sync - signals
  • a conventional arrangement stores the data mto the common RAM with respect of the identification control results before the Reed - Solomon decoder starts to perform the correction of corrupted data bytes
  • Replacmg the faulty data m memory would require processmg overhead that could accumulate and significantly dimmish system performance
  • RAM is an acronym for Random Access Memory It is a temporary storage area that the processor uses to execute programs and to hold data
  • Reed Solomon is a techmque term for a forward error correcting code that is used to offset the effects of bit error m the receiving bit stream Reed- Solomon codes are special and widely implemented because they are almost perfect in the sense that the extra redundant data added on by the encoder is at a minimum for any level of error correction, so that no bits are wasted
  • a method and an arrangement for an intelligent buffer in front of a Reed - Solomon decoder as for example a DVD Reed - Solomon decoder are provided m which the data are analysed based on the incoming sync - signals and the data are buffered at approp ⁇ ate buffer locations as long as the incoming ECC - block can be repaired by the Reed - Solomon decoder In case that the ECC - block cannot be corrected the Reed - Solomon decoder gets a reset signal to cancel the first stage of processmg An address control block and a buffer form said intelligent buffer
  • the front-end circuit has no way to store a complete incoming ECC - block before sendmg it as a contmuous data stream to the Reed - Solomon decoder Without any precaution the Reed - Solomon decoder will get many disordered ECC - blocks which the decoder cannot correct This leads to a poor performance of the complete circuitry
  • the intelligent buffer of m front of the Reed - Solomon - decoder accordmg to the mvention t ⁇ es to keep the organization of the data as far mtact as possible and smoothes small defects, in the case that the defects will lead to corrupted data the Reed - Solomon block and the micro controller will be informed about the corrupted data
  • the Reed - Solomon buffer interface is also usable m other context
  • the classification of data and synchronization lacks will hold true for other block codes
  • a buffer is a little room for data storage
  • the buffer is placed between two units, which exchange data
  • the buffer's function give room for a temporary storage of the data coming from a unit in a situation where the other umt is not ready to receive the data
  • the buffer holds these data for a while and delivers them as soon as the recipient is ready to receive them
  • the data commg from the acquisition part must be buffered before they can be delivered to the Reed - Solomon correction block to compensate slight defects of
  • the buffer block should be able to resynchromse the data stream at frame and sector boundaries to avoid that inappropriate frame length corrupts the Reed-Solomon
  • the buffer block stops the current first pass inner/outer correction of the Reed-Solomon decoder and resynchronises at the next ECC - block boundary
  • the Reed-Solomon- buffer interface must be reset in case of physical jumps
  • an intelligent buffer is used for a first step Reed Solomon correction that deals with the rows of an ECC - block Only some rest ⁇ ctions concerning the allowed jump area have to be respected In such a way advantageously a ramless Reed-Solomon decoder that having a high performance and requires less RAM-memory is performed BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGURE 1 is a block diagram for an intelligent buffer in front of a ramless
  • FIGURE 2 is a schematic for forward jumps m case of addr_m>addr_out.
  • FIGURE 3 is a schematic for forward jumps m case of addr_m ⁇ addr_out
  • FIGURE 4 is a schematic for backward jumps m case of addr_m>addr_out
  • FIGURE 5 is a schematic for backward jumps in case of addr n>addr_out and
  • FIGURE 6 shows mput- and output-address of the buffer in case of jumps in sector ED
  • the first part is an acquisition block ACQ that provides a clock byte clk of incoming data, the data at data line data in and synchronizing information.
  • the second part is an address control block ADC that creates addresses and control signals from the synchronisation signals provided from acquisition block ACQ, there are addresses for the m-going data stream at data line data in and addresses and the control-out-signal ctrl out for the outgomg data data out sent from the buffer BUF to the Reed-Solomon decoder
  • the third part is buffer BUF constructed as storage array with dual ports to handle mdependent time schemes for outgoing data data out and incoming data on data lme data in It may also be constructed with on IO-port if the mput- and output-data streams are approp ⁇ ate decoupled
  • the address control block ADC and the buffer BUF form the so-called intelligent buffer IBUF accordmg to the invention
  • a further block shows a generator clk gen to generate an independent clock out_clk used for the outgoing data data out stream This task represents a part of the not shown Reed - Solomon decoder
  • the generator clk_gen is connected to address control block ADC and buffer BUF for providmg the independent clock out clk . which is also used to read data from the buffer BUF to the not shown Reed Solomon block
  • a further clock byte clk of incoming data data in is de ⁇ ved from the acquisition-block ACQ and applied to address control block ADC and via an AND-gate & to the buffer BUF
  • the other input of said AND-gate & is connected to an output of the address control block ADC providmg an buffer-mput-enable-signal m en that enables the input of the buffer BUF via said AND-gate & by a masked byte clock signal byte_clk_msk formed by said AND-gate & and applied to a corresponding input of buffer BUF
  • a data lme data in connects a corresponding output of acquisition block ACQ with a corresponding input of buffer BUF and provides data as it is generated m the acquisition block and for entering into buffer BUF
  • Acquisition block ACQ and address control block ADC are furthermore connected for providing several signals for address control block ADC as there are a frame start signal nxfr.
  • the address control block ADC is connected with buffer BUF and provides the buffer BUF with a control-in-signal ctrl in comp ⁇ smg three bits signalling ECC-. sector- and frame-start of incoming data via data lme data in. a buffer m address signal addr m for the m-going data, a buffer out address signal addr_out for outgomg data data out and an output operation enable signal out_en for readmg data data out from the buffer BUF to the not shown Reed Solomon decoder
  • the address control block ADC provides furthermore a signal RST RS that stops or resets the Reed Solomon decoder m case of illegal jumps
  • the buffer BUF provides a control-out-signal ctrl out comp ⁇ smg three bits signalling ECC-. sector- and frame-start of outgomg data data out provided for the Reed Solomon decoder
  • the acquisition block ACQ as shown m Fig 1 represents the acquisition part of the channel circuit called as channel IC that has to extract the data and several control signals for synchronization
  • this block decodes the data data_ ⁇ n. the byte clock byte clk. the frame address fr addr and sector number identified by sector identifier SLD
  • the data data_ ⁇ n. the byte clock byte clk. the frame address fr addr and sector number identified by sector identifier SLD In case of disorder in the frame numbers a fault- representmg - sequence is substituted like m the present version of the acquisition part A definite decoding of the sector identifier SID is classified by a valid sector identifier signal SID vahd equal to 1 - pulse independently of the frame address decoding This information is used to resynchronise the frame address to 0 even if the order was corrupted
  • the address control block ADC as shown in Fig 1 has to do the mam work Three stages are used for generatmg the addresses for the buffer BUF
  • the lrst Stage Generatmg the expected frame address fr addr and sector identifier SLD Following the synchronization signals from acquisition block ACQ the counters for the expected frame address fr addr and for the sector identifier SID are set m address control block ADC and m cases of defects mcremented mdependently on the current mput.
  • an internal expected ECC - counter is used, which m the ideal case should follow the mcommg data's ECC blocks This internal counter is mcremented or decremented when the sector number crosses 0 If the acquisition block ACQ provides only an incomplete frame address fr addr and a definite sector identifier SLD and no ECC number, the most hkeh change in the expected address is assumed when jumps occur If the full sector identifier SID is used the most significant bit can synchronise the ECC- counter too
  • the process has to be able to perfo ⁇ n a jump, to stop the input until an address is reached or to resynchromze the total process until a new ECC - block starts
  • 3rd Stage Generate the output address for readmg outgoing data data out from the buffer BUF into the not shown Reed-Solomon decoder
  • the output address corresponding to buffer out address signal addr out is set to 0. in these cases and when the distance between input address addr m and output address addr out is less than the default distance the output address addr out process waits until it is reached If due to lumps the mput address addr m advances increasing the distance to the output address the addr_out is generated with full output clock out clk speed until the default distance is reached agam
  • the buffer BUF as shown in Fig 1 is a RAM of the specified size with dual ports so it can be asynchronously wntten and read or is alternatively constructed with one 10 - port and a control logic preventing comcident m- and out-requests, this is necessary because the two clocks - clock byte clk and clock out clk - are completely independent from each other Both, input and output, can be disabled to make the clock handling easier.
  • the sync - data are acquired in acquisition block ACQ and transferred to address control block ADC they must be transferred to the Reed Solomon block and the following RAM address generator block, therefore they must also be stored and sent synchronously with the outgoing data data_out
  • the generator clk gen is the generator of the mdependent clock out clk for the outgoing data data out. which must have a higher frequency than the maximum frequency of the incoming data, I e the clock byte clk
  • the generation of independent clock out clk can be done by dividing the system clock used m the realization by a proper factor
  • Figure 2 and 3 illustrate the situation of a requested forward jump FWDJ under the circumstance that a buffer-m-address addr in is higher than the buffer-out-address addr_out as shown m Figure 2 and under the circumstance that a buffer-m-address addr in is lower than the buffer-out- address addr_out as shown in Figure 3
  • the requested first jump 3 will target to an area, which will not hurt the above-mentioned integ ⁇ ty of the stored data m contrast to a second jump 4 which is longer than the first one
  • the latter case will therefore not be performed but the output must be accelerated until the next requested address is out of the forbidden range 6 or the complete ECC - block must be dropped
  • the decision depends on the progress in completmg the ECC - block and on the jump distance
  • Figure 4 and 5 show the configuration of backward jump BKWJ requests under the circumstance that an buffer-in-address addr m is higher than the buffer-out-address addr out as shown in Figure 4 and under the circumstance that an buffer-in-address addr in is lower than the buffer- out-address addr_out as shown m Figure 5
  • the shorter first jump 3 points to the allowed range and can continue the input but must stop the output until the distance between mput- and output-address is the nominal distance
  • the requested next mput address of the buffer-in-address signal addr m points to an area that is not yet sent out from the buffer BUF.
  • Figure 6 illustrates the behaviour of the embodiment for several jumps in the input and the behaviour of the output addresses It demonstrates that most of the jumps are smoothed out
  • Figure 6 shows an address range AR of the buffer BUF over a time axis t
  • the input address of the buffer in address signal addr n causes an output address of the buffer out address signal addr out following m some distance in spite of jumps like JMP which is evidently smoothed
  • stop flag stop_flag is activated as shown m Fig 1 This is independent whether or not the currently read sectors have been completed or not The address - processes will be restarted completely in such a case and a signal RST RS is generated to reset the Reed Solomon operation
  • the buffer BUF is used simultaneousK as correction buffer for the first step of the Reed Solomon decoder
  • the only difference to the previously desc ⁇ bed embodiment is a more restricted range for jumps because one has to take into account that the smgle output address of the buffer-out-address signal addr_out of the first embodiment is split into three addresses dedicated to
  • inner and outer correction are related to the known correction modes mside a Reed Solomon decoder
  • the Reed - Solomon decoder will not get disordered ECC blocks by an intelligent buffer IBUF that leads to less necessary RAM and a high performance of the complete circuitry
  • the intelligent buffer IBUF accordmg to this embodiment is used as a first pass correction storage of the Reed Solomon decoder too
  • the method and arrangement descnbed here are given as examples only and a person skilled m the art may realise other embodiments of the invention while remaimng in the scope of the invention
  • the mtelligent buffer IBUF accordmg to the invention is particularly advantageous in that it may easily be used for va ⁇ ous kinds of error correction systems

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Signal Processing (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Multimedia (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

La présente invention concerne un procédé et un agencement pour la préparation de données destinées à un décodeur Reed-Solomon et, plus précisément, un procédé et un agencement pour un tampon intelligent (IBUF) placé avant un décodeur Reed-Solomon DVD sans RAM. L'invention concerne plus précisément un procédé et un agencement destinés à un tampon intelligent (IBUF) utilisés également en tant qu'unité de stockage de correction à premier passage des blocs de code correcteur d'erreur (ECC). De ce fait, le décodeur Reed-Solomon ne recevra pas de bloc ECC non ordonné grâce à un tampon intelligent (IBUF), nécessitant ainsi moins de RAM et conduisant à une meilleure performance du circuit complet. Le tampon intelligent (IBUF) est également utilisé en tant qu'unité de stockage de correction à premier passage du décodeur Reed-Solomon.
EP00987387A 1999-12-15 2000-12-12 Preparation de donnees destinees a un decodeur reed-solomon Ceased EP1256175A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP00987387A EP1256175A1 (fr) 1999-12-15 2000-12-12 Preparation de donnees destinees a un decodeur reed-solomon

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP99125014 1999-12-15
EP99125014 1999-12-15
EP00987387A EP1256175A1 (fr) 1999-12-15 2000-12-12 Preparation de donnees destinees a un decodeur reed-solomon
PCT/EP2000/012552 WO2001045271A1 (fr) 1999-12-15 2000-12-12 Preparation de donnees destinees a un decodeur reed-solomon

Publications (1)

Publication Number Publication Date
EP1256175A1 true EP1256175A1 (fr) 2002-11-13

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP00987387A Ceased EP1256175A1 (fr) 1999-12-15 2000-12-12 Preparation de donnees destinees a un decodeur reed-solomon

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Country Link
EP (1) EP1256175A1 (fr)
JP (1) JP2003517238A (fr)
KR (1) KR100754905B1 (fr)
CN (1) CN1233097C (fr)
AU (1) AU778986B2 (fr)
MX (1) MXPA02005110A (fr)
PL (1) PL355602A1 (fr)
WO (1) WO2001045271A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100920736B1 (ko) * 2002-10-08 2009-10-07 삼성전자주식회사 전송신호의 왜곡을 줄일 수 있는 단일반송파 전송시스템및 그 방법
CN101873143B (zh) * 2010-06-01 2013-03-27 福建新大陆电脑股份有限公司 一种rs纠错码解码器中的伴随式计算电路及其计算方法

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Publication number Priority date Publication date Assignee Title
US5610983A (en) * 1994-09-30 1997-03-11 Thomson Consumer Electronics, Inc. Apparatus for detecting a synchronization component in a satellite transmission system receiver
US5627935A (en) * 1994-11-11 1997-05-06 Samsung Electronics Co., Ltd. Error-correction-code coding & decoding procedures for the recording & reproduction of digital video data
KR0166268B1 (ko) * 1995-11-30 1999-03-20 배순훈 리드 솔로몬 복호기용 블록 동기신호 생성장치

Non-Patent Citations (1)

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Title
See references of WO0145271A1 *

Also Published As

Publication number Publication date
KR20020059777A (ko) 2002-07-13
AU778986B2 (en) 2004-12-23
CN1409896A (zh) 2003-04-09
AU2364801A (en) 2001-06-25
JP2003517238A (ja) 2003-05-20
KR100754905B1 (ko) 2007-09-04
CN1233097C (zh) 2005-12-21
MXPA02005110A (es) 2003-01-28
WO2001045271A1 (fr) 2001-06-21
PL355602A1 (en) 2004-05-04

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