EP1230683A4 - I2c opto-isolator circuit - Google Patents
I2c opto-isolator circuitInfo
- Publication number
- EP1230683A4 EP1230683A4 EP00992226A EP00992226A EP1230683A4 EP 1230683 A4 EP1230683 A4 EP 1230683A4 EP 00992226 A EP00992226 A EP 00992226A EP 00992226 A EP00992226 A EP 00992226A EP 1230683 A4 EP1230683 A4 EP 1230683A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- buffer
- opto
- output
- isolator
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/20—Repeater circuits; Relay circuits
- H04L25/26—Circuits with optical sensing means, i.e. using opto-couplers for isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/32—Non-reciprocal transmission devices
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/80—Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups H04B10/03 - H04B10/70, e.g. optical power feeding or optical transmission through water
- H04B10/801—Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups H04B10/03 - H04B10/70, e.g. optical power feeding or optical transmission through water using optical interconnects, e.g. light coupled isolators, circuit board interconnections
- H04B10/802—Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups H04B10/03 - H04B10/70, e.g. optical power feeding or optical transmission through water using optical interconnects, e.g. light coupled isolators, circuit board interconnections for isolation, e.g. using optocouplers
Definitions
- the present invention relates to circuits for providing electrical isolation and more particularly, to optical isolation circuits (hereinafter referred to as "opto- isolator” circuits), that are compatible with the Inter-Integrated Circuit (referred to hereinafter as "I2C”) communication protocol.
- the I2C bus is a bi-directional, two- wire communication architecture that was developed to provide communications among integrated circuit (“IC") devices, and is well known to those in the art.
- the I2C protocol is essentially a master/slave system, where a master station broadcasts a request for information, addressed to a particular slave, over a single physical wire.
- Slave stations continuously monitor the wire for such broadcasts directed to them; when a slave detects that it is being addressed, the slave responds to the request at a predetermined time after the master as finished transmitting. In this way, only one transmitter is using the wire at a time, all under the control and direction of the master station.
- the standard data rate is 100,000 bits per second, which can be escalated to 400,000 bits per second in the fast mode. There is no particular limit to the number of devices that can be connected to the I2C bus, as long as the maximum bus capacitance of 400 pF is not exceeded.
- FIG. 1 shows a battery monitoring application in which the I2C bus may be used.
- a large number of individual cell modules 20 e.g., 30 or more modules
- Each of the cell modules 20 includes a voltage cell 22, along with a power monitor module 24 associated with the cell 22.
- the cell includes a NiMH cell, although other technologies for generating voltage known to those in the art may also be used.
- the power monitor module 24 determines various parameters of the associated cell 22 and reports those parameters via an I2C bus 30.
- Each module provides a data input/output ("I/O") port 32, a clock I/O port 34, and a local ground 36.
- the data I/O 32 and the clock I/O 34 are referenced to the local ground 36.
- a large number of individual cell modules 20, all connected at different voltage levels provide information about the constituent cells.
- the cell modules 20 are stacked, i.e., connected in series, a differential voltage exists between the output signals of the modules.
- each cell 22 produces 10.8 NDC
- the battery 10 includes 30 such cells.
- the voltage differential between the cell module 20 at the top of the series and the cell module 20 at the bottom of the series is 324 volts.
- a battery monitor module 40 communicates with the individual modules 20 via an I2C bus 42.
- the data 32 and clock 34 outputs cannot be commonly connected. Accordingly, the data 32 and clock 34 outputs can only be tied to a common bus after they have been isolated from one another via an isolation device 50 as shown in FIG. 1.
- One prior art device used to provide isolation between circuits that operate at different voltage levels is an opto-isolator.
- prior-art opto- isolator circuits can not accommodate the unique characteristics of the I2C communications protocol.
- the opto-isolator circuit for providing isolation between a bidirectional, I2C transmission line and a pair of single-direction transmission lines.
- the opto-isolator circuit includes a bi-directional port for receiving data from, and providing data to, the bi-directional transmission line.
- the circuit further includes an output path that has (i) a first buffer for receiving outgoing data from the bidirectional port, (ii) a first opto-isolator for receiving the outgoing data from an output of the first buffer, and (iii) a second buffer for receiving the outgoing data from an output of the first opto-isolator and providing the outgoing data to an output port.
- the circuit also includes an input path, that has (i) a third buffer for receiving incoming data from an input port, (ii) a second opto-isolator for receiving the incoming data from an output of the third buffer, and (iii) a fourth buffer for receiving the incoming data from an output of the second opto-isolator.
- the fourth buffer provides the incoming data to the bi-directional port such that characteristics of the incoming data are compatible with I2C characteristics.
- the bi-directional port is at a voltage level corresponding to a logic high when a voltage level corresponding to a logic high is applied to the input port, and the bi-directional port is at a voltage level corresponding to a logic low when a voltage level corresponding to a logic low is applied to the input port.
- the output port is at a voltage level corresponding to a logic high when a voltage level corresponding to a logic high is applied to the bi-directional port, and the output port is at a voltage level corresponding to a logic low when a voltage level corresponding to a logic low is applied to the bi-directional port.
- the first buffer includes a tri-state buffer having (i) a high-impedance enable input electrically coupled to the bidirectional port, (ii) an output electrically coupled to the first opto-isolator, and (iii) an input electrically coupled to a reference voltage corresponding to a logic high state.
- the second buffer includes a tri-state buffer constructed and arranged such that the output of the tri-state buffer is in a high- impedance state when the first opto-isolator presents a voltage corresponding to a logic high state to the input of the second buffer.
- the output of the tri-state buffer is at a voltage level corresponding to a logic low state when the first opto-isolator presents a high impedance state to the input of the second buffer, and the output of the tri-state buffer is electrically coupled to the output port.
- the third buffer includes a tri-state buffer having (i) a high-impedance enable input electrically coupled to the input port, (ii) an output electrically coupled to the second opto-isolator, and (iii) an input electrically coupled to a reference voltage corresponding to a logic high state.
- the fourth buffer includes a tri-state buffer constructed and arranged such that its output is at a voltage level corresponding to a logic high when the second opto-isolator presents a voltage corresponding to a logic high state to the input of the fourth buffer.
- the output of the tri-state buffer is at a voltage level corresponding to a logic low state when the first opto-isolator presents a high impedance state to the input of the fourth buffer, and the output of the tri-state buffer is electrically coupled to the bi-directional port.
- the invention includes a method of providing isolation between a bi-directional, I2C transmission line and a pair of single-direction transmission lines.
- the method includes providing a bi-directional port for receiving data from, and providing data to, the bi-directional transmission line.
- the method further includes providing an output path, including (i) a first buffer for receiving outgoing data from the bi-directional port, (ii) a first opto-isolator for receiving the outgoing data from an output of the first buffer, and (iii) a second buffer for receiving the outgoing data from an output of the first opto-isolator and providing the outgoing data to an output port.
- the method also includes providing an input path, including (i) a third buffer for receiving incoming data from an input port, (ii) a second opto- isolator for receiving the incoming data from an output of the third buffer, and (iii) a fourth buffer for receiving the incoming data from an output of the second opto- isolator.
- the fourth buffer provides the incoming data to the bi-directional port such that characteristics of the incoming data are compatible with I2C characteristics.
- FIG. 1 shows a battery monitoring application in which the I2C bus may be used
- FIG. 2 shows a block diagram view of one preferred embodiment of an I2C opto-isolator circuit according to the present invention
- FIG. 3 shows the distribution of opto-isolator circuits to clock and data lines for three different cells in the circuit of FIG. 2; and, FIG. 4 shows a schematic representation of one preferred embodiment of the opto-isolator circuit of FIG. 2.
- FIG. 2 shows a block diagram view of one preferred embodiment of an I2C opto-isolator circuit 100 according to the present invention.
- Each clock I/O 32 and data I/O 34 from the battery 10 is connected to a separate opto-isolator circuit.
- FIG. 3 shows the distribution of opto-isolator circuits 100 to clock and data lines for three different cells 20.
- the opto-isolator 100 includes a bi-directional port 102, an output port 104 and an input port 106.
- the opto-isolator 100 operates in one of three modes.
- the opto-isolator 100 receives an input signal at the bi-directional port 102, transmits the signal through the opto-isolator 100, and drives the signal out of the output port 104.
- the opto-isolator 100 receives an input signal at the input port 106, transmits the signal through the opto-isolator 100, and drives the signal out of the bi-directional port 102.
- the opto-isolator 102 is inactive, and all ports 102, 104 and 106 are in a predetermined inactive state. In one preferred embodiment, the predetermined inactive state is logic high.
- the signals driven in and out of the ports 102, 104 and 106 are digital logic signals, although in other embodiments the signals could be analog signals, or other forms of signals known in the art.
- a first buffer 108 receives a signal the bi-directional port 102 and drives it into a first opto-isolator 110.
- this first opto-isolator 108 is a light emitting diode ("LED") and phototransistor combination that is well known to those in the art.
- the LED transforms an electrical signal into a light signal, and transmits the light signal to the phototransistor.
- the phototransistor receives the light signal, transforms it back into an electrical signal, and provides the recovered electrical signal at an output of the opto-isolator.
- Such an opto-isolator thus provides isolation to the extent of the gap between the LED and the phototransistor.
- Other such devices that provide isolation by transforming an electrical signal to some other form and then back into an electrical signal again, or by another method of providing isolation known in the art, may also be used.
- One example of a commercially available opto- isolator such as the one described herein is a PS2501 manufactured by NEC.
- a second buffer 112 receives the output signal from the first opto-isolator 110 and drives the signal to the output port 104.
- a third buffer 114 receives a signal on the input port 106 and drives it into a second opto- isolator 116, which has similar characteristics to the first opto-isolator 110.
- a fourth buffer 118 receives the output signal from the second opto-isolator 116 and drives the signal to the bi-directional port 102.
- the opto-isolator circuit 100 When there is no input signal at either the bi-directional port 102 or the input port 106, the opto-isolator circuit 100 is operating in the third mode, also referred to herein as the "idle" mode.
- the opto-isolator circuit 100 detects the absence of an input signal at either the bi-directional port 102 or the input port 106, the opto- isolator circuit 100 drives the bi-directional port 102 and the output port 104 to a predetermined "idle" level.
- the idle level is a voltage level that corresponds to a logic high (depending upon the particular logic family being used), although other predetermined levels may also be used to represent an idle state.
- the first buffer 108 includes a driver circuit 202 with a tri- state output.
- the output of the driver circuit can therefore be either a logic high, a logic low, or a state of high-impedance.
- the input of the driver circuit 202 is electrically coupled to a reference voltage V CC1 that preferably corresponds to a logic high, and the output of the driver circuit 202 is electrically coupled to the anode 203 of an LED 204 in the opto-isolator 110.
- the high-impedance enable input 206 is electrically coupled to the bi-directional port 102.
- the cathode 205 of the LED 204 is electrically coupled to a terminal of a resistor 208.
- the other terminal of the resistor 208 is electrically coupled to local ground-1 ("LG1"), where "LG1" is defined as a reference voltage of zero volts with respect to V CC1 .
- the second buffer 112 includes a driver circuit 210 with a tri-state output, an NPN bipolar transistor 212, a pull-up resistor 214, and a pull-down resistor 216.
- the input of the driver 210 is electrically coupled to local ground (“LG"), where "LG” is defined as a reference voltage of zero volts with respect to the reference voltage V cc , and the output of the driver 210 is electrically coupled to the output port 104.
- the high-impedance enable 218 is electrically coupled to the collector of the transistor 212 and to a first terminal of the pull-up resistor 214.
- the second terminal of the pull-up resistor is electrically coupled to V cc .
- the base of the transistor 212 is electrically coupled to a first terminal of the pull-down resistor 216 and to a first terminal of a phototransistor 220 in the opto-isolator 110.
- a second terminal of the pull-down resistor 216 is electrically coupled to LG
- a second terminal of the phototransistor 220 is electrically coupled to V cc
- the emitter of the transistor 212 is electrically coupled to LG.
- the third buffer 114 includes a driver circuit 222 with a tri-state output.
- the input of the driver circuit 222 is electrically coupled to a reference voltage V cc that preferably corresponds to a logic high, and the output of the driver circuit 222 is electrically coupled to the anode 223 of an LED 224 in the opto-isolator 116.
- the high-impedance enable input 228 is electrically coupled to the input port 106.
- the cathode 225 of the LED 224 is electrically coupled to a terminal of a resistor 226.
- the other terminal of the resistor 226 is electrically coupled to LG.
- the fourth buffer 118 includes a driver circuit 230 with a tri-state output, an NPN bipolar transistor 232, a pull-up resistor 234, and a pull-down resistor 236.
- the input of the driver 230 is electrically coupled to LG1, and the output of the driver 230 is electrically coupled to the bi-directional port 102.
- the high-impedance enable 238 is electrically coupled to the collector of the transistor 232 and to a first terminal of the pull-up resistor 234.
- the second terminal of the pull-up resistor 234 is electrically coupled to V CC1 .
- the base of the transistor 232 is electrically coupled to a first terminal of the pull-down resistor 236 and to a first terminal of a phototransistor 240 in the opto-isolator 116.
- a second terminal of the pull-down resistor 236 is electrically coupled to LG1
- a second terminal of the phototransistor 240 is electrically coupled to V CC1
- the emitter of the transistor 212 is electrically coupled to LG1.
- a first terminal of a second pull-up resistor 242 is electrically coupled to the bi-directional port 102.
- a second terminal of the second pull up resistor 242 is electrically coupled to V c ⁇ .
- a logic low level causes a voltage drop across the pull-up resistor 242, and enables the high impedance state of the buffer 202. While in the high- impedance state, no current flows through the LED 204, and the phototransistor 220 remains off. While the phototransistor 220 remains off, the transistor 212 also remains off, resulting in a negligable voltage drop across the pull up resistor 214, which in turn keeps the high-impedance enable 218 of driver circuit 210 in the inactive state (logic high), enabling the driver 210.
- the enabled driver 210 drives the LG (logic low) at its input to the output port 104.
- a logic low at the bi-directional port 102 results in a logic low at the output port 104.
- a logic high level at bi-directional input 102 causes a negligible voltage drop across the pull-up resistor 242 and places the high-impedance enable 206 of the driver 202 in its inactive state, thus enabling the driver 202.
- the enabled driver 202 drives the VCC1 at its input to the anode 203 of the LED 204, thus forward biasing the LED 204 and causing it to emit light.
- the emitted light turns on the phototransistor 220, which turns on the transistor 212.
- the transistor 212 being on creates a voltage drop across the pull-up resistor 214 that is large enough to place the high-impedance enable 218 in the active state, placing the output of the driver 210 in the high-impedance state.
- a logic high at the input of the bidirectional port results in a high impedance state at the output port 104.
- An external pull-up resistor on the output port would thus produce a logic high.
- a logic low level enables the high impedance state of the buffer 222. While the buffer 222 is in the high-impedance state, no current flows through the LED 224, and the phototransistor 240 remains off.
- the transistor 232 While the phototransistor 240 remains off, the transistor 232 also remains off, resulting in a negligable voltage drop across the pull up resistor 234, which in turn keeps the high- impedance enable 238 of driver circuit 230 in the inactive state (logic high), enabling the driver 230.
- the enabled driver 230 drives the LG (logic low) at its input to the bidirectional port 102.
- a logic low at the input port 106 results in a logic low at the bi-directional port 102.
- a logic high level at the input port 106 places the high- impedance enable 206 of the driver 202 in the inactive state, thus enabling the driver 222.
- the enabled driver 222 drives the V CC] at its input to the anode 223 of the LED 224, thus forward biasing the LED 224 and causing it to emit light.
- the emitted light turns on the phototransistor 240, which turns on the transistor 232.
- the transistor 232 being on creates a voltage drop across the pull-up resistor 234 that is large enough to place the high-impedance enable 238 in the active state, placing the output of the driver 210 in the high-impedance state.
- the pull-up resistor 242 brings the high- impedance output of the driver 210 to a logic high state.
- a logic high at the input port 106 results in a logic high state at the bi-directional port 102.
- the third mode i.e., the idle state
- a logic high state is present at the bidirectional port 102 and the input port 106 (i.e., the idle state), indicative of no data at either port.
- a logic high at the bi-directional port results in a high-impedance state at the output port 104
- a logic high at the input port 106 results in a logic high at the bi-directional port 102.
- the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Optical Communication System (AREA)
- Dc Digital Transmission (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16231499P | 1999-10-28 | 1999-10-28 | |
US162314P | 1999-10-28 | ||
PCT/US2000/041694 WO2001039515A2 (en) | 1999-10-28 | 2000-10-27 | I2c opto-isolator circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1230683A2 EP1230683A2 (en) | 2002-08-14 |
EP1230683A4 true EP1230683A4 (en) | 2006-05-17 |
Family
ID=22585110
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP00992226A Withdrawn EP1230683A4 (en) | 1999-10-28 | 2000-10-27 | I2c opto-isolator circuit |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP1230683A4 (en) |
JP (1) | JP2003530685A (en) |
KR (1) | KR20020041463A (en) |
AU (1) | AU3967901A (en) |
MX (1) | MXPA02002773A (en) |
TW (1) | TW548998B (en) |
WO (1) | WO2001039515A2 (en) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100654763B1 (en) * | 2004-06-24 | 2006-12-08 | 공상혁 | Mouse pad for computer |
EP1815056B1 (en) * | 2004-11-10 | 2010-02-24 | Koninklijke Philips Electronics N.V. | Method of an device for performing bi-directional transmission using a single-wire |
CN101820314B (en) * | 2009-02-27 | 2013-07-10 | 深圳拓邦股份有限公司 | Single-line bidirectional communication optical coupling isolation circuit |
JP2011108036A (en) * | 2009-11-18 | 2011-06-02 | Panasonic Electric Works Co Ltd | Digital input circuit |
TWI419607B (en) * | 2010-06-14 | 2013-12-11 | E Sun Prec Ind Co Ltd | Signal transmission circuit |
US11539392B2 (en) | 2012-07-30 | 2022-12-27 | Photonic Systems, Inc. | Same-aperture any-frequency simultaneous transmit and receive communication system |
US9935680B2 (en) * | 2012-07-30 | 2018-04-03 | Photonic Systems, Inc. | Same-aperture any-frequency simultaneous transmit and receive communication system |
US10374656B2 (en) | 2012-07-30 | 2019-08-06 | Photonic Systems, Inc. | Same-aperture any-frequency simultaneous transmit and receive communication system |
US9966584B2 (en) | 2013-03-11 | 2018-05-08 | Atieva, Inc. | Bus bar for battery packs |
US9229889B2 (en) * | 2013-03-13 | 2016-01-05 | Atieva, Inc. | Dual voltage communication bus |
US9514086B2 (en) | 2013-03-13 | 2016-12-06 | Atieva, Inc. | Configuration switch for a broadcast bus |
US9946675B2 (en) | 2013-03-13 | 2018-04-17 | Atieva, Inc. | Fault-tolerant loop for a communication bus |
US10089274B2 (en) | 2013-03-13 | 2018-10-02 | Atieva, Inc. | Dual voltage communication bus |
US9041454B2 (en) | 2013-03-15 | 2015-05-26 | Atieva, Inc. | Bias circuit for a switched capacitor level shifter |
US9228869B2 (en) | 2013-09-26 | 2016-01-05 | Rosemount Inc. | Industrial process variable transmitter with isolated power scavenging intrinsically safe pulse output circuitry |
US9175993B2 (en) * | 2013-09-26 | 2015-11-03 | Rosemount Inc. | Industrial process field device with low power optical isolator |
US10075246B2 (en) | 2013-09-26 | 2018-09-11 | Micro Motion, Inc. | Optical isolator mounted in printed circuit board recess |
US10158432B2 (en) | 2015-10-22 | 2018-12-18 | Photonic Systems, Inc. | RF signal separation and suppression system and method |
US10623986B2 (en) | 2015-10-22 | 2020-04-14 | Photonic Systems, Inc. | RF signal separation and suppression system and method |
KR101945425B1 (en) * | 2015-11-27 | 2019-02-07 | 주식회사 엘지화학 | Apparatus for monitoring the status of battery pack in parallel |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4282604A (en) * | 1979-04-04 | 1981-08-04 | Jefferson William T | Optical isolation circuit for bidirectional communication lines |
FR2600476A1 (en) * | 1986-06-19 | 1987-12-24 | Hewlett Packard France Sa | Device for connection between a data network and a plurality of terminal clusters |
US5406091A (en) * | 1993-05-27 | 1995-04-11 | Ford Motor Company | Communication network optical isolation circuit |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5323014A (en) * | 1993-03-01 | 1994-06-21 | Aeg Transportation Systems, Inc. | Optocoupler built-in self test for applications requiring isolation |
US5438210A (en) * | 1993-10-22 | 1995-08-01 | Worley; Eugene R. | Optical isolation connections using integrated circuit techniques |
-
2000
- 2000-10-27 MX MXPA02002773A patent/MXPA02002773A/en unknown
- 2000-10-27 EP EP00992226A patent/EP1230683A4/en not_active Withdrawn
- 2000-10-27 AU AU39679/01A patent/AU3967901A/en not_active Abandoned
- 2000-10-27 JP JP2001540535A patent/JP2003530685A/en active Pending
- 2000-10-27 KR KR1020027004937A patent/KR20020041463A/en not_active Application Discontinuation
- 2000-10-27 WO PCT/US2000/041694 patent/WO2001039515A2/en not_active Application Discontinuation
- 2000-10-30 TW TW089122848A patent/TW548998B/en active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4282604A (en) * | 1979-04-04 | 1981-08-04 | Jefferson William T | Optical isolation circuit for bidirectional communication lines |
FR2600476A1 (en) * | 1986-06-19 | 1987-12-24 | Hewlett Packard France Sa | Device for connection between a data network and a plurality of terminal clusters |
US5406091A (en) * | 1993-05-27 | 1995-04-11 | Ford Motor Company | Communication network optical isolation circuit |
Non-Patent Citations (3)
Title |
---|
KUHNKE F K: "BIDIRECTIONAL I2C BUS ISOLATOR", ELECTRONICS WORLD, NEXUS MEDIA COMMUNICATIONS, SWANLEY, KENT, GB, vol. 100, no. 1704, 1 November 1994 (1994-11-01), pages 920, XP000477703, ISSN: 0959-8332 * |
WIEMANN: "Bussysteme", BUSSYSTEME, 1984, pages 102 - 102, XP002260915 * |
XIA Y: "OPTICALLY ISOLATED I2C INTERFACE", ELECTRONICS WORLD, NEXUS MEDIA COMMUNICATIONS, SWANLEY, KENT, GB, vol. 104, no. 1752, December 1998 (1998-12-01), pages 1018, XP000880680, ISSN: 0959-8332 * |
Also Published As
Publication number | Publication date |
---|---|
JP2003530685A (en) | 2003-10-14 |
WO2001039515A2 (en) | 2001-05-31 |
MXPA02002773A (en) | 2003-01-28 |
EP1230683A2 (en) | 2002-08-14 |
WO2001039515A3 (en) | 2001-10-25 |
KR20020041463A (en) | 2002-06-01 |
AU3967901A (en) | 2001-06-04 |
TW548998B (en) | 2003-08-21 |
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Legal Events
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