EP1228601A1 - Systeme de remplacement de cable sans fil - Google Patents

Systeme de remplacement de cable sans fil

Info

Publication number
EP1228601A1
EP1228601A1 EP00976936A EP00976936A EP1228601A1 EP 1228601 A1 EP1228601 A1 EP 1228601A1 EP 00976936 A EP00976936 A EP 00976936A EP 00976936 A EP00976936 A EP 00976936A EP 1228601 A1 EP1228601 A1 EP 1228601A1
Authority
EP
European Patent Office
Prior art keywords
wireless transceiver
interface
adapter
network
communication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00976936A
Other languages
German (de)
English (en)
Inventor
Alan Mikhak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of EP1228601A1 publication Critical patent/EP1228601A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/72—Mobile telephones; Cordless telephones, i.e. devices for establishing wireless links to base stations without route selection
    • H04M1/725—Cordless telephones
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H21/00—Adaptive networks
    • H03H21/0001—Analogue adaptive filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H21/00—Adaptive networks
    • H03H21/0012—Digital adaptive filters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/253—Telephone sets using digital voice transmission
    • H04M1/2535—Telephone sets using digital voice transmission adapted for voice communication over an Internet Protocol [IP] network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M2250/00—Details of telephonic subscriber devices
    • H04M2250/02—Details of telephonic subscriber devices including a Bluetooth interface
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W4/00—Services specially adapted for wireless communication networks; Facilities therefor
    • H04W4/18—Information format or content conversion, e.g. adaptation by the network of the transmitted or received information for the purpose of wireless delivery to users or terminals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W84/00—Network topologies
    • H04W84/02—Hierarchically pre-organised networks, e.g. paging networks, cellular networks, WLAN [Wireless Local Area Network] or WLL [Wireless Local Loop]
    • H04W84/10—Small scale networks; Flat hierarchical networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W84/00—Network topologies
    • H04W84/18—Self-organising networks, e.g. ad-hoc networks or sensor networks

Definitions

  • a local-area network is a group of computing and telecommunications devices which are interconnected through a physical medium to facilitate the sharing of applications, data and peripherals.
  • Local-area networks are generally confined to a single building.
  • Ethernet is an exemplary local-area network which has enjoyed considerable success in the office environment.
  • an Ethernet typically includes a local backbone with any number of access points to connect the
  • a personal area network includes a device having a first wireless transceiver, and an adapter having a second wireless transceiver in communication r, with the first wireless transceiver, and a plug capable of mating to a jack coupled to a local backbone.
  • a method of communication includes exchanging information over a wireless medium between a device and an adapter having a plug mated to a jack coupled to a local backbone, and communicating at least a portion of the rye information between the adapter and the local backbone.
  • a personal area network includes a device having a first complementary metal-oxide semiconductor (CMOS) wireless transceiver, and an adapter having a second CMOS wireless transceiver in communication with the first CMOS wireless transceiver, and an interface to interface the second CMOS wireless transceiver to the o local backbone.
  • CMOS complementary metal-oxide semiconductor
  • a wall dongle in still another aspect of the present invention, includes a plug capable of mating to a jack coupled to a local backbone, an interface coupled to the plug, and a wireless transceiver coupled to the interface.
  • -, _- communication medium to a local backbone includes using a wall dongle to exchange information with an external device over a wireless medium, the wall dongle having an adapter 1 plugged into a jack coupled to a local backbone, and communicating at least a portion of the information between the wall dongle adapter and the local backbone.
  • a device dongle includes a plug capable
  • ⁇ - of mating to a jack coupled to a device an interface coupled to the plug, and a wireless transceiver coupled to the interface.
  • a method of interfacing a wireless communication medium to a device includes using a device dongle to exchange information with an external device over a wireless medium, the device dongle having an adapter plugged into a
  • n jack coupled to the device, and communicating at least a portion of the information between the device dongle and the device.
  • a communications network includes a device having a first wireless transceiver, a second wireless transceiver in communication with the first wireless transceiver, a local backbone coupled to the second wireless transceiver, and an Internet
  • gateway coupled to the local backbone.
  • a communications network includes a plurality of devices each having a wireless transceiver, a local backbone, an access point to the local backbone, the access point having an access wireless transceiver in communication with the wireless transceiver for each of the devices, and an Internet gateway coupled to the local
  • a method of communication includes exchanging information over a wireless medium between a device and an access point to a local backbone, communicating at least a portion of the information between the access point and the local backbone, and coupling the communicated information between the local backbone and an
  • FIG. 1 is a block diagram of a cable replacement system utilized in a LAN and coupled to an Internet via a gateway;
  • FIG. 2 is a block diagram of an exemplary embodiment of a DOCSIS compliant cable modem utilized as a residential gateway;
  • FIG. 3 presents a data flow diagram that describes the flow of transport packets in the residential gateway
  • FIG. 4 is a block diagram of an adapter embodiment that interfaces with the exemplary cable modem MAC via the gateway bus;
  • FIG. 5 is a block diagram of a transceiver and network interface;
  • FIG. 6 is a block diagram of a transceiver in accordance with an exemplary embodiment of the present invention.
  • FIG. 7 is a block diagram of the transceiver blocks including a receiver, transmitter and local oscillator in accordance with an exemplary embodiment of the present invention
  • FIG. 8 is a block diagram of a wall dongle
  • FIG. 9 is a block diagram of a device dongle.
  • FIG. 10 is a representation of the physical construction of a dongle.
  • a wireless cable replacement system is typically utilized in a networked environment.
  • the cable replacement system allows wiring to be replaced with more flexible connectivity as c supplied via one or more wireless links.
  • a typical environment where a wireless cable replacement system would be utilized includes a home network, or a local area network (LAN).
  • Home networks are typically utilized to allow appliances, computers, telephones, televisions and other devices equipped with suitable interfaces to communicate throughout the home and to an external Internet.
  • a LAN typically interconnects, or networks, business equipment such as faxes, ⁇ ⁇ telephones, and computers together and to an external Internet.
  • Typical communications protocols include HPNA in a home enviornment and ethernet in a business enviornment.
  • the gateway provides signal processing to allow data from the various devices coupled to a backbone to be packetized in a suitable format for transmission over an Intranet and/or an
  • DSP digital signal processing
  • a gateway provides an interface in the architecture of a packetized data transmission
  • a wireless cable replacement is applicable to any type of network separated by one or more gateways, including residential gateways or other types of gateways known to those skilled in the art.
  • a residential gateway is typically a gateway that is suitable for use in interfacing a home or office network typically utilizing telephone circuits for Intranet interconnections to an Intranet, typically utilizing
  • ⁇ r a cable television (CATV) network, or public switched telephone network (PSTN) via a digital subscriber line (DSL) to access an Internet.
  • CATV cable television
  • PSTN public switched telephone network
  • DSL digital subscriber line
  • DSP techniques are utilized to allow multiple channel of data supplied by differing devices such as computers, appliances and telephones present on the Internet to be individually packetized and transfened between networks such as
  • -, _• accommodates the characteristics of the wired network coupled to is typically present in the hardware and software of the particular gateway.
  • Gateway functions including residential gateway functions, are provided in a variety of hardware configurations including a personal computer, a set top box or the exemplary set top box that is described in the following paragraphs.
  • FIG. 1 is a block diagram of a cable replacement system utilized in a LAN 102 and coupled to an Internet 1 16 via a gateway 1 12.
  • An embodiment of the present invention is directed to a system and technique to deliver services in the home using existing wire pairs, and wireless cable replacement systems already installed in the home all while not disrupting existing services provided on the existing wire pair.
  • a series of adaptors 101 are provided to establish a wireless link through a wireless medium such as RF or infrared 108.
  • Adaptors present in the client devices 132, and coupled to a local backbone 1 10 make up a portion of the wireless cable replacement system.
  • the local backbone includes all of the wiring interconnecting the individual client devices 132 to a main wiring bus emanating from the residential gateway.
  • an adaptor is shown as part of the residential gateway 1 12. This embodiment couples signals from the bus of a cable modem MAC (not shown) included in the residential gateway to the adaptor.
  • a residential gateway may be installed at a location inside or outside the home.
  • the residential gateway accepts inputs from an IP network on one side that is capable of delivering IP (Internet Protocol) services to the home.
  • IP Internet Protocol
  • the other side of the residential gateway 10 can be the interface to the in home wiring that previously delivered POTS.
  • the exemplary embodiment shown in FIG. 1 has two wire pairs, one pair continues to deliver POTS the other wire pair delivers POTS and other services to a local area network (LAN).
  • LAN local area network
  • the residential gateway provides a means to convert the physical media and protocols , - used for the IP network to the physical media and protocols (typically HomePNA) used on the in home wire pairs.
  • the in home wire pairs that couple client devices 132 to the residential gateway 1 12 are termed a local backbone 110.
  • the residential gateway provides a means to convert the physical media and protocols used for the IP network to the physical media and protocols used on the LAN backbone (typically Ethernet, ADSL and
  • DOCSIS Data Over Cable Service Interface
  • IP network is used for delivery of IP services over the IP network (an HFC network coupled to a CATV network).
  • IP network an HFC network coupled to a CATV network.
  • the residential gateway includes a cable modem.
  • a modem may be provided that is coupled to the PSTN via digital subscriber line technology.
  • the described exemplary embodiment uses two well-known protocols for delivery of in home services.
  • the first protocol is a base band protocol to deliver POTS. This protocol is described by Bellcore (now Telcordia) in TR-NWT-000057.
  • the second protocol is HomePNA (Home Phoneline Network Alliance) as described in the Version 2.0 specification.
  • the function of the residential gateway can be divided into three components along service delivery lines.
  • the first is delivery of broadband data services.
  • This function is the primary function of the cable modem as described by the CableLabs DOCSIS specification.
  • Data service is delivered using Ethernet as specified by CableLabs in the DOCSIS specification, and alternatively by HPNA.
  • the second function is the POTS interface.
  • the gateway contains the high voltage circuits and the processing elements necessary to convert packetized voice delivered over IP streams to
  • the third function is a proxy for the voice over HPNA phones 103 connected to the HPNA network 102.
  • the Proxy performs an interface conversion function at two levels, first is a transport packet conversion and the second is the signaling protocol conversion. . - Two POTS phones are shown 102. Both of these are traditional telephones connected to the residential gateway for telephone service. As described above, for installations where only a single wire pair is available in the home as a local backbone, only one phone line is used, that would be the phone attached to the HomePNA network. Not shown in this drawing is the possibility of bridging additional POTS telephones on the wire pair, or local backbone 1 10. In 7f) this system, these bridged phones will behave as a bridged phone on a traditional POTS line. All bridged telephones are assigned to the same phone number and the ring/dial tone behavior is as described in TR-NWT-000057.
  • Home appliance control is represented by an appliance block 106.
  • the concept here is to allow appliance controllers on the network to access control information for connected client ⁇ t - devices 132.
  • a connected personal computer 104 might control the start time for an appliance 106, such as a coffee maker.
  • Another possible client device 132 is a connected printer device. This can be any type of computer peripheral that permits resource sharing from any of multiple personal computers or other control devices connected to the HomePNA network.
  • the HomePNA phone 103 shown is a telephone that integrates the function of the
  • An additional appliance 106 that may be connected to the HomePNA network is a television. This can be used to display television programming streamed from the external IP network or spooled from memory systems of an attached video server. This video server could be a dedicated device for this purpose or specialized programming on one of the attached personal computers.
  • a cable modem provides an access point for a home network or Intranet to an Internet via a CATV connection.
  • a DSL capable modem supplies the capabilities for coupling a home network, or Intranet to an Internet via a DSL line and the PSTN.
  • a cable modem utilized as a gateway processes packetized data for transmittal over the CATV network in compliance with a transmission standard known as DOCSIS.
  • FIG. 2 is a block diagram of an exemplary embodiment of a DOCSIS compliant cable
  • the gateway includes adaptor circuitry 101 that is coupled to the cable modem MAC 1 112.
  • the described exemplary embodiment may provide a highly integrated solution implemented single chip that is compliant with the (DOCSIS).
  • DOCSIS was developed to ensure that cable modem equipment built by a variety of manufacturers is compatible, as is the case with traditional dial-up modems.
  • the described Q exemplary embodiment can provide integrated functions for communicating with the CMTS.
  • a QPSK upstream modulator 1 102 transmits data to the far end data terminating device
  • a QAM downstream demodulator 1100 receives data from the far end data terminating device via a CMTS
  • a QPSK out of band downstream demodulator 1106 receives out of band MPEG-2 encoded messages from the CMTS.
  • a universal serial bus transceiver 1104 provides transparent bi-directional IP traffic between devices operating on a USB such as for example a PC workstation, server printer or other similar devices and the far end data terminating device.
  • a voice and data processor 1 160 is used for processing and exchanging voice, as well as fax and modem data between packet based networks and telephony devices.
  • the QAM downstream demodulator 1 100 may utilize either 64 QAM or 256 QAM in the
  • 1 100 accepts an analog signal centered at the standard television IF frequencies, amplifies and digitizes the signal with an integrated programable gain amplifier and A/D converter.
  • the 1 digitized signal is demodulated with recovered clock and canier timing.
  • Matched filters and then adaptive filters remove multi-path propagation effects and nanowband co-channel interference.
  • Soft decisions are then passed off to an ITU-T J.83 Annex A/B/C compatible c decoder.
  • the integrated decoder performs enor conection and forwards the processed received data, in either parallel or serial MPEG-2 format to a DOCSIS Media Access Controller (MAC) 11 12.
  • MAC DOCSIS Media Access Controller
  • the output of the downstream demodulator 1 100 is coupled to the DOCSIS MAC 1 1 12.
  • the DOCSIS MAC 1 1 12 may include baseline privacy encryption and decryption as well as
  • the DOCSIS MAC 1 1 12 implements the downstream portions of the DOCSIS protocol.
  • the DOCSIS MAC 1 1 12 extracts DOCSIS MAC frames from MPEG-2 frames, processes MAC headers, and filters and processes messages and data.
  • Downstream data packets and message packets may be then placed in system memory
  • the SDRAM interface 1 1 16 preferably interfaces to a number of off the shelf SDRAMs which are provided to support the high bandwidth requirements of the Ethernet MAC 1112 and other peripherals.
  • the SDRAM interface 1 1 16 may support multiple combinations of 8, 1 16 or 32 bit wide SDRAMs, allowing for external data storage in the range of about 2 to 32 MBytes.
  • the DOCSIS MAC 1 1 12 includes
  • DMA direct memory access
  • the upstream modulator 1102 provides an interface with the CMTS.
  • the upstream modulator 1 102 may be configured to operate with numerous modulation schemes including QPSK and 16-QAM.
  • the upstream modulator 1102 supports bursts or continuous data, provides
  • FEC forward enor conection
  • the DOCSIS MAC 1 1 12 can also implement the upstream portions of the DOCSIS protocol before transmission by the upstream modulator 1102.
  • the DOCSIS MAC 1 1 12 receives data from one of the DMA channels, requests bandwidth and frames the data for TDMA with other modems on the same upstream frequency.
  • the DOCSIS MAC interfaces with the MIPS core 1 128 via the ISB 11 18.
  • An exemplary embodiment of the MIPS core 1 128 includes a high performance CPU operating at a speed of at least 80 MHZ with 32-bit address and data paths.
  • the MIPS core includes two way set associative instruction and data caches on the order of about 4kbytes each.
  • the upstream modulator 1 102 and the downstream demodulator 1 100 are controlled by the MIPS core 1 128 via a serial interface which is compatible with a subset of the Motorola M-Bus and the Philips I2C bus.
  • the interface consists of two signals, serial data (SDA) and serial clock (SCL), which may control a plurality of devices on a common bus. The addressing of the different devices may be accomplished in accordance with an established protocol on the two wire interface.
  • the described exemplary embodiment of the network gateway includes a full-speed universal serial bus (USB) transceiver 1 104 and USB MAC 1 122 which is compliant with the
  • the USB MAC 1122 provide concunent operation of control, bulk, isochronous and interrupt endpoints.
  • the USB MAC 1122 also can support standard USB commands as well as class/vendor specific commands.
  • the USB MAC 1 122 include integrated RAM which allows flexible configuration of the device. Two way communication of information to a device operating on a USB can be provided, such as for example a PC on a USB
  • the USB MAC 1 122 can be ananged for hardware fragmentation of higher layer packets from USB packets with automatic generation and detection of zero length USB packets.
  • the USB MAC 1 122 may include DMA channels which are used to communicate received data to the system memory 1 1 14 via the internal system bus 1 1 18. Data stored in system memory 11 14 may then be processed and communicated to the cable modem termination
  • USB packets may then be communicated to the external device
  • USB transceiver 1 104 operating on the USB via the USB transceiver 1 104.
  • a media independent interface (Mil) 11 10 can provide bi-directional communication with devices such as for example a personal computer (PC) operating on an Ethernet.
  • the media independent interface 1 1 10 can forward data to and receive information from the Ethernet MAC 1 134.
  • the Ethernet MAC 1 134 can also perform all the physical layer interface (PHY) functions
  • the Ethernet MAC 1 134 can also decode the received data in accordance with a variety of standards such as for example 4B5b, MLT3. and Manchester decoding.
  • the Ethernet MAC can perform clock and data recovery, stream cipher de-scrambling, and digital adaptive equalization.
  • the Ethernet MAC 1 134 may include DMA channels which are used for fast data
  • Processed data stored in system memory 1 1 14 may then be communicated to the cable modem termination system(not shown) via the upstream modulator 1 102.
  • data received from 1 the cable modem termination system is processed by the downstream demodulator 1100 and stored in system memory as higher layer packets which can then be retrieved by the Ethernet
  • the Ethernet MAC 1134 may also perform additional management functions such as link integrity monitoring, etc.
  • the described exemplary embodiment of the gateway includes a 16-bit external bus interface (EBI) 1140 that supports connection to flash memories 1142, external SRAM 1144 or EPROMS 1144. Additionally, the EBI 1140 may be
  • n used to interface the described exemplary network gateway with additional external peripherals.
  • the EBI 1140 can provide a 24 b : .t address bus and a 16-bit bi-directional data bus. Separate read and write strobes can be provided along with multiple firmware configurable chip select signals. Each chip select can be fully programmable, supporting block sizes between about 4 K-bytes and 8 M-bytes, extended clock cycle access control and 8 or 16-bit selection of peripheral data bus
  • the EBI 1140 can support both synchronous and asynchronous transfers. Pseudonymous transfers may be supported through the use of read/write strobes to indicate the start and duration of a transfer.
  • the EBI 1140 can include DMA access capability to or from the SDRAM interface 1116. The DMA operation may take one or more forms. For example, in EBI mode, an EBI bridge can act as the DMA controller, and perform
  • an external device can act as the DMA controller and the EBI 1 140 can serve as a simple bridge.
  • the MIPS core 1128 can be responsible for DMA setup.
  • the network gateway may be vulnerable to network breaches due to peripheral devices such as PC employing windows or network Macintosh computers. These operating systems
  • the exemplary embodiment of the gateway includes IP security module 1148 which interfaces with ISB 1118.
  • the MIPS corel 128 can set-up and maintain all security associations.
  • the MIPS corel 128 can also filter all IP traffic and route any messages requiring security processing to the security module via the ISB 1118.
  • the security module 150 may support single DES (CBC and ECB modes) triple DES (CBC and ECB modes) MD-5 and SHA authentication in hardware to provide support for virtual private networks.
  • the security module 1148 can implement the basic building blocks of the developing IP Security Standard (IPsec).
  • IPsec IP Security Standard
  • the security module 1148 may also be used to implement any other IP Security Standard
  • IPsec IP Encapsulating Security Pay load
  • ESP IP Encapsulating Security Pay load
  • AH IP Authentication Header
  • Both protocols may be used to provide access based on the distribution of cryptographic keys and the management of traffic flows.
  • the protocols may be used alone or in combination to satisfy the security requirements of a particular system.
  • the security module 1 148 can support multiple modes of operation depending on a security association to the traffic canied by a simplex connection. For example, transport mode security association between two hosts, primarily protects protocols above the IP layer while
  • tunnel mode security association provides security and control to a tunnel of IP packets.
  • the exemplary security module 1 148 addresses possible differences in packet format between IPsec and future security applications with a generalized scheme to determine where the authentication / encryption algorithms are applied with a data packet.
  • the authentication / encryption algorithms consider each packet to consists of three parts, a header, body and trailer.
  • the security module 1 148 can add and initialize any necessary headers, determine necessary parameters, generate the associated control message and add the control and data message.
  • the control fields of the received data In an encryption mode, the control fields of the received data
  • the exemplary embodiment of the network gateway includes a DMA controller 1150 having a number of channels that enable direct access over the ISB 1118 between peripherals and the system memory 1 1 14. With the exception of the security module 1 148, packets received by the DMA controller 1150 having a number of channels that enable direct access over the ISB 1118 between peripherals and the system memory 1 1 14. With the exception of the security module 1 148, packets received by the DMA controller 1150 having a number of channels that enable direct access over the ISB 1118 between peripherals and the system memory 1 1 14. With the exception of the security module 1 148, packets received by the security module 1 148.
  • the network gateway 98 cause DMA transfers from a peripheral to memory, which is refened to as a receive operation.
  • a DMA transfer from memory to a peripheral is refened to as a transmit operation.
  • Programmable features in each channel can allow DMA controller 1 150 to manage maximum ISB burst lengths for each channel, enable interrupts, halt operation in each channel, and save power when certain modules are not operational.
  • the maximum ISB burst length may n be programmed independently for each channel preferably up to 64 32 bit words.
  • Each channel can include maskable interrupts connected to the MIPS core 1128 which indicate buffer complete, packet complete and or invalid descriptor detected. Busy DMA channels may be stalled or completely disabled by the MIPS corel 128.
  • Source clocks (not shown) for each channel are can be connected to the channels based on the internal peripheral they service. For
  • these clocks may be turned off and on coincident with the respective peripheral's clock.
  • the DMA controller 1150 can be operable in both non-chaining and chaining mode.
  • the DMA channel refers to its internal registers for the pertinent information related to a scheduled DMA burst transfer.
  • the DMA controller can set-up the
  • the DMA channels can send the specified number of bytes (preferably up to 4095) from the specified byte address.
  • the DMA channels can insert data into a specified memory location until a buffer has been completely filled or the end of a packet is detected.
  • the system memory can be partitioned, preferably using descriptor rings containing pointers to memory buffers as well as status information for each memory buffer.
  • the MIPS corel 128 can write the descriptor pointers while the DMA controller 1150 follows by inserting/taking data into/from the location designated by the descriptor. Upon completion of the transfer of a buffer, the DMA controller 1150 effectively clears the descriptor
  • the MIPS core 1128 can fill or recognize a data block for a particular DMA channel, then write the next unused descriptor in the ring indicating that the
  • the DMA controller 1150 can follow the DSP write to the descriptor ring, sending out data and clearing the descriptor when the transfer is complete.
  • the DMA controller 1150 reads a descriptor that does not contain valid data, it can go idle until initiated by the DSP core.
  • the MIPS corel 128, can allocates memory space for incoming
  • the DMA controller 1150 read the base address and insert data until either the buffer is full or an end of packet has been detected.
  • the DMA controller 1 150 can update the descriptor, communicating to the MIPS corel 128 that the block is full , indicating the length of the data on the block, and/or asserted first and or last buffer flags.
  • the described exemplary network gateway can include a voice processor 1160 for processing and transporting voice over packet based networks such as PCs running network on a USB (Universal Serial Bus) or an asynchronous serial interface, Local Area Networks (LAN) such as Ethernet, Wide Area Networks (WAN) such as Internet Protocol (IP), Frame Relay (FR), Asynchronous Transfer Mode (ATM), Public Digital Cellular Network such as TDMA (IS- 13x),
  • a voice processor 1160 for processing and transporting voice over packet based networks such as PCs running network on a USB (Universal Serial Bus) or an asynchronous serial interface, Local Area Networks (LAN) such as Ethernet, Wide Area Networks (WAN) such as Internet Protocol (IP), Frame Relay (FR), Asynchronous Transfer Mode (ATM), Public Digital Cellular Network such as TDMA (IS- 13x),
  • IP Internet Protocol
  • FR Frame Relay
  • ATM Asynchronous Transfer Mode
  • TDMA IS- 13x
  • the described embodiment of the voice processor 1160 also supports the exchange of voice, as well as fax and modem, between a traditional circuit switched network or any number of 1 telephony devices and the CMTS (not shown).
  • the voice processor may be implemented with a variety of technologies including, by way of example, embedded communications software that enables transmission of voice over packet based networks.
  • the described exemplary embodiment of the cable modem acting as a network gateway includes integrated peripherals including independent periodic interval timers 1180, a dual universal asynchronous receiver-transmitter (UART) 1182 that handles asynchronous serial communication, a number of internal intenupt sources 1184, and a GPIO module 1186 that provides multiple individually configurable input/output ports.
  • integrated peripherals including independent periodic interval timers 1180, a dual universal asynchronous receiver-transmitter (UART) 1182 that handles asynchronous serial communication, a number of internal intenupt sources 1184, and a GPIO module 1186 that provides multiple individually configurable input/output ports.
  • UART universal asynchronous receiver-transmitter
  • n can be provided to drive various light emitting diodes (LEDs) and to control a number of external
  • a peripheral bus bridge 1186 can be used to interface the low speed peripheral to the internal system bus 1 1 18.
  • the described exemplary embodiment also includes an HPNA MAC (not shown) which provides an interface between the HomePNA network and the MIPS processor.
  • FIG. 3 presents a data flow diagram that describes the flow of transport packets in the residential gateway previously described.
  • the DOCSIS Interface is the primary interface to the
  • DOCSIS network within the residential gateway. All packets that anive to or leave from the residential gateway via the DOCSIS network must go through the DOCSIS interface block. As shown all packets aniving from the DOCSIS network go through the DOCSIS interface block and are delivered to the packet based network filter.
  • the DOCSIS interface block translates the packet format as represented in the DOCSIS network to an internal format that is used for all
  • the DOCSIS packet filter accepts packets from the DOCSIS interface and makes a routing decision based on the destination address within the packet.
  • the destination of the packet will be one of three possibilities: (1) VoIP Packets for the proxy gateway, (2) VoIP packets for the telephony interface controller or (3) data packets delivered directly to the packet based network
  • the packet based network interface is the primary interface to the packet based network within the residential gateway. All packets that anive to or leave from the residential gateway via the packet based network must go through the packet based network interface block. As shown all packets aniving from the packet based network go through the packet based network interface
  • the packet based network interface block translates the packet format as represented in the packet based network to an internal format that is used for all packet filter and routing functions within the residential gateway.
  • the packet based network filter accepts packets from the packet based network interface and makes a routing decision based on the destination address within the packet.
  • the destination of the packet will typically be one of two possibilities: (1) VoHN packets for the proxy gateway,
  • the proxy gateway performs a translation function between the packets in the VoHN format to packets in the VoIP format.
  • the specific translation is direction dependent.
  • Packets aniving from the packet based network filter are translated to a VoIP format and delivered to the DOCSIS interface.
  • Packets aniving from the DOCSIS packet filter are translated to a VoHN
  • a home network typically utilizes telephone wiring and connecting jacks typically found in a home.
  • the cable replacement system typically replaces a telephone line that would be utilized to couple a client device to the telephone wall jack.
  • Ethernet cabling and interfaces provide the network protocols
  • the wireless cable replacement system utilizes dongles, devices that provide half of the wireless cable replacement function, to establish a series of wireless links.
  • a wall dongle couples to, or is integral with a telephone wall jack.
  • the wall dongle is in communication via a wireless link to a device dongle that is coupled to a data IO port
  • a Bluetooth transceiver provides the wireless coupling between dongles.
  • a Bluetooth transceiver provides a robust wireless link between dongles that is typically immune to jammers and other interference.
  • transceivers built to accommodate other types of wireless transmission standards will provide equivalent functionality.
  • FIG. 4 is a block diagram of an adaptor embodiment that interfaces with the exemplary cable modem MAC via a gateway bus.
  • the cable modem MAC bus 1 1 18 is coupled to a device dongle 136 via connector 129.
  • Device dongle 136 includes a connector 129 coupling signals to an adaptor 101.
  • n adaptor 101 includes a network interface 122 coupled to a transceiver 124 and are both disposed onasubstrate 142. Wireless signals are received and transmitted by transceiver 124.
  • Transceiver 124 is coupled to network interface 122.
  • Network interface 122 reformats packetized data being transfened between the cable modem MAC bus 1118 and the transceiver 124 such that the transceiver may communicate with the gateway. Reformatting of the data is accomplished by
  • FIG. 5 is a block diagram of a transceiver and network interface.
  • An RF/IF interface connection is typically provided to an antenna (not shown) by an RF/IF interface 139.
  • RF/IF interface 139 is typically provided by a RF transceiver.
  • the RF/IF interface 139 is provided by a Bluetooth transceiver.
  • the RF/IF interface is coupled to a conventionally constructed digital transmitter 140 and to a conventionally constructed digital receiver 148 via receiver data line 149.
  • a synthesizer control line 145 couples the RF/IF interface 139 to a conventionally constructed frequency control block 146.
  • the frequency control block is in turn coupled to a conventionally constructed base band controller core 144.
  • the base band controller core 144 is coupled to the digital transmitter 140 via Tx control/data line 141.
  • the digital receiver 148 is coupled to the base band controller core 144 via Rx control/data line 143.
  • the base band controller core 144 is coupled to a conventionally constructed timing control block 147 and to the network interface 125.
  • the transceiver is typically integrated onto the CMOS substrate with the network interface. Although a CMOS circuit is described, those skilled in the art will realize that other equivalent integrated circuit 20 technologies may be utilized.
  • a transceiver utilizes a combination of frequency planning, circuit design, layout and implementation, differential signal paths, dynamic calibration, and self-tuning to achieve robust performance over process variation and interference.
  • This approach allows for the full integration of the transceiver 2 onto a single IC for a low cost, low power, reliable and more compact solution. This can be achieved by (1) moving external bulky and expensive image reject filters, channel select filters, and baluns onto the RF chip; (2) reducing the number of off-chip passive elements such as capacitors, inductors, and resistors by moving them onto the chip; and (3) integrating all the remaining components onto the chip.
  • the described exemplary embodiments of the transceiver do not require integration into a single IC and may be implemented in a variety of ways including discrete hardware components.
  • FIG. 6 is a block diagram of an exemplary embodiment of the transceiver including an antenna 8. a switch 9, a receiver 10, a transmitter 12, a local oscillator (LO) generator (also called a synthesizer) 14, a controller 16, and a self-testing unit 18. All of these components can be 5 packaged for integration into a single IC including components such as filters and inductors.
  • LO local oscillator
  • the transceiver can operate in either a transmit or receive mode.
  • the transmitter 12 is coupled to the antenna 8 through the switch 9.
  • the switch 9 provides sufficient isolation to prevent transmitter leakage from desensitizing or damaging the receiver 10.
  • the switch 9 directs signal transmissions from the antenna 8 to the receiver 10.
  • the position of the switch 9 can be controlled by an external device (not shown) such as a computer or any other processing device known in the art.
  • the receiver 10 provides detection of desired signals in the presence of noise and interference. It should be able extract the desired signals and amplify it to a level where information contained in the received transmission can be processed.
  • the receiver 10 is based on a heterodyne complex (I-Q) architecture with a
  • the LO generator 14 provides a reference signal to the receiver 10 to downconvert the received transmission to the programmed IF.
  • a low IF heterodyne architecture is chosen over a direct conversion receiver because of the DC offset problem in direct conversion architectures.
  • DC offset in direct conversion architectures arises from a number of sources including impedance mismatches, variations in
  • AC coupling between the IF stages can be used to remove the DC offset.
  • the transmitter 12 modulates incoming data onto a canier frequency.
  • the modulated canier is upconverted by the reference signal from the LO generator 14 and amplified to a
  • the transmitter uses a direct conversion architecture. With this approach only one step of upconversion is required This leads to a reduction in both circuit complexity and power consumption.
  • the controller 16 performs two functions.
  • the first function provides for adaptive programming of the receiver 10, transmitter 14 and LO generator 16.
  • the first function provides for adaptive programming of the receiver 10, transmitter 14 and LO generator 16.
  • transceiver can be programmed to handle various communication standards for local area networks (LAN) and personal areanetworks (PAN) including HomeRF, IEEE 802.11 , Bluetooth, or any other wireless standard known in the art. This entails programming the transceiver to handle different modulation schemes and data rates.
  • the described exemplary embodiment of the transceiver can support modulation schemes such as Binary Phase Shift Keying (BPSK),
  • Quadrature Phase Shift Keying QPSK
  • offset quadrature phase shift keying OFQPSK
  • Multiple frequency modulations such as M level frequency shift keying (FSK), Continuous Phase Frequency Shift Keying modulation (CFSK), Minimum Shift Keying modulation (MSK), Gaussian filtered FSK modulation (GFSK), and Gaussian filtered Minimum Shift Keying (GMSK), Phase/ Amplitude modulation (such as Quadrature Amplitude Modulation (QAM)),
  • M level frequency shift keying FSK
  • Continuous Phase Frequency Shift Keying modulation CFSK
  • Minimum Shift Keying modulation MSK
  • GFSK Gaussian filtered FSK modulation
  • GMSK Gaussian filtered Minimum Shift Keying
  • Phase/ Amplitude modulation such as Quadrature Amplitude Modulation (QAM)
  • IF frequency hopped spread spectrum systems and numerous other modulation schemes known in the art.
  • Dynamic programming of 1 the transceiver can also be used to provide optimal operation in the presence of noise and interference.
  • the IF can be programmed to avoid interference from an external source.
  • the second function provides for adaptive calibration of the receiver 10. transmitter 14 and LO generator 16.
  • the calibration functionality controls the parameters of the transceiver to account for process and temperature variations that impact performance.
  • resistors can be calibrated within exacting tolerances despite process variations in the chip fabrication process. These exacting tolerances can be maintained in the presence of temperature
  • n changes by adaptively fine tuning the calibration of the resistors.
  • the controller 16 can be controlled externally by a central processing unit (CPU) , a microprocessor, a digital signal processor (DSP), a computer, or any other processing device known in the art.
  • a control bus 17 provides two way communication between the controller 16 and the external processing device (not shown). This
  • 5 communication link can be used to externally program the transceiver parameters for different modulation schemes, data rates and IF operating frequencies.
  • the output of the controller 16 is used to adjust the parameters of the transceiver to achieve optimal performance in the presence of process and temperature variations for the selected modulation scheme, data rate and IF.
  • the self-testing unit 18 generates test signals with different amplitudes and frequency
  • test signals are coupled to the receiver 10, transmitter 12 and LO generator 14 where they are processed and returned to the self-testing unit 18.
  • the return signals are used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver 10. transmitter 12 and LO generator 14. This is accomplished by measuring the strength of the signals output from the self-testing unit 18 against the returned signals over the
  • these measurements can be made with different transceiver parameters by sweeping the output of the controller 16 through its entire calibrating digital range, or alternatively making measurements with the controller output set to a selected few points, by way of example, at the opposite ends of the digital range.
  • the self-testing unit 18 is in communication with the external processing device (not shown) via the control bus 17. During self- test, the external processing device provides programming data to both the controller 16 and the self-testing unit 18. The self-testing unit 18 utilizes the programming data used by the controller 16 to set the parameters of the transceiver to determine the gain, frequency characteristics, selectivity, noise
  • FIG. 7 shows a block diagram of the transceiver in accordance with an embodiment of the invention.
  • the described exemplary embodiment is integrated into a single IC.
  • each component coupled to the controller is shown with a "program” designation or a "calibration” designation. These designations indicate whether the component is programmed by the controller or calibrated by the controller.
  • program designation
  • calibration designations indicate whether the component is programmed by the controller or calibrated by the controller.
  • the components that are programmed receive the MSBs and the components that are calibrated receive the LSBs.
  • the components requiring both programming and calibration receive the entire digital output from the controller.
  • any number of methodologies may be used to deliver programming and calibration information to the individual components.
  • n single controller bus could be used having the programming and or calibration data with the appropriate component addresses.
  • the receiver 10 front end includes a low noise amplifier (LNA) 22 which provides high gain with good noise figure performance.
  • LNA low noise amplifier
  • the gain of the LNA 22 can be set by the controller (not shown) through a "select gain" input to maximize the receivers dynamic range.
  • the output of the LNA 22 is downconverted to a low IF frequency by the combination of
  • LNA 22 is coupled to the complex IF mixers 24 which generate a spectrum of frequencies based upon the sum and difference of the received signal and the RF clocks from the LO generator.
  • the complex bandpass filter passes the complex IF signal while rejecting the image of the received signal.
  • the complex bandpass filter 26 eliminates the need for the costly and power consuming preselect filter typically required at the input of the LNA for conventional low IF architectures.
  • the output of the complex bandpass filter 26 is coupled to a programmable multiple gain stage amplifier 28.
  • the amplifier 28 can be designed to be programmable to select between a limiter and an automatic gain control (AGC) feature, depending on the modulation scheme used
  • the limiting amplifier can be selected if the transceiver uses a constant envelope modulation such as FSK.
  • AGC can be selected if the modulation is not a constant envelope, such as QAM.
  • the bandwidth of the amplifier 28 can be changed by the controller to accommodate various data rates and modulation schemes.
  • the output of the amplifier 28 is coupled to a second set of complex IF mixers 30 where
  • the complex IF mixers 30 not only reject the image of the complex IF signal, but also reduces some of the unwanted cross modulation spurious signals thereby relaxing the filtering requirements.
  • the complex baseband signal from the mixers 30 is coupled to a programmable passive polyphase filter within a programmable low pass filter 32.
  • the programmable low pass filter 32 further filters out higher order cross modulation products.
  • the polyphase filter can be centered at four times the IF frequency to notch out one of the major cross modulation products which results from the multiplication of the third harmonic of the IF signal with the IF clock.
  • A/D analog-to-digital
  • the analog demodulator 36 can be implemented to handle any number of different modulation schemes by way of example FSK.
  • Embodiments of the present invention with an FSK demodulator uses the A/D converter 36 to sample baseband data with other modulation schemes for digital demodulation in a digital signal processor (not shown). 5
  • the LO generator 14 provides the infrastructure for frequency planning. The LO generator
  • the 14 includes an IF clock generator 44 and an RF clock generator 47.
  • the IF clock generator includes an oscillator 38 operating at a ratio of the RF signal (fOCS). High stability and accuracy can be achieved in a number of ways including the use of a crystal oscillator.
  • the reference frequency output from the oscillator 38 is coupled to a divider 40.
  • the ⁇ divider 40 divides the reference signal fOSC by a number L to generate the IF clocks for downconverting the complex IF signal in the receiver to baseband.
  • a clock generator 41 is positioned at the output of the divider 40 to generate a quadrature sinusoidal signal from the square wave output of the divider 40. Alternatively, the clock generator 41 can be located in the receiver.
  • the divider 40 may be programmed by through the program input. This feature allows 5 changes in the IF frequency to avoid interference from an external source.
  • the output of the divider 40 is coupled to the RF clock generator 47 where it is further divided by a number n by a second divider 42.
  • the output of the second divider 42 provides a reference frequency to a phase lock loop (PLL) 43.
  • the PLL includes a phase detector 45, a divide by M circuit 46 and a voltage controlled oscillator (VCO) 48.
  • the output of the VCO 48 Q is fed back through the divide by M circuit 46 to the phase detector 45 where it is compared with the reference frequency.
  • the phase detector 45 generates an enor signal representative of the phase difference between the reference frequency and the output of the divide by M circuit 46.
  • the enor signal is fed back to the control input of the VCO 48 to adjust its output frequency fVCO until the VCO 48 locks to a frequency which is a multiple of the reference frequency.
  • the 5 VCO 48 may be programmed by setting M via the controller through the program input to the divide by M circuit 46.
  • the programmability resolution of the VCO frequency fVCO is set by 1 the reference frequency which also may be programmed by the controller through the program input of the divider 42.
  • the VCO frequency is sufficiently separated (in
  • This methodology is implemented with a divide by N circuit 50 coupled to the output of the VCO 48 in the PLL 43.
  • the output of the VCO 48 and the output of the divide by N circuit 50 are coupled to a complex mixer 52 where they are multiplied together to generate the RF clocks.
  • a filter 53 can be positioned at the output of the complex mixer to remove the harmonics and any residual mixing images of the RF clocks.
  • the divide by N circuit can be
  • fVCO (2/3)fLO
  • fNCO (3/4) fLO.
  • a VCO frequency set at 2/3 the frequency of the RF clocks works well in the described exemplary embodiment because the transmitter output is sufficiently separated (in frequency) from the VCO frequency.
  • the frequency of the RF clocks is high enough so that its harmonics and any residual mixing images such as fVCO ⁇ l-(l/N)), 3fVCO ⁇ l+(l/N), and
  • 3 fVCO x 1 -( 1 IN)) are sufficiently separated (in frequency) from the transmitter output to relax the filtering requirements of the RF clocks.
  • the filtering requirements do not have to be sharp because the filter can better distinguish between the harmonics and the residual images when they are separated in frequency.
  • Programming the divide by N circuit 50 also provides for the
  • the outputs of the divide by N circuit 50 would not be quadrature.
  • the divider 50 outputs will be differential, but will not be 90 degrees out of phase, i.e., will not be I-Q signals.
  • the RF clocks are generated in the in the LO
  • the mixer 52 will produce a spectrum of frequencies including the sum and difference frequencies, specifically, fVCO ⁇ (l+(l/N)) and its image fVCO ⁇ (l-(l/N)). To reject the image, the mixer 52 can be
  • the double quadrature mixer includes one pair of mixers 55, 57 to generate the Q-clock and a second pair of mixers 59, 61 to generate the I-clock.
  • the Q-clock mixers utilizes a first mixer 55 to mix the I output of the VCO 48 (see FIG. 2) with the Q output of the divider 40 and a second mixer 57 to mix the Q output of the VCO with the I output of the divider.
  • the outputs of the first and second mixers are connected together to generate the Q-clock.
  • the I-clock mixers utilizes a first mixer 59 to mix the I output of the divider with the Q output of the VCO and a second mixer 61 to mix the Q output of the divider with the I output of the VCO.
  • the outputs of the first and second mixers are connected together to generate the I-clock.
  • Optimized performance is achieved through frequency planning and implemented by programmable dividers in the LO generator to select different ratios. Based on FIG. 2, all the dependencies of the frequencies are shown by the following equation:
  • fRF frequency of the transmitter output
  • the transmitter 12 includes a complex buffer 54 for coupling incoming I-Q modulated baseband signals to a programmable low-pass filter 56.
  • the low-pass filter 56 can be programmed by the controller through the select input.
  • the output of the low-pass filter 56 is coupled to complex mixers 58.
  • the complex mixers 58 mixes the I-Q modulated baseband signals with the RF clocks from the LO generator to directly upconvert the baseband signals to the transmitting frequency.
  • the upconverted signal is then coupled to an amplifier 60 and eventually a power amplifier (PA) 62 for transmission into free space through the antenna.
  • PA power amplifier
  • a bandpass filter (not shown) may be disposed after the PA 62 to filter out unwanted frequencies before transmission through the antenna.
  • the transmitter can be configured to minimize spurious transmissions.
  • Spurious transmissions in a direct conversion transmitter are generated mainly because of the nonlinearity of the complex mixers and the DC offsets at the input to the complex mixers.
  • the complex mixers can be designed to meet a specified IIP3 (Input Intercept Point for the 3rd Harmonic) for the maximum allowable spurs over the frequency spectrum of the communications standard.
  • the DC offsets at the input to the complex mixers can be controlled by the physical size of the transistors.
  • the transmitter can be designed to minimize spurious transmission outside the frequency spectrum of the communications standard set by the FCC. There are two sources for these spurs: the LO generator and the transmitter.
  • spurs can be are suppressed by multiple filtering stages in the LO generator and transmitter.
  • all the spurs are at least fNCO N away from the RF clocks.
  • N By setting N to 2, by way of example, these unwanted spurs will be sufficiently separated (in frequency) from the transmitted signal and are easily removed by conventional filters in the LO generator and transmitter.
  • the spurs will be mainly limited to the harmonics of the transmitted signal, which are also sufficiently separated (in frequency) from the transmitted signal, and therefore, can be rejected with conventional filtering techniques.
  • a dielectric filter may be placed after the PA in the transmitter.
  • transceiver embodiment presented is described in more detail in co-pending U.S. Application entitled “Adaptive Transceiver,” filed October 23, 2000, Atty Docket No. 40593/CAG/B600. The disclosure thereof is incorporated herein in its entirety by reference.
  • FIG. 8 is block diagram of a wall dongle.
  • the wall dongle 138 provides a means of
  • a local backbone connection 1 10 is available through a telephone wall jack (not shown). This connection is typically provided through an RJ-1 1 type phone jack.
  • Connector 128, an RJ-1 1 phone plug in the exemplary embodiment couples an external cable 120 to the local backbone 1 10.
  • External cable 120 is coupled to a conventionally constructed network interface 122 which
  • ⁇ n is in turn coupled via connection 130 to a transceiver 124, including an emitter 1 18 utilized for transmitting and receiving over the wireless link.
  • CMOS complementary metal-oxide-semiconductor
  • alternative embodiments include differing substrates other than silicon fabricated by the CMOS process. Also, differing processes known to those skilled in the art may
  • network interface 122 and transceiver 124 are not disposed on a common substrate.
  • FIG. 9 is a block diagram of a device dongle.
  • a device dongle 136 provides the second half to the wireless cable replacement system.
  • the device dongle 136 is coupled to the wall dongle 138 through a wireless coupling mechanism.
  • the wireless coupling mechanism includes
  • a client device 132 typically includes a data I/O port 134 typically providing data formatted in an Ethernet or HomePNA format utilized by the Intranet via the local backbone connections.
  • a connector 129 included in device dongle 136 is coupled to data I/O port 134 to transfer data formatted according to the client device's architecture, to a network interface 122.
  • a conventionally constructed network interface 122 converts the data supplied by the data I/O port 134 into a format suitable for presentation to transceiver 124. 1
  • the network interfaces utilize conventionally constructed circuitry to reformat a given data type, present on the Intranet or at the gateway, to data suitable for transmission via a Bluetooth compatible transceiver.
  • a Bluetooth compatible transceiver Several data types present on the
  • Intranet or at the gateway, include PNA, ADSL, Ethernet and IDSL.
  • the network interface 122 and the transceiver 124 are disposed on a common substrate 142.
  • the network interface 122 and the transceiver 124 may be disposed on differing substrates.
  • FIG. 10 illustrates the physical construction of an exemplary dongle.
  • the dongle can be
  • the dongle has high density packaging with a light weight construction for ease of use.
  • the dongle includes a transceiver housing 160 formed of a suitably sturdy material.
  • the transceiver housing 160 is coupled to a connector 1162 with a short cable 164.
  • Various connector can be employed to support numerous applications.
  • an RJ-45 connector can be used to access an Ethernet device
  • Ethernet backbone depending on whether the dongle is used as a device dongle or wall dongle.
  • an RJ-11 connector can be used to access a telephony device, computer, or appliance when used as a device dongle or an HPNA backbone when used as a wall dongle.
  • a telephony device computer, or appliance
  • HPNA backbone when used as a wall dongle.
  • other connectors can be used to support other wireless applications.
  • the transceiver housing 160 provides an enclosure for a network interface 166 positioned rearwardly for easy coupling to the short cable 164. Forward of the network interface 166 is a bluetooth transceiver 168.
  • the bluetooth transceiver 168 includes an antenna 170 which protrudes from the forward end of the transceiver housing 160 in manner which optimizes reception and transmission coverage.
  • 25 166 can be powered from a variety of sources and may receive supplemental power from a solar panel 172 positioned within the transceiver housing 160.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Small-Scale Networks (AREA)

Abstract

L'invention concerne un système de remplacement de câble sans fil, comprenant un réseau zonal personnel comprenant un dispositif composé d'un premier émetteur-récepteur sans fil, un adaptateur composé d'un second émetteur-récepteur sans fil en communication avec le premier émetteur-récepteur sans fil, et une prise capable de se connecter à un jack couplé à une dorsale locale.
EP00976936A 1999-11-02 2000-11-02 Systeme de remplacement de cable sans fil Withdrawn EP1228601A1 (fr)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US16317199P 1999-11-02 1999-11-02
US163171P 1999-11-02
US16339999P 1999-11-04 1999-11-04
US163399P 1999-11-04
US23637400P 2000-09-28 2000-09-28
US23622200P 2000-09-28 2000-09-28
US236222P 2000-09-28
US236374P 2000-09-28
PCT/US2000/030437 WO2001033773A1 (fr) 1999-11-02 2000-11-02 Systeme de remplacement de cable sans fil

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EP1228601A1 true EP1228601A1 (fr) 2002-08-07

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EP00976936A Withdrawn EP1228601A1 (fr) 1999-11-02 2000-11-02 Systeme de remplacement de cable sans fil

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EP (1) EP1228601A1 (fr)
AU (1) AU1464201A (fr)
WO (1) WO2001033773A1 (fr)

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FR2842693B1 (fr) * 2002-07-22 2005-02-11 France Telecom Dispositif automatique de retransmission d'informations
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