EP1219072A1 - Operating method for a data bus - Google Patents

Operating method for a data bus

Info

Publication number
EP1219072A1
EP1219072A1 EP00962458A EP00962458A EP1219072A1 EP 1219072 A1 EP1219072 A1 EP 1219072A1 EP 00962458 A EP00962458 A EP 00962458A EP 00962458 A EP00962458 A EP 00962458A EP 1219072 A1 EP1219072 A1 EP 1219072A1
Authority
EP
European Patent Office
Prior art keywords
operating method
clock generator
data bus
clock
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00962458A
Other languages
German (de)
French (fr)
Inventor
Martin Peller
Josef Berwanger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bayerische Motoren Werke AG
Original Assignee
Bayerische Motoren Werke AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bayerische Motoren Werke AG filed Critical Bayerische Motoren Werke AG
Publication of EP1219072A1 publication Critical patent/EP1219072A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40169—Flexible bus arrangements
    • H04L12/40176—Flexible bus arrangements involving redundancy
    • H04L12/40202—Flexible bus arrangements involving redundancy by using a plurality of master stations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/40—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection

Definitions

  • the invention relates to an operating method for a data bus with the features of the preamble of claim 1
  • a data bus that can be used within the scope of the invention results from DE 19720401 A.
  • the data bus then described preferably has a star topology. However, it can also have a bus topology known per se, in which the participants communicate with one another via one or more data lines within the data bus There is a bus master that generates synchronization pulses so that communication between the participants can take place
  • the invention has for its object to provide an operating method for a data bus of the type mentioned, with which the described problem of erroneous activation of a replacement master can be avoided
  • an independent monitoring element can be used, for example, which only enables the bus access in the permitted synchronization window. If a bus master is mistakenly accessed, the monitoring device can block access, notify the data bus system or the subscribers of the error in a suitable manner (for example via a serial interface to the microprocessor of the bus master and from there via "alive counter" to all subscribers), so that at the system level the corresponding ones Measures can be taken
  • These measures can consist, for example, of bringing a control system dependent on the data bus system into a safe state
  • Advantageous embodiments of the invention exist in the case of a data bus constructed as a star coupler, in that the clock generator itself is arranged in a star coupler and / or in the presence of a protocol controller, in that the clock generator is integrated in the protocol controller

Abstract

The invention relates to an operating method for a data bus which is provided with a clock generator. A second clock generator is activated when said first clock generator has a failure.

Description

Betπebsverfahren für einen DatenbusOperating method for a data bus
Die Erfindung bezieht sich auf ein Betriebsverfahren für einen Datenbus mit den Merkmalen des Oberbegriffs von Patentanspruch 1The invention relates to an operating method for a data bus with the features of the preamble of claim 1
Ein Datenbus, der Im Rahmen der Erfindung einsetzbar ist, ergibt sich aus der DE 19720401 A Der dann beschriebene Datenbus besitzt vorzugsweise Sterntopologie Er kann aber auch eine an sich bekannte Bustopologie besitzen bei der die Teilnehmer über eine oder mehrere Datenleitungen miteinander kommunizieren Innerhalb des Datenbusses gibt es einen Busmaster, der Synchronisatioπspulse erzeugt, damit die Kommunikation zwischen den Teilnehmern stattfinden kannA data bus that can be used within the scope of the invention results from DE 19720401 A. The data bus then described preferably has a star topology. However, it can also have a bus topology known per se, in which the participants communicate with one another via one or more data lines within the data bus There is a bus master that generates synchronization pulses so that communication between the participants can take place
Wenn dieser Busmaster ausfallt, dann ist keine Kommunikation mehr möglich Deshalb ist es vorstellbar, einen Teilnehmer als Ersatzmaster zu definieren, der Synchronisationspulse erzeugt, wenn der Busmaster ausfallt Dies wird durch den Ersatzmaster daran erkannt, daß die Synchroπisationspulse ausbleiben Ist z B aber die Empfangsleitung des Ersatzmasters defekt, seine Sendeleitung aber noch funktionsfähig, wurde sich der Ersatzmaster irrtümlich aktivieren und dadurch den Datenverkehr stören, da er unsynchronisiert zum eigentlichen Busmaster Syπchronisie- rungspulse erzeugen wurdeIf this bus master fails, then communication is no longer possible.Therefore, it is conceivable to define a participant as a substitute master that generates synchronization pulses if the bus master fails.This is recognized by the substitute master by the fact that the synchronization pulses are absent Substitute master defective, but its transmission line still functional, the substitute master was activated by mistake and thereby disrupted the data traffic, since it would generate synchronization pulses unsynchronized with the actual bus master
Der Erfindung liegt die Aufgabe zugrunde, ein Betriebsverfahren für einen Datenbus der eingangs genannten Art zu schaffen, mit dem sich das beschriebene Problem einer irrtumlichen Aktivierung eines Ersatzmasters vermeiden laßtThe invention has for its object to provide an operating method for a data bus of the type mentioned, with which the described problem of erroneous activation of a replacement master can be avoided
Eine Losung dieses Problems ist die gezielte und absichtliche Aktivierung von meh- reren Busmastern auf dem Datenbus Die verschiedenen Busmaster synchronisieren sich dabei gegenseitig derart daß sich z B immer der Busmaster mit der „schnellsten Uhr" (Taktgenerator mit der höchsten Frequenz) mit seiner Synchroni- sierungssequenz durchsetzt und alle anderen Busmaster aufsynchronisiertOne solution to this problem is the targeted and deliberate activation of several bus masters on the data bus. The various bus masters synchronize each other in such a way that, for example, the bus master always interacts with the "Fastest clock" (clock generator with the highest frequency) interspersed with its synchronization sequence and all other bus masters synchronized
Zur Vermeidung des Falles, daß ein Busmaster völlig außerhalb des Synchronisie- rungsfensters (definiert durch die Quarzungenauigkeiten) eine Synchronisierungs- sequenz absetzt kann z B ein unabhängiges Uberwachungsglied eingesetzt werden, das nur im erlaubten Synchronsierungsfenster den Buszugπff freigibt Falls irrtümlich ein Buszugπff eines Busmasters erfolgt, kann die Uberwachungseinπch- tung den Zugriff sperren, dem Datenbussystem bzw den Teilnehmern auf geeignete Weise den Fehler mitteilen (z B über eine serielle Schnittstelle an den Mikroprozessor des Busmasters und von dort per „alive-counter" an alle Teilnehmer), damit auf Systemebene entsprechende Maßnahmen getroffen werden können Diese Maßnahmen können beispielsweise dann bestehen, ein vom Datenbussystem abhangiges Steuerungssystem in einen sicheren Zustand zu bringenTo avoid the case that a bus master sends a synchronization sequence completely outside the synchronization window (defined by the crystal inaccuracies), an independent monitoring element can be used, for example, which only enables the bus access in the permitted synchronization window. If a bus master is mistakenly accessed, the monitoring device can block access, notify the data bus system or the subscribers of the error in a suitable manner (for example via a serial interface to the microprocessor of the bus master and from there via "alive counter" to all subscribers), so that at the system level the corresponding ones Measures can be taken These measures can consist, for example, of bringing a control system dependent on the data bus system into a safe state
Vorteilhafte Ausgestaltungen der Erfindung bestehen im Falle eines als Stemkoppler aufgebauten Datenbus, indem der Taktgenerator selbst in einem Stemkoppler angeordnet ist und/oder bei Vorhandensein eines Protokollcontroller, indem der Taktgeber in den Protokollcontroller integriert istAdvantageous embodiments of the invention exist in the case of a data bus constructed as a star coupler, in that the clock generator itself is arranged in a star coupler and / or in the presence of a protocol controller, in that the clock generator is integrated in the protocol controller
Das Problem der irrtümlichen Aktivierung des Ersatzmasters laßt sich damit losen The problem of the erroneous activation of the replacement master can thus be solved

Claims

Patentansprücheclaims
1 Betriebsverfahren für einen Datenbus der einen Taktgeber besitzt dad urch gekennzeichnet daß bei Ausfall des Taktgeberes ein zweiter Taktgeber aktiviert wird1 operating method for a data bus that has a clock generator, characterized in that a second clock generator is activated if the clock generator fails
2 Betriebsverfahren nach Anspruch 1 dad urch gekennzeichnet daß der erste und der zweite Taktgeber im Normalfall gleichzeitig aktiviert und aufeinander synchronisiert werden2 Operating method according to claim 1 dad characterized in that the first and the second clock are normally activated and synchronized with each other in the normal case
3 Betπebsverfahren nach Anspruch 2, dadurch gekennzeichnet, daß der Taktgeber mit der höheren Frequenz den Taktgeber mit der niedrigeren Frequenz auf seine Taktfrequenz aufsynchronisiert3 Betπebsverfahren according to claim 2, characterized in that the clock generator with the higher frequency synchronizes the clock generator with the lower frequency to its clock frequency
4 Betriebsverfahren nach Anspruch 3 dadurch gekennzeichnet, da ß der Taktgeber mit der niedrigeren Frequenz seinen Sendebetrieb einstellt4 Operating method according to claim 3, characterized in that ß the clock with the lower frequency stops its transmission
5 Betriebsverfahren nach einem der Ansprüche 2 bis 4, dadurch gekennzeichnet, daß der Taktgeber mit der niedrigeren Frequenz nur dann auf den Taktgeber mit der höheren Frequenz aufsynchronisiert wird, wenn dessen Taktfrequenz ein vorgegebenes Maß nicht übersteigt 5 Operating method according to one of claims 2 to 4, characterized in that the clock generator with the lower frequency is only synchronized to the clock generator with the higher frequency if its clock frequency does not exceed a predetermined level
EP00962458A 1999-10-04 2000-09-08 Operating method for a data bus Withdrawn EP1219072A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19947662 1999-10-04
DE19947662A DE19947662A1 (en) 1999-10-04 1999-10-04 Operating method for a data bus
PCT/EP2000/008785 WO2001026297A1 (en) 1999-10-04 2000-09-08 Operating method for a data bus

Publications (1)

Publication Number Publication Date
EP1219072A1 true EP1219072A1 (en) 2002-07-03

Family

ID=7924373

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00962458A Withdrawn EP1219072A1 (en) 1999-10-04 2000-09-08 Operating method for a data bus

Country Status (5)

Country Link
US (1) US20020163370A1 (en)
EP (1) EP1219072A1 (en)
JP (1) JP2003511903A (en)
DE (1) DE19947662A1 (en)
WO (1) WO2001026297A1 (en)

Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
KR102253158B1 (en) * 2014-11-21 2021-05-18 현대모비스 주식회사 Vehicels network system and the operation method

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US4239982A (en) * 1978-06-14 1980-12-16 The Charles Stark Draper Laboratory, Inc. Fault-tolerant clock system
NL8203921A (en) * 1982-10-11 1984-05-01 Philips Nv MULTIPLE REDUNDANT CLOCK SYSTEM, CONTAINING A NUMBER OF SYNCHRONIZING CLOCKS, AND CLOCK CIRCUIT FOR USE IN SUCH A CLOCK SYSTEM.
US4683570A (en) * 1985-09-03 1987-07-28 General Electric Company Self-checking digital fault detector for modular redundant real time clock
NL8502768A (en) * 1985-10-10 1987-05-04 Philips Nv DATA PROCESSING DEVICE, COMPRISING MULTIPLE, PARALLEL-OPERATING DATA PROCESSING MODULES, MULTIPLE REDUNDANT CLOCK, CONTAINING A NUMBER OF MACHINERY-SYNCHRONIZING CLOCK CIRCUITS FOR USE IN ANY IN-PROPERTY AND PROCESSING EQUIPMENT.
US4979191A (en) * 1989-05-17 1990-12-18 The Boeing Company Autonomous N-modular redundant fault tolerant clock system
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Also Published As

Publication number Publication date
DE19947662A1 (en) 2001-04-12
JP2003511903A (en) 2003-03-25
US20020163370A1 (en) 2002-11-07
WO2001026297A1 (en) 2001-04-12

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