EP1203401A1 - Integrated inductive circuits - Google Patents

Integrated inductive circuits

Info

Publication number
EP1203401A1
EP1203401A1 EP00967395A EP00967395A EP1203401A1 EP 1203401 A1 EP1203401 A1 EP 1203401A1 EP 00967395 A EP00967395 A EP 00967395A EP 00967395 A EP00967395 A EP 00967395A EP 1203401 A1 EP1203401 A1 EP 1203401A1
Authority
EP
European Patent Office
Prior art keywords
well
substrate
circuit
circuits
radio frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00967395A
Other languages
German (de)
French (fr)
Inventor
Ting-Wah Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Programmable Silicon Solutions
Original Assignee
Programmable Silicon Solutions
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Programmable Silicon Solutions filed Critical Programmable Silicon Solutions
Priority claimed from PCT/US2000/040646 external-priority patent/WO2001093317A1/en
Publication of EP1203401A1 publication Critical patent/EP1203401A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • This invention relates generally to radio frequency (RF) integrated circuits that include active devices and passive components such as inductors and capacitors used for radio frequency devices such as cellular telephones and wireless network devices such as Bluetooth and other wireless devices and personal digital assistants.
  • RF radio frequency
  • Radio frequency circuits have not been mixed with logic circuits in the same integrated circuit.
  • Radio frequency circuits are analog circuits that are involved in filtering and detecting radio frequency signals such as cellular telephone signals.
  • logic circuits generally include transistors and other active components that form digital integrated circuit devices.
  • bipolar techniques may be utilized to manufacture radio frequency circuits and standard complementary metal oxide semiconductor (CMOS) processes may be utilized to manufacture logic circuits.
  • CMOS complementary metal oxide semiconductor
  • Memory circuits may account for still another category.
  • special processes may be utilized in connection with the manufacture of memory circuits because of special design considerations such as multiple gate electrodes and special voltage supply needs.
  • memory circuits are often fabricated separately from logic circuits.
  • Still another category are the so-called mixed signal circuits which may include both digital and analog components. These signals too may be accounted for separately so that a device that includes RF signal processing, RF integrated circuits, mixed signal circuits, logic circuits and memory circuits may be made up of a number of separately fabricated integrated circuit chips.
  • the cost of an electronic device may be closely correlated to the extent of integration that is possible. The more devices and the more types of devices that can be integrated into a single integrated circuit and manufactured using highly replicated techniques, the lower the resulting price.
  • Silicon Wave Inc. has devised a so-called silicon over insulator (SOI) BiCMOS (Bipolar
  • CMOS complementary metal oxide semiconductor
  • Figure 1 is a depiction of the various families of integrated circuit technologies that may be fabricated on the same integrated circuit in accordance with embodiments of the present invention
  • Figure 2 is a block depiction of a cellular telephone in accordance with one embodiment of the present invention
  • Figure 3 is a block diagram of a Bluetooth transceiver in accordance with one embodiment of the present invention
  • Figure 4 is a greatly enlarged cross-sectional view of an inductive circuit element in accordance with one embodiment of the present invention
  • Figure 5 is a greatly enlarged top plan view of an inductive element in accordance with one embodiment of the present invention
  • Figure 6 is an equivalent circuit of the inductive element shown in Figures 4 and 5;
  • Figure 7 is a perspective view of an embodiment of the inductive element shown in Figure 5;
  • Figures 8 A and 8B are top plan views of two different layers of an inductive element that may be used in the present invention.
  • Figure 9 is an enlarged cross-sectional view of still another embodiment of an inductive element that may be utilized in connection with the present invention;
  • Figure 10 is a perspective view of the inductive element shown in Figure 9;
  • Figure 11 is a top plan view of layer one in the embodiment shown in Figure 9;
  • Figure 12 is top plan view of layer two in the embodiment shown in Figure 9;
  • Figure 13 is a top plan view of layer three in the embodiment shown in Figure 9;
  • Figure 14 is a front elevational view of the combined effect of the layers one through three in forming an inductive element.
  • an integrated circuit 10 may include analog circuit elements operating above 100 megahertz, such as RF components 12, mixed signal components 14 and logic and memory components 16, all integrated within the same monolithic integrated circuit. Coupling between the radio frequency circuit elements, such as inductors, capacitors and transistors and the substrate on which the components are all integrated can be reduced, if not effectively eliminated, by creating an effective reverse biased diode between the radio frequency component and the substrate. This reverse biased diode may be formed using a triple well fabrication process in which the inductive circuit element is formed over a triple well.
  • memory components such as flash memory and static random access memory (SRAM) may be made on the same process, in the same substrate, utilized to form logic circuits such as microprocessors and digital signal processors.
  • logic circuits such as microprocessors and digital signal processors.
  • the processes disclosed in U.S. Patents 5,926,418 and 5,867,425, assigned to the assignee of the present application, may be utilized to form both logic devices and flash memory.
  • a radio frequency transceiver useful in a cellular telephone 10a includes an antenna 18, a radio frequency section 20, a logic section 22, a memory 26 and an interface 24.
  • the interface 24 provides the graphical user interfaces that may be displayed on display screens to implement the functions of the cellular telephone 10a.
  • the logic circuit 22 may also include a microprocessor which operates using a memory 26.
  • the memory 26 is a flash memory.
  • the radio frequency section 20 may include a number of passive components including inductive circuits.
  • the radio frequency section 20 as well as the antenna 18 may be formed using integrated circuit techniques to create a single integrated circuit that includes all of the components 18, 20, 22, 24 and 26, in accordance with one embodiment of the present invention.
  • analog and digital components may be fabricated on the same integrated circuit chip.
  • complementary metal oxide semiconductor techniques may be utilized to form all of the components depicted in Figure 2 on a single chip.
  • particular components may be split among two or more integrated circuits.
  • the designer is free to position particular components on particular integrated circuits based on design considerations rather than process and technology incompatibilities.
  • the problem of coupling of unwanted signals to the RF components included in the radio frequency section 20 may be avoided by forming an effective reverse biased diode in the common substrate utilized to form all the components of the telephone 10a.
  • an integrated transceiver 10b for a wireless network may be fabricated using the same principles.
  • the Bluetooth transceiver 10b includes an antenna 28 coupled to a radio 30.
  • the radio 30 is coupled to a link baseband controller or link controller 32.
  • a central processor unit 34 couples an interface 36 and a memory 38.
  • the memory 38 may be a flash memory. All of the components may be integrated into a single chip in one embodiment.
  • An integrated radio frequency (RF) element 40 that may be utilized in connection with the RF section 20 or the radio 30 of the embodiments of Figures 2 and 3 or any other integrated circuit using an inductive element, is shown in Figure 4.
  • a triple well is defined within the substrate 42 by a P-well 46, a deep N-well 44 and the P-type substrate 42.
  • the P-well 46 is a well or tub within the deep N-well 44.
  • Two reverse biased pn junctions are created, one by the juxtaposition of the P-well 46 and N-well 44, and another by the juxtaposition of the P-type substrate 42 and the N-well 44. Both pn junctions may be biased by a potential V B on the N-well 44. For example, if the P- well 46 and P-type substrate 42 are grounded, increasing the bias potential on the N-well 44 increases the bias on each junction. In some embodiments, if the N-well 44 is biased, the P- well 46 floats.
  • Depletion regions are formed by the junction bias, adding a depletion capacitance across the pn junctions between the P-well 46 and N-well 44 and between the N-well 44 and the P-type substrate 42. These depletion capacitances can be reduced by increasing the bias across the pn junctions. The higher the junction bias, the more reduction in the junction capacitance, reducing the total capacitance. Reducing total capacitance reduces the capacitive coupling of the RF circuits to the substrate and the self-resonance frequency of the inductive element 40. The reverse biased junctions reduce the coupling of noise or other unwanted signals between the substrate 42 and the RF integrated circuit components, formed over the substrate 42, such as the capacitor 48 or the inductive element 50.
  • the layer 54 is conventionally formed of an oxide.
  • the present invention is equally applicable to multi-layer metal processes in which the passive components, such as the inductive element 50, are formed in any desired metal layer.
  • triple wells are well known.
  • U.S. Patents 5,926,418 and 5,867,425 (assigned to the assignee of the present application) provide an explanation of exemplary processes for forming a triple well.
  • the triple well process is equally applicable to manufacturing flash memory devices.
  • a flash memory may be formed in the same integrated circuit with logic family components such as processors and digital signal processors.
  • the inductive element 50 may be formed of a planar, spiral-shaped layer defined over the substrate 42, for example atop a oxide layer 54.
  • the inductive element 50 is formed by patterning and deposition techniques. However, any technique for forming the inductive element 50 may be utilized.
  • the resulting structure may be formed of a spiral-shaped flat ribbon that may include a plurality of interconnected straight sections such as the sections 58a and 58b.
  • the element 50 is positioned over the P-well 46 of the triple well 40. Appropriate electrical connections may be made through various layers to electrically couple the ends of the inductive element 50 to the rest of the integrated circuit.
  • Non-planar design may be used as shown in Figure 7 and as described, for example in U.S. Patent 5,545,916 to KouUias.
  • the spiral inductive element 50 shown in Figure 5, may have a non-planar cross-section as indicated in Figure 7 including a rectangular portion 70 and a circular portion 72.
  • Each of the trace elements 58c and 58d are arranged such that the material thickness favors the innermost edge "O".
  • the trace shown in Figure 7 is from the left side of the spiral inductive element 50 (shown in Figure 5). The material is added close to an edge "O" where the current may flow at higher frequencies.
  • the spiral inductive element 50 may have an non-rectangular configuration such as the multilevel, multi-element polygonal design, for example, as set forth in U.S. Patent 5,559,360, and as shown in Figure 8.
  • the layer with wires Ai through Aw has a first end A that is designated by the connective structure CON1.
  • a group often connective wires, A ⁇ >, A 2 > Aic are shown in the center of the spiral.
  • the wires Bi-B ⁇ .0 of the second layer, shown in Figure 8B are centrally connected to the wires Ai through Aio inverse sequentially.
  • the output of the spiral inductive element is identified as a parallel connection CON2 in Figure 8B that forms the parallel connections of all the elements of the B level.
  • a multi-layer non-planar integrated inductor design may also be used as the inductive element 50 (Figure 5), as described in U.S. Patent 6,008,102.
  • a series of three conductive layers one, two and three, are progressively coated one on top of another as shown in Figure 9.
  • the three layers combine to form an integrated helical coil as shown in Figure 14.
  • the first layer is formed of a conductive material in the shape shown in Figure 11
  • the second layer is formed of a conductive material in the shape shown in Figure 12
  • the third layer is formed of conductive in the shape shown in Figure 13.
  • the net effect of the three layers is the coil shown in Figure 14.
  • the angular coil 450 shown in Figure 10, has a series of multiple loops that are set perpendicularly to the plane of the substrate.
  • a layer 304 is coated over a passivated wafer.
  • the layer 304 may be formed of a conductive material such as titanium-tungsten (TiW) to form a barrier layer and provide for the adhesion of a subsequently sputtered layer of copper 306.
  • An initial photoresist layer 406 and a second photoresist 408 define the intervening conductive material.
  • the layer 414 may be a sputtered conductor, and a layer 420 is a third layer of plated metal while the material 416 may be photoresist.
  • An equivalent circuit, shown in Figure 6, for the inductive element 50 includes an inductance 62a which may arise from all or any part of the spiral-shaped inductive element 50.
  • the inductive element 50 may also be represented by resistance 62b which arises from the natural resistance of the material utilized to form the spiral-shaped inductive element 50.
  • a capacitance 64 arises from the capacitance between the inductive element 50 (or any other RF component such as fransistors and capacitors) and the substrate 42 and particularly by the intervening dielectric layer 54.
  • An additional resistance 66a may arise from the material utilized to form the P-well 46.
  • the effect of the pn junction created by the P-well 46 and the N-well 44 is represented by the diode 66b and the effect of the pn junction created by the N-well 44 and P-type subsfrate 42 is represented by the diode 66c.
  • the capacitance 67b and the diode 66c reduce the coupling from the subsfrate 42 back to the inductor 50.
  • the reverse biased diode 66b oriented oppositely to the diode 66c, reduces the inductive element 50 capacitive coupling losses to the substrate 42.
  • the inductive element 50 may be a highly tuned element that may be adversely affected by noise and other unwanted signals present in the subsfrate 42. These signals may be present in the substrate 42 due to the formation of a wide variety of other circuit elements in the same integrated circuit. These unwanted signals are isolated from the sensitive inductive element 50 by the reverse biased diode 66c.
  • radio frequency circuit elements including radio frequency circuit elements, mixed signal circuit elements, logic elements and memory elements, including flash memory elements, may all be formed in the same integrated circuit in the same substrate 42. Therefore, greater integration is possible and more efficient and lower cost radio frequency devices, such as Bluetooth transceivers and cellular telephones wireless local area networks, may be fabricated.
  • the benefits of the triple well can be further appreciated by comparing a triple well approach to a approach in which a single well such as a deep N-well is utilized below the inductive element 50.
  • the impedance caused by the deep N-well, in a deep N-well embodiment may be represented by the value R w .
  • the total impedance, R, from the inductive element 50 to the substrate then may be represented by the equation:
  • R ⁇ 5 of the triple well is expressed as (indicated as 64 follows:
  • the effect of the triple well is to substantially increase the impedance compared to a single deep N-well.
  • the capacitance created by the triple well can be adjusted by the N-well bias to be less than the capacitance created by the deep N-well.
  • the coupling that results from the capacitance in the triple well is significantly less.
  • the total impedance of the triple well is much greater than the impedance of the deep N-well and the capacitance of the triple well is less, there is less capacitive and resistive coupling to the subsfrate and also better noise isolation from the subsfrate to the RF circuits arising from the use of the triple well compared to the use of only a deep N-well.
  • the self-resonance frequency may also be improved in some embodiments, by reducing the total capacitance.
  • the self-resonance frequency is proportional to 1/LC, so that the lower the capacitance, the higher the self-resonance frequency or the better the high frequency performance of the inductor 50. Reducing the capacitive coupling also improves the quality factor or Q of the inductor 50.
  • additional wells may be incorporated to form a series of one or more additional diodes in other embodiments.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An RF circuit (12) may be formed over a triple well that creates two reverse biased junctions (66b and 66c). By adjusting the bias across the junctions, the capacitance (67a and 67b) across the junctions can be reduced, reducing the capacitive coupling from the RF circuits to the substrate (42), improving the self-resonance frequency of inductors (48, 50) and reducing the coupling of unwanted signals and noise from the underlying substrate to the active circuits and passive components such as the capacitors and inductors. As a result, radio frequency devices (10), such as radios, cellular telephones and transceivers such as Bluetooth transceivers, logic devices and Flash and SRAM memory devices may all be formed in the same integrated circuit die using CMOS fabrication processes.

Description

Integrated Inductive Circuits Background
This invention relates generally to radio frequency (RF) integrated circuits that include active devices and passive components such as inductors and capacitors used for radio frequency devices such as cellular telephones and wireless network devices such as Bluetooth and other wireless devices and personal digital assistants.
The technology for manufacturing integrated circuits has conventionally divided integrated circuits into various categories based on the compatibility of processes and other considerations. Generally, radio frequency circuits have not been mixed with logic circuits in the same integrated circuit. Radio frequency circuits are analog circuits that are involved in filtering and detecting radio frequency signals such as cellular telephone signals. In contrast, logic circuits generally include transistors and other active components that form digital integrated circuit devices. Thus, for example, bipolar techniques may be utilized to manufacture radio frequency circuits and standard complementary metal oxide semiconductor (CMOS) processes may be utilized to manufacture logic circuits.
Memory circuits may account for still another category. Generally, special processes may be utilized in connection with the manufacture of memory circuits because of special design considerations such as multiple gate electrodes and special voltage supply needs. Thus, memory circuits are often fabricated separately from logic circuits. Still another category are the so-called mixed signal circuits which may include both digital and analog components. These signals too may be accounted for separately so that a device that includes RF signal processing, RF integrated circuits, mixed signal circuits, logic circuits and memory circuits may be made up of a number of separately fabricated integrated circuit chips. The cost of an electronic device may be closely correlated to the extent of integration that is possible. The more devices and the more types of devices that can be integrated into a single integrated circuit and manufactured using highly replicated techniques, the lower the resulting price. Unfortunately, because of incompatibilities between the different types of integrated circuits, it has not been possible, to date, to fabricate both radio frequency circuits, mixed signal circuits, logic circuits and memory circuits all on the same standard CMOS integrated circuit process. One problem that arises in connection with radio frequency circuits in CMOS processes is that the passive components such as capacitors and inductors may be adversely affected by the substrates over which they are formed. In particular, coupling may occur between the substrate and integrated circuit inductors for example. This coupling may result in degraded performance of inductive circuits. As a result, inductive circuits may be formed in bipolar or silicon over insulator (SOI) integrated circuits rather than using standard CMOS logic processes. Thus, two or more integrated circuits are needed—one for logic, one for RF circuits, one for memory and one for mixed signals.
Some efforts have been made to overcome this coupling problem. For example, Silicon Wave Inc. has devised a so-called silicon over insulator (SOI) BiCMOS (Bipolar
CMOS) integrated circuit which integrates both logic and radio frequency components onto the same die. However, the use of silicon over insulator technology greatly complicates the manufacturing process and increases cost. Moreover, the bulk of semiconductor fabrication facilities in the United States and the rest of the world are dedicated to manufacturing metal oxide semiconductor technologies. The SOI process is not amenable to widespread manufacturing at a number of highly expensive, already existent, fabrication facilities.
Thus, there is a continuing need for better ways to manufacture integrated inductive circuits which enable these circuits to be manufactured using the same process technologies that are utilized for other circuit families such as mixed signal, memory and logic. Moreover, it would be desirable to have a way that avoids the capacitive coupling from RF circuits to the substrate and coupling of noise or other unwanted signals from substrates to circuit elements.
Brief Description of the Drawings Figure 1 is a depiction of the various families of integrated circuit technologies that may be fabricated on the same integrated circuit in accordance with embodiments of the present invention;
Figure 2 is a block depiction of a cellular telephone in accordance with one embodiment of the present invention; Figure 3 is a block diagram of a Bluetooth transceiver in accordance with one embodiment of the present invention; Figure 4 is a greatly enlarged cross-sectional view of an inductive circuit element in accordance with one embodiment of the present invention;
Figure 5 is a greatly enlarged top plan view of an inductive element in accordance with one embodiment of the present invention; Figure 6 is an equivalent circuit of the inductive element shown in Figures 4 and 5;
Figure 7 is a perspective view of an embodiment of the inductive element shown in Figure 5;
Figures 8 A and 8B are top plan views of two different layers of an inductive element that may be used in the present invention; Figure 9 is an enlarged cross-sectional view of still another embodiment of an inductive element that may be utilized in connection with the present invention;
Figure 10 is a perspective view of the inductive element shown in Figure 9;
Figure 11 is a top plan view of layer one in the embodiment shown in Figure 9;
Figure 12 is top plan view of layer two in the embodiment shown in Figure 9; Figure 13 is a top plan view of layer three in the embodiment shown in Figure 9; and
Figure 14 is a front elevational view of the combined effect of the layers one through three in forming an inductive element.
Detailed Description Referring to Figure 1, an integrated circuit 10 may include analog circuit elements operating above 100 megahertz, such as RF components 12, mixed signal components 14 and logic and memory components 16, all integrated within the same monolithic integrated circuit. Coupling between the radio frequency circuit elements, such as inductors, capacitors and transistors and the substrate on which the components are all integrated can be reduced, if not effectively eliminated, by creating an effective reverse biased diode between the radio frequency component and the substrate. This reverse biased diode may be formed using a triple well fabrication process in which the inductive circuit element is formed over a triple well.
In addition, memory components such as flash memory and static random access memory (SRAM) may be made on the same process, in the same substrate, utilized to form logic circuits such as microprocessors and digital signal processors. For example, the processes disclosed in U.S. Patents 5,926,418 and 5,867,425, assigned to the assignee of the present application, may be utilized to form both logic devices and flash memory.
A radio frequency transceiver useful in a cellular telephone 10a, shown in Figure 2, includes an antenna 18, a radio frequency section 20, a logic section 22, a memory 26 and an interface 24. The interface 24 provides the graphical user interfaces that may be displayed on display screens to implement the functions of the cellular telephone 10a. The logic circuit 22 may also include a microprocessor which operates using a memory 26. In one embodiment of the present invention, the memory 26 is a flash memory. The radio frequency section 20 may include a number of passive components including inductive circuits. The radio frequency section 20 as well as the antenna 18 may be formed using integrated circuit techniques to create a single integrated circuit that includes all of the components 18, 20, 22, 24 and 26, in accordance with one embodiment of the present invention. In other embodiments, some but not all of the analog and digital components may be fabricated on the same integrated circuit chip. Generally, complementary metal oxide semiconductor techniques may be utilized to form all of the components depicted in Figure 2 on a single chip. However, in some cases, particular components may be split among two or more integrated circuits. However, the designer is free to position particular components on particular integrated circuits based on design considerations rather than process and technology incompatibilities. Again, the problem of coupling of unwanted signals to the RF components included in the radio frequency section 20 may be avoided by forming an effective reverse biased diode in the common substrate utilized to form all the components of the telephone 10a.
Similarly, an integrated transceiver 10b for a wireless network, for example in accordance with the Bluetooth specification may be fabricated using the same principles. The Bluetooth transceiver 10b includes an antenna 28 coupled to a radio 30. The radio 30 is coupled to a link baseband controller or link controller 32. A central processor unit 34 couples an interface 36 and a memory 38. In some embodiments of the present invention, the memory 38 may be a flash memory. All of the components may be integrated into a single chip in one embodiment. An integrated radio frequency (RF) element 40 that may be utilized in connection with the RF section 20 or the radio 30 of the embodiments of Figures 2 and 3 or any other integrated circuit using an inductive element, is shown in Figure 4. In this case, a triple well is defined within the substrate 42 by a P-well 46, a deep N-well 44 and the P-type substrate 42. The P-well 46 is a well or tub within the deep N-well 44.
Two reverse biased pn junctions are created, one by the juxtaposition of the P-well 46 and N-well 44, and another by the juxtaposition of the P-type substrate 42 and the N-well 44. Both pn junctions may be biased by a potential VB on the N-well 44. For example, if the P- well 46 and P-type substrate 42 are grounded, increasing the bias potential on the N-well 44 increases the bias on each junction. In some embodiments, if the N-well 44 is biased, the P- well 46 floats.
Depletion regions are formed by the junction bias, adding a depletion capacitance across the pn junctions between the P-well 46 and N-well 44 and between the N-well 44 and the P-type substrate 42. These depletion capacitances can be reduced by increasing the bias across the pn junctions. The higher the junction bias, the more reduction in the junction capacitance, reducing the total capacitance. Reducing total capacitance reduces the capacitive coupling of the RF circuits to the substrate and the self-resonance frequency of the inductive element 40. The reverse biased junctions reduce the coupling of noise or other unwanted signals between the substrate 42 and the RF integrated circuit components, formed over the substrate 42, such as the capacitor 48 or the inductive element 50.
The layer 54 is conventionally formed of an oxide. Of course, the present invention is equally applicable to multi-layer metal processes in which the passive components, such as the inductive element 50, are formed in any desired metal layer.
The techniques for forming triple wells are well known. For example, U.S. Patents 5,926,418 and 5,867,425 (assigned to the assignee of the present application) provide an explanation of exemplary processes for forming a triple well. The triple well process is equally applicable to manufacturing flash memory devices. By using the triple well process, a flash memory may be formed in the same integrated circuit with logic family components such as processors and digital signal processors.
Referring next to Figure 5, the inductive element 50 may be formed of a planar, spiral-shaped layer defined over the substrate 42, for example atop a oxide layer 54. Conventionally, the inductive element 50 is formed by patterning and deposition techniques. However, any technique for forming the inductive element 50 may be utilized. The resulting structure may be formed of a spiral-shaped flat ribbon that may include a plurality of interconnected straight sections such as the sections 58a and 58b. Advantageously, the element 50 is positioned over the P-well 46 of the triple well 40. Appropriate electrical connections may be made through various layers to electrically couple the ends of the inductive element 50 to the rest of the integrated circuit.
Alternatively a non-planar design may be used as shown in Figure 7 and as described, for example in U.S. Patent 5,545,916 to KouUias. The spiral inductive element 50, shown in Figure 5, may have a non-planar cross-section as indicated in Figure 7 including a rectangular portion 70 and a circular portion 72. Each of the trace elements 58c and 58d are arranged such that the material thickness favors the innermost edge "O". Thus, the trace shown in Figure 7 is from the left side of the spiral inductive element 50 (shown in Figure 5). The material is added close to an edge "O" where the current may flow at higher frequencies.
As another alternative, the spiral inductive element 50 may have an non-rectangular configuration such as the multilevel, multi-element polygonal design, for example, as set forth in U.S. Patent 5,559,360, and as shown in Figure 8. Referring to Figure 8A, the layer with wires Ai through Aw has a first end A that is designated by the connective structure CON1. A group often connective wires, Aι>, A2> Aic are shown in the center of the spiral. The wires Bi-Bι.0 of the second layer, shown in Figure 8B, are centrally connected to the wires Ai through Aio inverse sequentially. The output of the spiral inductive element is identified as a parallel connection CON2 in Figure 8B that forms the parallel connections of all the elements of the B level. Through the use of multiple parallel conductive elements arranged on the substrate (in lieu of a single element conductive path), the resistance may be decreased and self-inductance increases. The decreased resistance and increased inductance may result in an improved quality factor (Q).
A multi-layer non-planar integrated inductor design, as shown in Figures 9 through 14, may also be used as the inductive element 50 (Figure 5), as described in U.S. Patent 6,008,102. A series of three conductive layers one, two and three, are progressively coated one on top of another as shown in Figure 9. The three layers combine to form an integrated helical coil as shown in Figure 14. The first layer is formed of a conductive material in the shape shown in Figure 11 , the second layer is formed of a conductive material in the shape shown in Figure 12 and the third layer is formed of conductive in the shape shown in Figure 13. The net effect of the three layers is the coil shown in Figure 14. The angular coil 450, shown in Figure 10, has a series of multiple loops that are set perpendicularly to the plane of the substrate. Referring again to Figure 9, a layer 304 is coated over a passivated wafer. The layer 304 may be formed of a conductive material such as titanium-tungsten (TiW) to form a barrier layer and provide for the adhesion of a subsequently sputtered layer of copper 306. An initial photoresist layer 406 and a second photoresist 408 define the intervening conductive material. The layer 414 may be a sputtered conductor, and a layer 420 is a third layer of plated metal while the material 416 may be photoresist.
An equivalent circuit, shown in Figure 6, for the inductive element 50 (Figure 5) includes an inductance 62a which may arise from all or any part of the spiral-shaped inductive element 50. The inductive element 50 may also be represented by resistance 62b which arises from the natural resistance of the material utilized to form the spiral-shaped inductive element 50. A capacitance 64 arises from the capacitance between the inductive element 50 (or any other RF component such as fransistors and capacitors) and the substrate 42 and particularly by the intervening dielectric layer 54. An additional resistance 66a may arise from the material utilized to form the P-well 46. The effect of the pn junction created by the P-well 46 and the N-well 44 is represented by the diode 66b and the effect of the pn junction created by the N-well 44 and P-type subsfrate 42 is represented by the diode 66c. The capacitance 67b and the diode 66c reduce the coupling from the subsfrate 42 back to the inductor 50.
The reverse biased diode 66b, oriented oppositely to the diode 66c, reduces the inductive element 50 capacitive coupling losses to the substrate 42. Through the creation of the diode 66c, an effectively infinite resistance is created to reduce interference by substrate signals with the element 50 (and any other RF circuits). In particular, the inductive element 50 may be a highly tuned element that may be adversely affected by noise and other unwanted signals present in the subsfrate 42. These signals may be present in the substrate 42 due to the formation of a wide variety of other circuit elements in the same integrated circuit. These unwanted signals are isolated from the sensitive inductive element 50 by the reverse biased diode 66c.
As a result, a variety of different circuit types, including radio frequency circuit elements, mixed signal circuit elements, logic elements and memory elements, including flash memory elements, may all be formed in the same integrated circuit in the same substrate 42. Therefore, greater integration is possible and more efficient and lower cost radio frequency devices, such as Bluetooth transceivers and cellular telephones wireless local area networks, may be fabricated.
The benefits of the triple well can be further appreciated by comparing a triple well approach to a approach in which a single well such as a deep N-well is utilized below the inductive element 50. The impedance caused by the deep N-well, in a deep N-well embodiment, may be represented by the value Rw. The total impedance, R, from the inductive element 50 to the substrate then may be represented by the equation:
1 1
+ JωCv
R R„ where C is the capacitance resulting from the oxide between the inductive element 50 and the substrate and the capacitance of the substrate and ω is the frequency. Similarly, the total capacitance, Cw, for the series, is expressed as follows:
■ + • w ox CSUB where Cox is the capacitance due to the dielectric between the inductive element 50 and the subsfrate and CSUB is the capacitance between the inductive element 50 and the substrate. In contrast the total impedance, Rχ5 of the triple well is expressed as (indicated as 64 follows:
1 1 . _ — = — + jωCτ Rτ Rj where Rj is the resistance 66a of the N-well and CT is the capacitance of the triple well (indicated as 64 in Figure 6). Similarly, the series capacitance created by the triple well, CT, is as follows: where Cox is the capacitance 64 due to the oxide between the inductive element 50 and the subsfrate, Cj is the capacitance 67a arising from the junction between the P-well and the N- well and CSUB is the capacitance 67b between the N-well and the subsfrate. Since the impedance arising from the junction Rj is much greater than the impedance without the junction, the effect of the triple well is to substantially increase the impedance compared to a single deep N-well. Moreover, the capacitance created by the triple well can be adjusted by the N-well bias to be less than the capacitance created by the deep N-well. Thus, the coupling that results from the capacitance in the triple well is significantly less. Since the total impedance of the triple well is much greater than the impedance of the deep N-well and the capacitance of the triple well is less, there is less capacitive and resistive coupling to the subsfrate and also better noise isolation from the subsfrate to the RF circuits arising from the use of the triple well compared to the use of only a deep N-well.
The self-resonance frequency may also be improved in some embodiments, by reducing the total capacitance. The self-resonance frequency is proportional to 1/LC, so that the lower the capacitance, the higher the self-resonance frequency or the better the high frequency performance of the inductor 50. Reducing the capacitive coupling also improves the quality factor or Q of the inductor 50.
While an illustrated embodiment using a triple well is described, additional wells may be incorporated to form a series of one or more additional diodes in other embodiments.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims

What is claimed is:
1. An integrated circuit comprising; a substrate; a radio frequency circuit element formed in said subsfrate; and a triple well formed in said substrate under said radio frequency circuit element.
2. The circuit of claim 1 wherein said circuit is a complementary metal oxide semiconductor circuit.
3. The circuit of claim 1 wherein said triple well includes an N-well with a P- well formed in said N-well and wherein said substrate is a P-type substrate.
4. The circuit of claim 3 wherein said N-well is biased to form two depletion capacitors.
5. The circuit of claim 1 wherein said triple well forms two reverse biased diodes between the substrate and said circuit element.
6. The circuit of claim 1 wherein said circuit element is an inductive circuit element.
7. A method comprising: forming a radio frequency circuit element in a substrate; and forming a pair of oppositely oriented, reverse biased diodes in said subsfrate under said radio frequency circuit element.
8. The method of claim 7 wherein forming a pair of oppositely oriented reverse biased diodes includes forming a triple well.
9. The method of claim 7 including isolating said circuit element from the substrate and isolating the subsfrate from the circuit element.
10. The method of claim 7 including biasing said diodes to reduce the capacitances across said diodes.
11. The method of claim 7 including forming a P-well embedded in an N-well in a P-type substrate, grounding said P-well and substrate, and biasing the N-well positively.
EP00967395A 2000-05-30 2000-08-16 Integrated inductive circuits Withdrawn EP1203401A1 (en)

Applications Claiming Priority (5)

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US58071300A 2000-05-30 2000-05-30
US580713 2000-05-30
US59648600A 2000-06-19 2000-06-19
US596486 2000-06-19
PCT/US2000/040646 WO2001093317A1 (en) 2000-05-30 2000-08-16 Integrated inductive circuits

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