EP1186967A2 - Verfahren zur Uhrensynchronisation - Google Patents
Verfahren zur Uhrensynchronisation Download PDFInfo
- Publication number
- EP1186967A2 EP1186967A2 EP01119500A EP01119500A EP1186967A2 EP 1186967 A2 EP1186967 A2 EP 1186967A2 EP 01119500 A EP01119500 A EP 01119500A EP 01119500 A EP01119500 A EP 01119500A EP 1186967 A2 EP1186967 A2 EP 1186967A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- clock cycle
- clock
- clocks
- value
- synchronization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G7/00—Synchronisation
Definitions
- the invention relates to a method for synchronization several clocks with their respective setting ranges changeable clock cycle.
- a communication network include, to which several components as network nodes are connected, all or a part of each one own clock.
- the clocks typically include a high-frequency clock and a downstream one Divider that sets the clock pulse to the desired clock pulse divides down.
- An application of this kind are Vehicle electronics systems with a data bus network to which Several vehicle control units, each with its own clock, are connected are.
- the term "clock cycle" is very general Understanding the speed of a watch, i.e. how fast or slowly it runs regardless of whether the gait speed by dividing down a high frequency, from a Timers generated clock signal as indicated above, or is set in another conventional manner.
- the normalized gait speed is usually used in the range around a setpoint of one.
- the invention is e.g. for systems with distributed, i.e. spatially distant, arranged clocks applicable, the clock cycle within of a certain setting range can be changed controllably can.
- a known method for the synchronization of several such Watches with an adjustable clock rate is for one respective clock the deviation of its clock cycle from the clock cycles determine several other clocks and make an effective one To determine the correction value for your own clock cycle. This can e.g. done by a selected Part of the determined deviations for which the largest deviations are not taken into account, an average is formed, which then serves as a correction value. For tolerance a number k of incorrectly distributed clocks are at this known technique a number 3k + 1 of clock cycle measurements and determinations of the associated deviations required.
- Another known method for synchronizing multiple clocks consists of selecting a clock as the master clock and the time value of the other clocks on those at certain time intervals to coordinate the master clock.
- Such synchronization methods are in the published patent application DE 197 50 929 A1 and in the patent specification DE 38 03 525 C2.
- a fundamental problem this technique is that if there is a malfunction Master clock the synchronization of all clocks accordingly disturbed or is no longer possible.
- the invention is a technical problem of providing a clock synchronization method of the aforementioned Kind of basis with which several clocks with changeable clock cycle in a relatively simple and reliable manner synchronize.
- the invention solves this problem by providing a Clock synchronization method with the features of the claim 1.
- This procedure is characterized in that everyone From time to time the information about the current Clock cycle of one of the other clocks, e.g. as a corresponding time stamp or time difference information transmitted and thereby this strange clock cycle accessible to one of the other clocks is made and the own clock cycle depending on the foreign clock cycle updated, i.e. is redetermined if the foreign clock cycle within its own setting range lies, the update depending on the difference between the foreign and your own clock.
- the clocks are synchronized successive, synchronizing update processes in each clock depending on only one foreign clock cycle one of the other clocks. Accordingly, are only relative few time value measurement processes and time value transmission processes, from which the clock cycles can be derived, and complex procedures for determining a correction value as an average over specially selected clock deviations can be omitted. Nevertheless, the synchronization of a respective Watch each of the other watches by adding the watch one by one the clock cycles of all other clocks for updating be made accessible. Let go of this procedure There are several watches with possibly different initially Synchronize clock cycle to a common clock cycle and keep synchronized on this, as far as the setting ranges of the clocks at least in this common clock cycle overlap. Another significant advantage of the invention The procedure is that even in the event of a failure one or more any clocks for the rest, yet functioning clocks fully functional without further measures remains.
- the respective clock contains a timer 2, which generates a high-frequency clock signal, and a downstream Divider 3 with a through a control input 3a Correction control signal variable division ratio.
- the Divider 3 divides the high-frequency clock signal of the timer 2 in set, determined by the value of the correction control signal Division ratio and delivers that at its output divided clock signal as a clock for the concerned Clock.
- Fig. 2 illustrates the working area of the divider and thus the clock cycle setting range of the clock.
- the division ratio increases with increasing correction value to be applied to the divider control input 3a, as long as the latter is within a setting interval [F -1 , F 1 ] which represents the clock cycle setting range.
- a watch's own initial setpoint ie a default value
- This initial setpoint serves as the initial zeroing value of the correction control signal during system initialization.
- the division ratio is kept at the end value of the clock cycle setting range belonging to the relevant setting interval end value F -1 or F 1 , ie it remains limited to this ,
- Fig. 3 illustrates in diagram form an example of predetermined setting ranges E1, ..., En for the different, distributed clocks U1, ..., Un of Fig. 1, the setting ranges E1, ..., E4, En for five clocks U1, ..., U4, Un are shown explicitly.
- These five setting ranges E1, ..., E4, En which can be of the same or different sizes, overlap in at least one clock cycle value UT S , which is therefore the control target for the synchronization of at least these five clocks U1, ..., U4, Un can serve, since it can be set in all these clocks U1, ..., U4, Un. If and to the extent consequently the clocks U1,..., Un of the system from FIG. 1 overlap at least in such a common clock cycle value UT S , they can be stably synchronized with the present method.
- the inventive synchronization of the clocks U1, ..., Un is from time to time, e.g. at predetermined regular intervals, information from a respective network node to derive the currently set clock rate from the Given bus line 1, via which this clock pulse information can be received by the other network nodes.
- this clock pulse information can be received by the other network nodes.
- the Clock clock information of the respective on the bus line 1 A watch is then made up of one or more, preferably to synchronize all of the other network nodes Receive clock update of your own watch.
- This synchronizing clock pulse update process for a respective clock is illustrated in FIG. 4. As shown there is from the network node concerned on the bus line 1 upcoming information about the foreign clock cycle value of the clock one of the other network nodes received and after one not presented processing, in which of the foreign clock cycle value the normalization value subtracts one and thus the corresponding one Correction value A of the foreign clock cycle received is, first in a deviation filter to obtain an output signal A 'evaluated.
- the evaluation consists in determining whether the external clock cycle or correction value A lies within the own clock cycle setting range [F -1 , F 1 ]. If this is the case, the foreign clock cycle or correction value A is passed through unchanged as output signal A '. If this is not the case, it is further checked whether the external clock cycle or correction value A is within a lower, predefinable tolerance range [F -2 , F -1 ] following the lower end value F 1 of the setting range or within an upper one the upper setting range end value F 1 subsequent, predeterminable tolerance range [F 1 , F 2 ].
- the associated final setting range value F -1 or F 1 is used as output signal value A ', ie in this case the deviation filter 4 limits the external clock cycle or correction value A to the relevant final setting range value F -1 or F 1 . If, on the other hand, the external clock cycle or correction value A is not within the two tolerance ranges, ie that it lies above the upper end value F 2 of the upper tolerance range or below the lower end value F -2 of the lower tolerance range, the external clock cycle is ignored, ie filtered out.
- the detected strong deviation of the foreign clock cycle from the setting range of your own clock is displayed by the deviation filter 4 via an error output 4a as an error.
- FIG. 5 illustrates in diagram form the function of the deviation filter 4 on the basis of its working characteristic for the output signal value A 'as a function of the external clock cycle or correction value A, the latter being represented by the associated correction signal value as shown in FIG. 2.
- the output signal value A ' is equal to the input signal value A, in the lower tolerance range [F -2 , F -1 ] the output signal A' has the value F 1 , in the upper tolerance range [ F 1 , F 2 ] it has the value F 1 , and outside of that the error signal is generated and the clock clock received is not used for the synchronizing update.
- the output signal A 'of the deviation filter 4 becomes when the foreign clock cycle or correction value A in the setting range [F -1 , F 1 ] or at least in one of the two tolerance ranges [F -2 , F -1 ] or [F -1 , F 2 ] is used by a subsequent correction filter to generate an updated correction value K for one's own clock.
- This is done by adding a value to the previous correction value which is equal to the difference between the deviation filter output signal value A 'and the previous correction value divided by a predeterminable adaptation factor "factor K ", which is chosen to be greater than one.
- factor K predeterminable adaptation factor
- the normalization value one is then added again to the correction value K in order to obtain the clock clock value to be set.
- the other clocks will predominantly receive clock cycles on average, which gradually change its correction value in the direction of the synchronization value UT S so that it finally reaches this target value and is held there.
- the clocks U1, ..., Un automatically settle to a common center of gravity value of the overlapping setting ranges E1, ..., En as a common, synchronized clock cycle UT S due to the present synchronization method.
- the correction filter 5 is used to carry out a cyclical internal update of the correction value K and thus of the clock clock.
- a new correction value is determined cyclically by adding a value to the old correction value which is equal to the negative of the previous correction value divided by an associated further adjustment factor "factor 0 ", which in turn is suitably specified as a factor value greater than one and given Deviation of the previous correction value K from the initial setpoint determines the amount of the gradual change.
- This cyclical self-update ensures that the clock automatically returns to its specified target clock cycle belonging to the initial setpoint and remains there when there are no more synchronization requests from received clock cycles from other clocks.
- This initial or rest correction value is preferably in the middle of the setting or control range [F -1 , F 1 ]. So that the synchronization process is not impaired by the cyclical self-update, it is advisable to carry out the self-updates only at significantly longer intervals and with a given deviation, a significantly lower change value, ie a higher adaptation factor, than the synchronizing updates.
- the received clock cycles or more precisely the received clock clock correction values in the correction filter 5 are subjected to filtering relative to the current own clock clock or correction value in the manner of an improper low-pass filter for the purpose of synchronizing updating of the own clock clock or correction value.
- the correction filter 5 contains a real low-pass filter, which very slowly takes back the synchronizing correction.
- the filter functions are represented by the two adjustment factors "factor K " and "factor 0 ".
- adaptation factors "factor K " and "factor 0 " and the outer tolerance range end values F -2 , F 2 are set to values adapted to the respective application, so that a smooth, stable synchronization or Control behavior is achieved without major jumps in control.
- the final setting range values F -1 , F 1 can each be specified by a certain control distance F from the central zero position value as the idle deviation and the outer tolerance range end values F -2 , F 2 can be specified three times the value 3F from the zero setting value .
- narrower tolerance ranges can be specified for safe system operation, for example by the outer tolerance range end values F -2 , F 2 being only twice as far from the zeroing value as the setting range end values F -1 , F 1 .
- this synchronization method a number of advantages on. So it has a robust behavior towards clocks running slowly and too fast and it is fault tolerant in the sense that by the failure of one or more Clocks the synchronization process for the remaining clocks in none Way is disturbed.
- the number of tolerated, wrongly running Clocks are therefore not limited.
- the procedure works regardless of the number of people involved in the synchronization Clocks and is therefore universal without switching algorithms used. By optimizing free parameters is one standardized applicability. Control oscillations of the Synchronization can be done by slowly correcting everyone Avoid clocks.
- the procedure is very simple to implement, since per synchronizing update process always only one measured value, i.e.
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
- Fig. 1
- ein schematisches Blockschaltbild eines datenbusvernetzten Systems mit auf die Netzknoten verteilten, zu synchronisierenden Uhren,
- Fig. 2
- eine diagrammatische Darstellung der Funktionsweise der verteilt angeordneten Uhren mit einstellbarem Uhrentakt,
- Fig. 3
- ein Diagramm zur Veranschaulichung der verschiedenen Uhrentakt-Einstellbereiche der Uhren,
- Fig. 4
- ein Blockfunktionsdiagramm zur Darstellung von synchronisierenden Uhrentakt-Aktualisierungsvorgängen in jeder der Uhren und
- Fig. 5
- eine Diagrammdarstellung des Einstellbereichs und angrenzender Toleranzbereiche für eine jeweilige Uhr, wie sie für den Aktualisierungsvorgang gemäß Fig. 5 verwendet werden.
Claims (4)
- Verfahren zur Synchronisation mehrerer Uhren (U1, ..., Un) mit innerhalb jeweils zugehöriger Einstellbereiche (E1, ..., En) veränderbarem Uhrentakt,
gekennzeichnet durch
folgende Schritte:jeder Uhr (U1, ..., Un) wird von Zeit zu Zeit die Information über den momentanen, fremden Uhrentakt einer der anderen Uhren übermittelt undes wird festgestellt, ob der fremde Uhrentakt einer jeweiligen anderen Uhr innerhalb des eigenen Einstellbereiches ([F-1, F1]) liegt, und bejahendenfalls wird der eigene momentane Uhrentakt in Abhängigkeit von der Differenz zwischen dem fremden und dem eigenen Uhrentakt aktualisiert. - Verfahren nach Anspruch 1, weiter
dadurch gekennzeichnet, dass
die Aktualisierung des eigenen Uhrentaktes durch eine schrittweise Änderung mit einem von der Differenz zwischen dem übermittelten und dem eigenen Uhrentakt abhängigen Änderungswert vorgenommen wird. - Verfahren nach Anspruch 1 oder 2, weiter
dadurch gekennzeichnet, dass
für jede Uhr eine zyklische schrittweise Rückstellungsaktualisierung vorgesehen ist, durch welche der Uhrentakt um ein Inkrement aktualisiert wird, das von der Differenz des momentanen Uhrentaktes und einem vorgegebenen Uhrentakt-Eigensollwert abhängt, wobei die Rückstellungsaktualisierungen seltener und/oder mit kleineren Änderungswerten als die synchronisierenden Aktualisierungen erfolgen. - Verfahren nach einem der Ansprüche 1 bis 3, weiter
dadurch gekennzeichnet, dass
ein unterer Toleranzbereich ([F-2, F-1]) unten und ein oberer Toleranzbereich ([F1, F2]) oben an den Uhrentakt-Einstellbereich ([F-1, F1]) angrenzend vorgegeben und der empfangene Uhrentakt für eine synchronisierende Aktualisierung des eigenen Uhrentaktes unverändert verwendet wird, wenn er im eigenen Einstellbereich liegt, auf den jeweiligen Einstellbereich-Endwert (F-1 bzw. F1) begrenzt gehalten wird, wenn er im angrenzenden Toleranzbereich liegt, und ignoriert wird, wenn er außerhalb des Einstellbereiches und der Toleranzbereiche liegt.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2000141724 DE10041724A1 (de) | 2000-08-25 | 2000-08-25 | Verfahren zur Uhrensychronisation |
| DE10041724 | 2000-08-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP1186967A2 true EP1186967A2 (de) | 2002-03-13 |
| EP1186967A3 EP1186967A3 (de) | 2007-01-03 |
Family
ID=7653732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP01119500A Withdrawn EP1186967A3 (de) | 2000-08-25 | 2001-08-14 | Verfahren zur Uhrensynchronisation |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP1186967A3 (de) |
| DE (1) | DE10041724A1 (de) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102006012421B3 (de) * | 2006-03-17 | 2007-12-13 | Görlitz Ag | Verfahren zum Abgleich der Geräteuhr eines Energiemessgeräts |
| CN113589883B (zh) * | 2021-05-19 | 2024-04-19 | 浙江大华技术股份有限公司 | 信号调整方法、电子设备和计算机存储介质 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1195899A (en) * | 1967-11-21 | 1970-06-24 | Mini Of Technology | Improvements in or relating to Synchronising Arrangements in Digital Communications Systems. |
| AU549343B2 (en) * | 1981-06-08 | 1986-01-23 | British Telecommunications Public Limited Company | Phase locking |
| FR2676152B1 (fr) * | 1991-05-03 | 1994-10-14 | Renault | Procede, systeme et dispositif de synchronisation des horloges d'un reseau. |
-
2000
- 2000-08-25 DE DE2000141724 patent/DE10041724A1/de not_active Withdrawn
-
2001
- 2001-08-14 EP EP01119500A patent/EP1186967A3/de not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| DE10041724A1 (de) | 2002-03-07 |
| EP1186967A3 (de) | 2007-01-03 |
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