EP1186149A1 - Leitungstreiber für pots, xdsl, oder pots/xdsl integrierte schnittstelle - Google Patents

Leitungstreiber für pots, xdsl, oder pots/xdsl integrierte schnittstelle

Info

Publication number
EP1186149A1
EP1186149A1 EP00942738A EP00942738A EP1186149A1 EP 1186149 A1 EP1186149 A1 EP 1186149A1 EP 00942738 A EP00942738 A EP 00942738A EP 00942738 A EP00942738 A EP 00942738A EP 1186149 A1 EP1186149 A1 EP 1186149A1
Authority
EP
European Patent Office
Prior art keywords
driver
transformer
loop
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00942738A
Other languages
English (en)
French (fr)
Other versions
EP1186149A4 (de
Inventor
Mark Feeley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Catena Networks Inc
Original Assignee
Catena Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Catena Networks Inc filed Critical Catena Networks Inc
Publication of EP1186149A1 publication Critical patent/EP1186149A1/de
Publication of EP1186149A4 publication Critical patent/EP1186149A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56Modifications of input or output impedances, not otherwise provided for
    • H03F1/565Modifications of input or output impedances, not otherwise provided for using inductive elements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0266Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0002Modulated-carrier systems analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M11/00Telephonic communication systems specially adapted for combination with other electrical systems
    • H04M11/06Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
    • H04M11/062Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors using different frequency bands for speech and other data
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/26Systems using multi-frequency codes
    • H04L27/2601Multicarrier modulation systems

Definitions

  • the present invention relates to the field of voice and data communications system and more particularly to interface circuits for coupling a combination of telephony and high-rate data communications functions to a 2- wire telephone loop.
  • a loop is a twisted-pair copper telephone line. Loops can differ in distance, diameter, age, and transmission characteristics, depending on the network. These loops are a natural conduit for provision of high speed digital communications services due to the large installation base that already exists. Digital transmission systems on these loops include asymmetric, symmetric, high-rate, and very high-rate digital subscriber loops, conventionally known as ADSL, SDSL, HDSL, and VDSL respectively. Normally these and other similar protocols are known as xDSL.
  • ADSL is intended to co-exist with traditional voice services by using different frequency spectra on the loop.
  • multiple different transmission schemes may be employed in different frequency bands on the same loop, and that these transmission schemes may include traditional analog voice services as well as current and new forms of xDSL.
  • POTS plain old telephone services
  • the ADSL uses the frequency spectrum between 30kHz and 1.1MHz for data over the telephone line. This is shown schematically in figure la.
  • ADSL also partitions its frequency spectrum with upstream (subscriber to CO) transmission in a lower frequency band, typically 30kHz to 138kHz, and with downstream transmission in a higher frequency band , typically 138kHz to 550kHz or 1.1MHz.
  • ADSL uses a discrete multi- tone (DMT) multi-carrier technique that divides the available bandwidth into approximately 4kHz sub-channels.
  • DMT discrete multi- tone
  • the architecture, interfaces and protocols for telecommunications networks incorporating ADSL modems is shown in figure lb.
  • the elements consist of one of more ATU-C's 2 or ADSL modems at a central office end 4.
  • the ATU-C 2 can be integrated within an access node 6 which is the concentration point for broadband data 8 and narrowband data 10.
  • the access node 6 can be located at a central office, or a remote site. Also a remote access node can subtend from a central access node.
  • the ATU-C's 2 are coupled via a splitter 12 to the telephone loop 14.
  • the loop 14 at the customer end is also coupled via a splitter 12 to the telephone loop 14.
  • the loop 14 at the customer end is also coupled via a splitter 12 to an ATU-R 16 or an ADSL modem at the customer end that can be integrated within an SM (Service Module) which are devices that perform terminal-adaptation functions. Examples are set top boxes, PC interfaces, or LAN routers.
  • the PSTN (Public Switched Telephone Network) 18 to the subscriber phones 20 shares the loop 14 via the splitter 12 which isolate the POTS form the ADSL modems.
  • an analog splitter 24 provides the filtering required to separate the POTS and ADSL bands before being input to their respective transceivers.
  • the splitter 34 consists of a low pass filter 36 between the telephone and the loop and a highpass filter between the ADSL transceiver and the loop.
  • the low frequency components output form the LPF are sent to the conventional telephone line card.
  • These analog signals are converted to digital signals and encoded as PCM signals by and AID CODEC. These signals may then be combined with other PCM signals and transmitted to other central offices or switching networks.
  • the splitter is generally a very bulky and expensive component. A number of solutions have been proposed to eliminate the splitter. For example, US Patent No. 5,757,803 describes an improved splitter, while US Patent No. 5,889,856 describes an integrated ADSL line card with a digital splitter.
  • the function of the POTS splitter is only to separate the different frequency bands and send them to their respective transceiver.
  • the actual function is more complex and deals with the need to provide the correct impedance in different frequency bands in order to allow the signals to properly propagate and meet the relevant specifications.
  • the conventional POTS splitter does eliminate or reduce the effects of interference from the POTS and ADSL equipment, a properly designed interface may eliminate these problems with adding the low or high pass filters in the signal path.
  • the invention seeks to provide a solution to the general problem of requiring a POTS splitter in an integrated line interface module and, in particular, at the central office or "head end".
  • An advantage of the present invention is that it may be used for a combined telephony and digital subscriber loop ("DSL") service or other communications systems where the telephony and data, or different types of data, occupy different frequency spectra on a 2-wire communication line.
  • DSL digital subscriber loop
  • a further advantage of the invention is to eliminate the traditional POTS splitter and to provide a broadband loop driver and termination that allows frequency dependent impedance synthesis to be implemented using highly integrated circuits using either digital, analog or a combination of digital and analog means.
  • a further advantage of the invention is to minimize power, cost and size for delivering integrated voice and data.
  • a drive circuit comprising a transformer having a primary winding for coupling to a subscriber loop and a secondary winding for coupling to an interface circuit; a feedback circuit for coupling the primary winding to the secondary winding to provide a predetermined impedance match between the interface circuit and the loop over a predetermined frequency band of the circuit.
  • Figure 1(a) is a diagram showing the frequency spectrum of an ADSL system
  • Figure 1(b) is a schematic diagram of an ADSL system architecture
  • Figure 2 is a schematic diagram of a prior art ADSL modem
  • Figure 3 is a schematic diagram of a prior art DSL transceiver
  • Figure 4 is a schematic diagram of an ADSL modem according to an embodiment of the present invention
  • Figure 5 is a schematic block diagram of the an ADSL modem according to an embodiment of the present invention
  • Figures 7(a)-(f) are schematic diagrams of drive circuits according to embodiments of the present invention.
  • Figures 8 (a)-(f) are detailed schematic circuit diagrams of the circuits in figures 7(a)-(f).
  • a DSL central office system is shown generally by numeral 20.
  • the system comprises an ADSL transceiver 21 for processing digital data, a POTS splitter 34, and a POTS transceiver incorporating a SLIC (subscriber line interface circuit) 26 and a CODEC 22 for processing voice data.
  • the POTS splitter 24 is coupled to a subscriber loop 28 which then splits off the voice signal and provides it to the SLIC and CODEC 22 and a high frequency data signal to the ADSL transceiver 21.
  • the ADSL transceiver includes a DSL baseband circuit 31 coupled to the broadband data path, a DSL analog front-end (AFE) 33 which is fed from the DSL baseband circuit couples to the splitter 24 via a loop driver.
  • the ADSL transceiver provides bi-directional communication between the broadband data path and the loop.
  • the digital processing circuits provide for the digital signal processing function such a modulation, echo cancellation and equalization.
  • the AFE includes both transmit and receive channels.
  • the transmitter channel consists of a digital to analog converter (D/A) coupled to the broadband data bus, transmit filters, followed by a line driver coupled through a hybrid to the splitter.
  • D/A digital to analog converter
  • the receive channel includes a receive filter coupled to the hybrid, a programmable gain amplifier driving an analog to digital converter, which in turn outputs digital signal to the digital processing unit onto the broadband data path.
  • Both the transmit and receive channels are couple to the splitter which is in turn coupled by a transformer to the loop.
  • the present invention involves modification to this conventional arrangement by integrating the voice/data analog front end (AFE) 42 and the voice/data baseband 44 with a common loop driver 46 as shown schematically in figure 4.
  • the integrated unit thus provides bi-directional communication between the loop and a system bus or busses carrying ADSL and PCM data. If this integrated approach is taken, the frequency dependent termination in each frequency band must be synthesized by the AFE 42, the baseband 44, or a combination of the two. Further, the loop driver must provide relatively flat response over the full range of frequency bands, which in an integrated POTS and ADSL application would be from 200Hz to l .lMHz.
  • the AFE 42 includes a loop driver 52 coupled to the loop, a wide band AFE 54 possibly including impedance synthesis and coupled to the loop driver 52, and A/D and D/A converters 56.
  • the AFE thus provides bi-directional communication between the loop and the digital processing section 44 and may provide full or partial frequency dependent impedance synthesis.
  • the digital processing section 44 may include a digital impedance synthesis unit
  • the unit performs either full or partial impedance synthesis required for the composite system and provides frequency dependent filtering and equalization.
  • the composite signal is coupled to a baseband processing unit comprising one or more DSP based processing elements which implement the voice CODEC 60 and ADSL modem 62 functions.
  • the baseband processing unit is coupled to one or more system busses carrying a high speed ADSL data and PCM voice signals.
  • a feature of this architecture is a broadband loop drive circuit which allows the integration of the complex impedance synthesis function in highly integrated digital or analog circuit.
  • the loop driver provides DC feed capability of up to 100mA; flat or nearly flat frequency response between 200Hz and l.lMHz or beyond; balanced loop drive; AC signal swing of up to 22V peak; and low power dissipation.
  • One approach in the prior art is to utilize a broadband SLIC implemented in a high voltage integrated circuit technology.
  • the SLIC needs to carry both DC loop currents, low frequency voice signals, and high frequency data signals.
  • This approach suffers from a variety of problems including excessive power dissipation because of the large signal currents and signal voltage headroom required on the driver amplifiers; difficulty of implementation in silicon technologies; and limited loop range with 48V battery feed.
  • a preferred approach is to use a transformer based drive circuit for coupling the integrated voice/xDSL unit to the loop.
  • the primary difficulties in using a transformer- based solution are caused by transformer roll-off at low and high frequencies because of a combination of primary inductance, leakage inductance and interwinding capacitance and core limitations.
  • FIGS. 7(a)-(f) various transformer based drive circuits for coupling the integrated voice/xDSL unit to the loop are shown. All seek to avoid the problems caused by transformer limitations by using feedback techniques to linearize the performance of the circuits in this application.
  • a transformer configuration is shown having a feedback loop for overdriving the input.
  • a pair of transformers is provided, with a high frequency feed forward on the second transformer.
  • Figure 7(d) is a variation of the configuration of figure 7(c) wherein a high frequency feed forward with a capacitor is provided.
  • two transformers are provided with a separate drive to the second transformer.
  • a broadband transformer has a split primary with the first winding and a second winding having polarities in the manner shown.
  • the transformer has a single secondary winding 104.
  • the primary refers to the loop side of the line feed transformer and the secondary refers to the voice/xDSL modem side of the transformer.
  • the transformer's primary to secondary turns ratio is preferably about 1 :1 but can be other ratios.
  • the line transformer is a 1 : 1 which must maintain a magnetizing inductance of lOOmH to 2H while carrying 20mA to 100mA in the primary winding.
  • the typical AC voltage swing is up to 22 volts peak, while the impedance looking onto the loop is in the order of 900 ohms in the voice band and 100 ohms in the ADSL band.
  • an interface circuit (not shown) provides an input V, to a driver circuit 180 which is coupled to a twisted pair telephone loop having TIP and RING leads which generally extend between the central office and customer premises.
  • the drive circuit includes a transformer having a pair of primary windings coupled to the respective TIP and RING lines by a respective line feed elements R feed which are typically 50 ohms. The other ends of the primary windings are connected to respective battery return or TIP DC and a talk battery or RING DC.
  • the input voltage V is provided to each terminal of the secondary via respective inverting opamps.
  • the first primary winding 106 is coupled at one end to a feed resistor 107 coupled one of the loop conductors TIP, while the second primary winding 108 is coupled to a feed resistor 110 coupled to the second of the loop conductors RING.
  • the differential voltage at the primary side is sensed and fed back to the secondary side.
  • the feedback circuit senses the differential output voltage Vo on the primary side of the transformer, compares that differential output voltage Vo to the desired output voltage Vi, and multiplies the error signal by a high gain to generate a feedback signal Vf and drives the secondary of the with the signal Vf to provide increased drive to the transformer.
  • the differential voltage at the primary side is sensed and fed back to the secondary side.
  • the feedback circuit senses the differential output voltage Vo on the primary side of the transformer, compares that differential output voltage Vo to the desired output voltage Vi, and multiplies the error signal by a high gain to generate a feedback signal Vf and drives the primary side of the transformer with Vf through capacitors.
  • the secondary side of the transformer is driven by the desired input voltage Vi.
  • the differential voltage at the primary side is sensed and fed back to the secondary side.
  • the feedback circuit senses the differential output voltage Vo on the primary side of the transformer, compares that differential output voltage Vo to the desired output voltage V warrant and multiplies the error signal by a high gain to generate a feedback signal V f and drives the primary side of the transformer with complimentary signals V f through respective capacitors.
  • the secondary side of the transformer also driven by the feedback signal V f .
  • the differential voltage at the primary side is sensed and fed back to the secondary side.
  • the feedback circuit senses the differential output voltage Vo on the primary side of the transformer, compares that differential output voltage Vo to the desired output voltage Vi, and multiplies the error signal by a high gain to generate a feedback signal Vf and drives the primary side of the transformer a second transformer coupled through capacitors.
  • the signal Vf drives the secondary of the second transformer and the primary windings of the second transformer are capacitively coupled to the output voltage Vo.
  • the secondary side of the first transformer is driven by the desired input signal Vi.
  • the differential voltage at the primary side is sensed and fed back to the secondary side.
  • the feedback circuit senses the differential output voltage Vo on the primary side of the transformer, compares that differential output voltage Vo to the desired output voltage Vi, and multiplies the error signal by a high gain to generate a feedback signal Vf and drives the primary side of the transformer a second transformer coupled through capacitors.
  • the signal Vf drives the secondary of the second transformer and the primary windings of the second transformer are capacitively coupled to the output voltage Vo.
  • the secondary side of the first transformer driven by the output signal Vf.
  • Figure 8(g) is similar to figure 8(f) except that an impedance is also added between the primary windings of the first transformer and the output voltage Vo.
  • the two transformers can be configured to provide drive in different frequency bands, with the crossover frequency determined by the impedances in series with the two transformers.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Telephonic Communication Services (AREA)
  • Interface Circuits In Exchanges (AREA)
EP00942738A 1999-06-10 2000-06-09 Leitungstreiber für pots, xdsl, oder pots/xdsl integrierte schnittstelle Withdrawn EP1186149A4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA2274171 1999-06-10
CA 2274171 CA2274171A1 (en) 1999-06-10 1999-06-10 Loop driver for pots, xdsl, or integrated pots/xdsl interface
PCT/US2000/015992 WO2000078013A1 (en) 1999-06-10 2000-06-09 Loop driver for pots, xdsl, or integrated pots/xdsl interface

Publications (2)

Publication Number Publication Date
EP1186149A1 true EP1186149A1 (de) 2002-03-13
EP1186149A4 EP1186149A4 (de) 2004-09-15

Family

ID=4163618

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00942738A Withdrawn EP1186149A4 (de) 1999-06-10 2000-06-09 Leitungstreiber für pots, xdsl, oder pots/xdsl integrierte schnittstelle

Country Status (5)

Country Link
EP (1) EP1186149A4 (de)
JP (1) JP2003502915A (de)
AU (1) AU5732100A (de)
CA (1) CA2274171A1 (de)
WO (1) WO2000078013A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6760433B2 (en) 2000-05-15 2004-07-06 Centillium Communications, Inc. Central office interface techniques for digital subscriber lines
US6826278B2 (en) * 2000-05-15 2004-11-30 Centillium Communications, Inc. Central office interface techniques for digital subscriber lines
US6831527B2 (en) 2002-12-17 2004-12-14 Adc Telecommunications, Inc. Insertion box
DE102005005538B4 (de) * 2005-02-07 2007-04-05 Infineon Technologies Ag Leitungstreiberschaltung mit hohem Wirkungsgrad
US8896351B2 (en) 2008-03-19 2014-11-25 Lantiq Deutschland Gmbh Line driver method and apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598467A (en) * 1994-12-09 1997-01-28 National Semiconductor Corporation Signal interface circuit with selectable signal interface parameters
WO1998058458A1 (en) * 1997-06-17 1998-12-23 Paradyne Corporation A method and apparatus for controlling the input impedance of an analog front end circuit of a data communications equipment (dce) device
US5910970A (en) * 1996-05-09 1999-06-08 Texas Instruments Incorporated MDSL host interface requirement specification

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5515433A (en) * 1994-08-30 1996-05-07 Reltec Corporation Resistance forward telephone line feed circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598467A (en) * 1994-12-09 1997-01-28 National Semiconductor Corporation Signal interface circuit with selectable signal interface parameters
US5910970A (en) * 1996-05-09 1999-06-08 Texas Instruments Incorporated MDSL host interface requirement specification
WO1998058458A1 (en) * 1997-06-17 1998-12-23 Paradyne Corporation A method and apparatus for controlling the input impedance of an analog front end circuit of a data communications equipment (dce) device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO0078013A1 *

Also Published As

Publication number Publication date
AU5732100A (en) 2001-01-02
EP1186149A4 (de) 2004-09-15
WO2000078013A1 (en) 2000-12-21
JP2003502915A (ja) 2003-01-21
CA2274171A1 (en) 2000-12-10

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