Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
  • H05B41/14—Circuit arrangements
  • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
  • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
  • H05B47/10—Controlling the light source
  • H05B47/175—Controlling the light source by remote control
  • H05B47/185—Controlling the light source by remote control via power line carrier transmission

Definitions

• This invention relates to power controllers and more specifically relates to a power controller, using digital implementation with such stand-alone features as automatic shut down; dead time control, close to inductive side driving; and filament connections.
• Power controllers are well known and normally employ analog techniques. Digital techniques are normally avoided where smooth control is desired, for example, in controlling the dimming gas discharge lamps such as fluorescent lamps in an electronic ballast.
• the present invention provides a novel digital implementation for power control circuits, particularly for the control of fluorescent lamp dimming.
• I. Inflexible driving algorithm Optimal driving of power switches (MOSFETs, bipolar, transistors, thyristers, IGBTs and the like) requires complex algorithms based on non-linear multiple stage and variable functions, with a variety of predetermined parameters being chosen as the circuitry's physical parameters change.
• a fluorescent ballast power controller flexible algorithms are desired to supply special loads when: a) a complex working regime for fluorescent lamps including the preheat startup operation is needed. b) Non-linear or special operation requirements for the fluorescent lamp complying to its V/I working curve, and as a function of the dimming decision table to provide the best operation at all light levels. c) Flexibility to enable use of different lamp configurations (types and numbers of lamps) and different mam voltages .
• the present invention provides a number of novel improvements which can be integrated into a simple system, or, in some cases can be used singly in a stand- alone circuit. These improvements are:
• DSP digital signal processing
• the predetermined fixed internal parameters above refer to a set of numbers and tables intended for: limits, constants ,. parameters and signed coefficients included in the control loop algorithm; and addressing/identification; etc.
• An externally programmable new parameters table is provided that can be set for a specific application that cannot use the already existing tables (for example: an EEPROM function).
• ASIC application specific integrated circuit
• a gate array which includes the fast algorithms or the fast portion of them, like:
• a very low-end microprocessor processes all the jobs by time-sharing instead of using the superscalar processor used in DSPs.
• a gate array carries out all of its assignments in parallel. Functionally, the assignments operate m parallel and require separate gate array sections or blocks for each one.
• the microprocessor manages the gate array operation, among others.
• the gate array receives input from monitoring nets and operates the immediate algorithm C protections. In the case of fluorescent lamp dimming, the job is done by using all the main ASIC elements A/D, microprocessor, and gate array. In the embodiment described, the gate array also carries out watchdog functions.
• the microprocessor monitors protections being operated and takes care of long term actions.
• the algorithm implemented in the gate array carries out the fast sub-functions which include fast pulses or actions.
• the sub-functions which require processing or actions that can be carried out during a slower mode, are carried out by the microprocessor.
• the novel structure and process of the invention provide a programmable integrated digital control module which can be used for a dimming fluorescent ballast.
• the control module features are :
• Dimmable Electronic Ballast (DEB) ASIC on a programmable printed circuit board product for new lighting ballast designs and evaluation suitable for low to medium volume production.
• An EEPRO enables the control parameters described above to use a single hardware platform for multiple lamps, diverse operation regimens and applications .
• Integrated software defaults predefined parameters to a 2-lamp 32w/36w lamp drive for 120/230V a-c line/mains .
• a modified critical -mode boost PFC control achieves lowest total harmonic distortion (THD) at all light levels.
• a series resonant lamp inverter control achieves less than 1% current-level control as required for architectural dimming fluorescent ballasts.
• Module flexibility speeds product redesign and field testing in advance of custom ASIC software specification suitable for high-volume ballast products.
• ballast control circuit A large number of other features can be incorporated into the novel system of the invention, as integral parts of the system, or as stand alone features which could be incorporated into any ballast control circuit. These include:
• a novel shut down circuit for turning off power to ballast in response to the sensing of a common mode high frequency current which exceeds a given value .
• an added winding is wound on the common mode choke to sense a high frequency ground fault current and turn off power to the ⁇ ballast in response thereto.
• a series/parallel circuit is provided which enables energization of the lamp filaments with a half wave rectified DC.
• a control arrangement for DC to AC inverters for driving non-linear loads such as electronic ballasts for high pressure and low pressure gas discharge lamps, resonant power supplies and laser power supplies and the like, wherein the control scheme employs both variable pulse width and frequency modulation, driving the load as close to resonance as possible but en the inductive side of resonance.
• Both the high side and low side switches of the bridge are independently controlled in this arrangement.
• a novel protection circuit for a bridge connected (half or full wave) inverter which supplies a resonant load such as a resonant electronic ballast for gas discharge lamps, which forces a dead-time during which no switch is driven in conduction without limiting the performance of the circuit .
• the point at which a dynamic dead-time begins is sensed by sensing the point where current collapses to zero in a capacitive timed circuit case.
• the sensing circuits may sense inductor current using a current transformer or shunt resistor, by sensing the current through the switching devices, by sensing the bridge v ltage or by sensing the bridge voltage dv/dt .
• an electronic ballast for a gas discharge lamp s provided in wmch the electronic ballast has an input a-c circuit, a common mode inductor for connecting said input a-c circuit to a bridge connected rectifier, an inverter circuit including a high side switch and a low side switch which is coupled to the bridge connected rectifier, and a resonant circuit coupling the inverter circuit to and driving the gas discharge lamp.
• a monitor circuit is coupled to the common mode inductor for sensing a high frequency fault ground current, which has a frequency greater than the frequency of the input a-c circuit, to a- ground connection.
• a controller circuit is coupled to the monitor circuit for turning off the inverter circuit or the power to the inverter circuit when the high frequency ground current exceeds a given value .
• an electronic ballast for at least two parallel connected gas discharge lamps removably mounted m a fixture which there is an inverter circuit, a resonant coupling circuit and at least two gas discharge lamps .
• the gas discharge lamps have first and second filaments.
• the resonant coupling circuit includes an inductor and a capacitor connected in series with the first and second filaments.
• First and second windings are coupled to the inductor and first and second diodes are connected m series with the first and second windings respectively and t ⁇ e first and second diodes respectively, whereby the disconnection of the lamps and the filaments from their fixtures opens the output circuit from c ⁇ *e inverter circuit .
• an electronic ballast for a gas discharge lamp in which there is an input a-c circuit.
• An a-c filter is connected to the input a-c circuit.
• a rectifier bridge is connected to the a-c circuit for producing an output d-c voltage from the a-c circuit input.
• An inverter circuit including a high side switch and a low side switch is connected in series at a node and connected across the output of the inverter circuit and a load circuit is connected to the node and includes the gas discharge lamp.
• the high side and low side switches each comprise MOSgated devices, and the like, having input control terminals energizable to turn them on and off and each has a parallel diode.
• a master control circuit applies suitably timed control signals for alternately turning the high side and low side switches on and off.
• a dynamic dead time control circuit in provided in the master control circuit for insuring only a short interval between the end of current conduction by either the high side and low side MOSgated devices, and the like, and the beginning of conduction by the other by the control of the application of controls signals to their control terminals.
• the dynamic dead time control circuit is coupled to and monitoring at least one of the current in the resonant load, the current in the first and second switches, the output voltage of the rectifier bridge or the rate of change dv/dt of the bridge voltages, and adjusts the application of turn on signals to the high side and low side switches for both capacitive and induqtive operations .
• an electronic control module for controlling the operation of an electronic ballast for at least one lamp
• the control module has an integrated circuit operable in accordance with control information to drive a first switch and a second switch to power the at least one lamp using a combination of pulse width modulation and frequency modulation.
• a first memory is coupled to the integrated circuit, the first memory storing a plurality of parameters tables, each parameters table having the control information for the integrated circuit .
• an integrated circuit for controlling the operation of an electronic lamp ballast is provided in which a central logic supervisor controls the overall operation of the electronic lamp ballast.
• a dc/ac generator module is coupled to the central logic supervisor and provides drive signals for an inverter circuit, the inverter circuit having a first switch and a second switch.
• a power line communication module is coupled to the central logic supervisor and receives dimming control data across a power line.
• a power factor correction module is coupled to the central logic supervisor and controls power factor detection and correction for the electronic lamp ballast.
• a method for controlling the dimming operation of an electronic ballast is provided m which a current
• Figure 1 is a prior art electronic ballast circuit which presents a hazard in the presence of a high frequency, high voltage ground fault.
• Figure 2 shows a novel circuit to provide high frequency hazard protection and is an improvement of the circuit of Figure 1.
• Figure 3 is a circuit diagram of a lamp ballast with a known serial connection of lamp filaments.
• Figure 4 shows a circuit diagram of a lamp ballast with a known parallel connection of lamp filaments .
• Figure 5 shows an improvement of the circuit of Figures 1 and 4 and is a novel circuit arrangement for a lamp ballast employing a novel series/parallel connection of filaments.
• Figure 6 shows a known generic half -bridge ballast circuit operated in a near resonance operation.
• Figure 7 shows the voltages and currents in the circuit of Figure 6 on a common time base for a reactive phase condition.
• Figure 8 shows the voltages and currents in the circuit of Figure 6 for a capacitive phase condition.
• Figure 9 shows the circuit of Figure 6 adapted 5 with a novel current sense protection circuit.
• Figure 10 shows the circuit of Figure 6 with a novel voltage sense protection circuit.
• FIG. 11 shows the circuit of Figure 6 with a novel dv/dt sense protection circuit.
• Figure 12 shows the curves of Figure S, using a novel continuous reactive load mode of operation. 5
• Figure 13 shows the curves of Figure 12, modified by a novel use of predicted minimum dead time.
• Figure 14 shows a novel voltage sense protection C circuit (Figure 10) for an. electronic ballast.
• Figure 15 is a block diagram of a preferred ASIC which can be used to control the circuit of Figure 14.
• Figure 16 is a block diagram of a full control module using the circuits of Figures 14 and 15.
• Figure 18 is a block diagram of the silicon topology nl 7 he ASIC of Figures 14 and 15.
• Figure 19 shows relevant voltage and current curves produced by the ASIC of Figure 18.
• Figure 20 is a diagram of light level versus current in which the curve is divided inl.o matched segments of the conventional non-linear curve.
• Figure 21 is an interconnect diagram of a PLC Remote Controlled Dimmable Ballast.
• Figure 21A is a schematic diagram of the ASIC used in Figure 20.
• Figure 22 shows the ASIC pin assignment for
• Figure 23 is a Wall Control Unit schematic diagram for the diagram of Figure 21.
• FIG. 24 is a further electrical diagram of the ballast control, module of the invention.
• FIG. 25 is an electrical diagram of the ballast olatform with control module. DETAILED DESCRIPTION OF THE DRAWINGS
• Figure 1 schematically shows a prior art electronic ballast circuit in which an AC input line is connected to a full wave bridge connected rectifier circuit 30 through a common mode choke 31.
• the windings of the common mode choke or inductor 31 both have stray capacitances associated therewith as shown.
• the output of bridge 30 may be connected to a DC-to-DC power factor converter circuit 33 which has one output connected to the V ss bus and another output to the V cc bus.
• a high side switching MOSFET (or other MOS controlled device such as an IGBT) Q is connected to the V cc bus and a low side switching MOSFET Q 2 is connected to the V ss bus.
• MOSFETs Q x and Q 2 are suitably controlled to alternately turn MOSFETs Q x and Q 2 on and off with controlled frequency, duty cycle and/or phase delay.
• Output node 35 is then connected to a resonant load, which, in Figure 1, consists of blocking capacitor 40, inductor 41, parallel capacitor 42 and fluorescent lamp 45 having filaments 43 and 44.
• a resonant load which, in Figure 1, consists of blocking capacitor 40, inductor 41, parallel capacitor 42 and fluorescent lamp 45 having filaments 43 and 44.
• the line conductors in Figure 1 are connected to ground 46 through capacitors 47 and 48.
• the hazard caused by the low frequency (50/60 Hz) is generally treated with a residual current sensor (not shown) .
• the high fre ⁇ uency (20-100Khz) voltage used in electronic ballasts might be dangerous because the voltages are high (especially during the ignition period) and the gas in the tube behaves like a - ⁇ large capacitor.
• FIG. 2 shows the novel circuit for avoiding the above hazard problem.
• a novel additional winding 60 is added to the common mode choke 31. Winding 60 is connected through diode 61 to a controller 62 which is adapted to sense a fault condition. If winding 60 senses a common mode high frequency current higher than a safe value, controller 62 applies a "shut-down" signal to converter 33, thereby shutting down the DC/AC power bridge. Details of a typical converter and DC/AC power bridge which could be used with this invention are later described herein. II. DC Filament Supply Circuit for Safe Parallel Lamp Operation.
• a fluorescent lamp has two filaments at its two sides.
• lamp 45 has filaments 43 and
• the heating current flows through the resonance circuit formed by inductor 41 and capacitor 42.
• the voltage on the lamp Prior to ignition and during a phase the voltage on the lamp should be low (under the ignition voltage) . Therefore the operating frequency should be significantly above resonance. At that frequency the current is determined by inductor 41 and might be too low to produce adequate filament heating. At and after ignition the current through the filament is adequate.
• FIG. 4 shows a prior art parallel connection of filaments 43 and 44.
• the inductor 41 has additional windings 70 and 71 which are used a supply a heating voltage to filaments 43 and 44 (rather than a series) current.
• This circuit provides an adequate current through the full lamp operating mode, but it has a serious drawback. That is, when a lamp is taken out of its housing, current still flows through the resonance circuit 41 and 42 and might damage the ballast especially when it is used to drive two parallel lamps.
• windings 70 and 71 of Figure 4 are reconnected as shown and are connected to filaments 44 and 43 respectively through diodes 75 and 76 respectively.
• This approach applies parallel heating to the filaments and connects the lamp in such a manner that pulling it out of the housing will open the lamp circuit.
• the result is a serial-parallel combination, the parallel segment feeding the lamp 45 with a half wave rectified DC wave form.
• the diodes 75 and 76 are connected in such a manner that whenever the lamp 45 is pulled out, current flow is blocked.
• connection of a second lamp 45 is shown in phantom lines in Figure 5. Under this arrangement, the removal of one of the lamps still allows the remaining lamp (or lamps where more than two lamps are driven) to operate. The removal of all lamps blocks the current flow.
• Figure 6 shows a "generic" naif -oridge circuit for driving any desired resonant load, such as an electronic ballast.
• the half-bridge consists of the high side and low side MOSgated devices, and the like, such as MOSFETs Q x and Q 2 respectively.
• MOSFETs Q, and Q 2 are snown with conventional parallel body diodes 80 and 81 respectively and load 82 can be any desired resonant load such as gas discharge lamp.
• the circuit of Figure 6 is a resonant topology and tne wor ⁇ regime is near resonance; that is, close to the resonant frequency of inductor 41 and capacitor 42.
• the invention to be described is suitable for any application in which a reactive current might flow through the bridge Q 1; Q 2 . Note that everything described below applies to a full bridge topology as well as the half-bridge shown in Figure 6.
• Figure 7 shows relevant voltages and currents in the circuit of Figure 6 on a common time axis when the excitation fre ⁇ uency of MOSFETs Q : and Q 2 is above the resonant frequency of inductor 41 capacitor 42 and load 82. In this condition the load is reactive.
• line 100 is tne HO signal to Q x and l ne 101 is the LO signal to Q 2 .
• the bridge voltage at node 35 is shown by line 102 and the bridge current is shown by line 103.
• FIG. 8 shows the behavior of the inverter bridge of Figure 6 when the excitation fre ⁇ uencv is below resonance (and the load is therefore called capacitive) .
• the various traoes of Figure 8 have the same numerals as those of Figure 7.
• the dead time should be long enough to provide protection for the switching devices, but, on the other hand, inserting a large dead time w ll deteriorate the performance of the bridge by limiting the duty cycle. It also limits the ability of the bridge to operate near resonance. Thus, the common solution is a compromise offering insufficient protection at the cost of limited performance .
• a variable dead time is provided that adapts itself to circuit needs. This dead time is termed a "dynamic dead time.”
• the dynamic dead time is achieved by sensing the point where the current collapses to zero m a capacitive case.
• Figure 9 shows the use of a current sense protection circuit in which a current transformer 110 is provided to monitor the bridge current.
• Figure 9 also shows the control module 111 which provides the LO and HO outputs to MOSFETs Q 2 and Q x respectively.
• This current measuring function can also be carried out by current transformers (not shown) in series with Q : and Q 2 or by the shunt resistor 112 in the Vss Bus. These current measurement devices are then connected to comparator 113 in control module 111. Any "ringing" sensed by comparator 113 close to the end of the current conduction period can be controlled by a regenerative circuit such as a Schmidt trigger, a flip-flop or a bus-holder.
• Figure 10 shows the circuits of Figures 6 and 9 modified for a voltage sense protection mode.
• a connection is made from node 35, through resistor 115 to comparator 111.
• That inversion is sensed by means of a voltage comparator (line 102, Figure 8) .
• a dead time is inserted from the period of the switcn being closed till the inversion of pridge voltage (line 102, Figure 8) .
• Any "ringing" sensed by the comparator 113 " near the end of the current conduction period can be controlled by a regenerative device such as a Schmidt Trigger or flip-flop or a bus holder (not shown) .
• Figure 11 shows a dv/dt sense protection scheme which provides a capacitor 117 coupled from node 35 to a logic gate 118 within control module 111.
• a control module connection is provided from resistor 119 to a node between diodes 120 and 121.
• the circuit of Figure 11 is a modification of the voltage sensing control of Figure 10 and is suitable for digitally controlled DC/AC Bridges*.
• This embodiment uses a logic gate 118 instead of the comparator 113, which is basically an analog device.
• Figure 14 shows a specific circuit diagram of a voltage sense protection system for a fluorescent lamp ballast ( Figure 3 ⁇ and 10) in conjunction with a specific ASIC 130 for providing all control signals.
• Figure 15 is a block diagram of the ASIC 130, which will later be more specifically described.
• Figure 16 shows the full control module, including the circuits of Figures 14 and 15.
• PWM pulse width modulation
• FM frequency modulation
• the various modules in ASIC 130 are interconnected within the ASIC (see Figure 15) to a central logic supervisor.
• the central logic supervisor controls the overall operation of ASIC 130 by facilitating communications and passing data between modules .
• both pulse width and fre ⁇ uency modulation are employed and are constantly varied in order to dim the lamp and/or to maintain a high quality control regime.
• the goal is to work as close as possible to resonance but to be at the inductive behavior shown n Figure 7, under transients, lamp aging, malfunctions, use of a non- compatible lamps, etc.
• the novel method is combined with a center tap protection solution that prevents, "pulse by pulse", being accidentally reflected into the inverter's bridge as the capacitive load, shown m Figures 12 and 13.
• the novel algorithm for controlling the bridge when used for dimmable electronic ballasts controls the preheat, ignition and dimming control functions.
• a constant width pulse is used for the lower switch Q 2 of the bridge, and a pulse of variable width is used for the upper switch Q x .
• This control scheme is shown m Figure 17 which shows light level as a function of pulse width Ton for the high side and low side switches Q. and Q 2 in figures 6 and 14 to 16.
• low side curve 141 is employed for constant pulse 'width, but any of the alternates curves 142 can be used.
• Figure 17a further explains the high side switch behavior- shown in Figure 17. In Figure 17a, the terms shown are defined as fellows:
• the aim of the half-bridge drive algorithm is to keep the half-bridge load inductive but close to resonance at all operation regimes.
• the novel method is to drive the switches under reverse [parallel diode) conduction, when switch voltage is close to zero.
• the high side drive rising edge must come during the Tl time frame.
• the algorithm must keep time Tl short in order to be close to resonance but never zero or negative which is the expression of capacitive load to the half bridge.
• the algorithm provides high and low side drives that preserves a short fixed Tl . during steady state conditions. If however, during transients the Tl shortens and gets close to zero, then, the center tap mechanism will bring it back to a safe length or duration.
• the novel method allows independent control of each one of the bridge switches Q x and Q 2 (or pairs of switches in case of full bridge) in a zero voltage switching full protected mode.
• the stability of the control is achieved by changing the time constant of the DC/AC bridge control through the different operation regimens.
• a small time constant is used (fast control) when the light level is changed en request and a larger time constant (slow control) is used at steady state (fixed) light control. This method avoids overshoots or undershoots and light fluctuations respectively.
• the ASIC 130 of Figures 14, 15 and 16 carries out the control scheme described above.
• a further block diagram of the silicon topology that
• SUBST ⁇ UTE SHEET (RULE26) controls switches Q x and Q 2 of the bridge, including center tap protection is shown m Figure 18.
• Figure 19 shows tne control pulses produced by the circuit of Figure 18 on a common time base. 5
• a lamp current sample is provided to microprocessor 160 through A/D converter 161 (also included m ASIC 130) .
• Microprocessor 160 processes all 5 information and provides one DATA BUS 162 that includes all processed information (PLC, PFC, DC/AC) .
• Selector 163 latches appropriate data into the appropriate LATCH 164 and 165.
• the rate of re- 0 latching is a decision or default of the software.
• the HS waveform is fed into AND1 gate 168. Fixed dead time and also variable dead time (determined by C the center tap input) is added to the waveform which then exits through the HSDV (High Side Driver) output 169.
• SUBST ⁇ UTE SHEET (RULE26) 6.
• the waveform is also inverted by* NOT3 gate 170 and fed to AND2 gate 171.
• F ⁇ ?_ed and variable dead time is added to the waveform which then exits through the LSD (Low Side driver) output.
• NOT1 and NOT2 gates 173 and 174 respectively avoid the possibility of the 2 outputs HSD and LSD respectively being both "High" at the same time.
• the outputs of AND1 and AND 16S and 171 respectively, are monitored. If there is no overlapping with the original waveform (as getting out from HS PWM Logic) for 16 consecutive pulses, then the 16 tries counter 176 increases by 1, enabling 4 consecutive cycles with no interrupting. If the same phenomenon repeats itself the 16 tries counter 176 continues to increase. If the phenomenon disappears the 16 tries counter 176 is reset.
• the 16 tries counter 176 reaches 16 it sends an "Abnormal" message to the microprocessor 160 and enters an abnormal protection regime.
• variable depth "dithering" technique is applied m the variable width pulse mechanism through the entire lamp dimming work line.
• a digital control fcr the upper or the lower switch pulse width by a simple FW procedure will cause the light to flicker.
• a dithering method can be used.
• a PWM of an average level which lies between PWM steps is composed of a mixed sequence of pulses made from these two time steps.
• Precise light level control is acnieved by measuring the lamp current only. This method is implemented by matching the current versus light -level non-linear curve into linear segments. Each segment enables a ratio between percentage of ligh -level and the lamp current, allowing a very precise light level control as shown in Figure 20. This technique avoids the need for a complex lamp power or current measurement algorithm for each type of lamp to characterize the above non-linear behavior. Light control accuracy can be further increased by adding additional linear segments to the matched current versus light-level non-linear curve.
• This method is implemented by using a dedicated parameter table that can be set or defined by the user.
• the above ratio is between the light level and the current at certain points (the extremes of each segment) .
• the control method described uses a PWM whose frequency and dead times are variable. It is applied m a half/full bridge topology: high side pulse width, low side pulse width with dead times between them are programmed and applied m a manner designed to achieve stable, smooth control loop throughout the whole range of no load to full load.
• the method used suggests working near resonance at all loads but always keeping the load ust a little above resonance. This is done first by providing best open loop control behavior (minimum gam variation) at every point of the load regime. Pulse width and frequency are manipulated a manner that achieves a constant open loop gam (sometimes the PWM is used to increase load current and the frequency used to decrease it and vice versa) These manipulations are performed according to the load V/I characteristics.
• SUBST ⁇ UTE SHEET (RULE26) The following is an example of an embodiment in a ballast application.
• the control of dimmable discharge lamps over the full dimming range is based on a control range that is divided into three portions by two breaking points :
• PWM control is used from minimum load to the first breaking point : the high side pulse increases and the low side pulse decreases. The total periodic time is kept at a fixed number. 2. Fix the low side and PWM the high side pulse from the first breaking point to, second breaking point . The duty cycle is increased and at the same time frequency is decreased.
• Frequency control is used from the second breaking point to maximum load both high side and low side pulses increase.
• This method creates an open loop work- line with minimum gain variation and minimum predetermined dead time between pulses. This will best control a predictable load (e.g., a lamp with normal operating behavior) .
• a predictable load e.g., a lamp with normal operating behavior
• the center-tap voltage of the bridge is sampled to ensure that switching is at zero voltage. Pulses are dynamically changed to protect against destructive currents. Dead time is increased dynamically to the zero voltage point.
• This feature of the method enables working at high frequencies with very short predetermined dead time for a lamp with normal operating behavior. In addition, its permits increasing the dead time in the event of transients and changes in load behavior, for example, as the discharge lamps age.
• FIG. 21 shows the power line carrier (PLC) controlled dimmable ballast of layout Bi ilar to that shown in Figure 16.
• the ballast control ⁇ SIC 200 is shown within the solid line block 200 in Figure 20. PLC operation allows the ballast to receive dimming control information across the same power line bfting used to power the ballast.
• ASIC 200 is in turn schematically shown in Figure 21A.
• the ASIC Pin assignments are shown in Figure 22.
• the wall control unit (W.C.U.) schematics are also shown in
• the dynamic response of the control loop is "flexible". It will use a different "dumping factor" & loop response time for a number of pre-decided conditions. For example the following decisions table is applied m the case of the electronic ballast:
• step light level + if under 90% of desired then fast response; If input voltage step changed more than +-2% then fast response, etc.
• the desired light level is first given to the controller, as for example, going from full light to light off (transient mode) , then the PFC operation mode will be switched to fast response in order to avoid DC bus dips. At constant light (steady state) the PFC control switches to slow response mode preventing light flickering/glimmering.
• Limits, dumping factors and response times are parameters listed in predefined designer programmable tables .
• the control can be adjusted to handle all kinds of applications, including motor control, temperature control and manv others .
• DC bus soft start Auxiliary build up; Lamp preheat ; Lamp ignition; Up going light level; Down going light level;
• Step up light level Step down light level; Steady state "high” load; Steady state “low” load; Abnormals - output power shut-down; and
• Every single regime has. its own specific parameters table that is chosen when entering a new regime .
• Each parameter table contains all the special parameters for PFC control and DC/AC bridge control for each specific regime. The designer can program these parameters .
• Static ' and dynamic loop response adapt themselves to the inputs by getting feedback information from a number of digital and/or analog inputs chosen according to the right parameter tables, decision tables and addressed equations.
• This mode is operational any time the ballast output stage is inhibited and the PFC stage must carry en its operation in standby mode.
• the PFC stage has two tasks: first - to provide the auxiliary voltages 5V and 12V to the control and second - to keep the DC bus voltage within limits.
• the DC bus capacitor When the PFC stage has very small load, the DC bus capacitor will charge rapidly to a nominal limit and will inhibit PFC control pulses. Special parameters are used in order to allow the PFC stage to provide auxiliary voltages: minimum pulse width and fixed dead time between pulses. Another mode of operation is to change from controlling the DC bus (except for maximum) to controlling the auxiliary voltage to 12V.
• the parameter tables also contain some limits to provide part of the protections. For example: control pulses will be inhibited (pulse-by-pulse) in case of DC bus over-voltage (the pulses are inhibited if the DC bus is higher than 110%) . Also, if input voltage is above a certain predetermined limit, pulses will be inhibited. Input under-voltage is also monitored; the PFC control will go to power
• SUBST ⁇ UTE SHEET (RULE26) shutdown mode under a predetermined limit (over-voltage protection (OVP) in the present ASIC implementation) .
• OVP over-voltage protection
• MinPFCParam Max. PFC Ton pulse for Max load at Min Input RMS voltage Ton (255-n) /12MHz 100 1.29E-05 Sec
• MaxPFCParam Minimum usable Pulse for PFC control 125 4.17E-07 Sec LowDelPrs Discontinuous mode Maximum Dead time. 0 2.13E-05 Sec Hi ⁇ hDelPrs At Critical mode only.
• control step ⁇ [ (Vref-VDC) /n] +l ⁇ *83nsec 14
• VDCRef 2.19 Volt (A/D level) This is the normal VDC reference. 223 400 Volt VdcHvsl
• PfcPWMlPrs Fast PWM response factor (0 when no PWM) . 0 MinPFCStartUp
• SlowDcAcPrs Slow response PWM of 20 possible combinations of last and next Ton (HSD) . Pulse may change every 250usec. 20
• FastDcAcPrs Fast response PWM of 5 combinations. Pulse may change every 250usec. 5 StartDcAcPrs
• F 3ee06/ (64-n) "33,34,35,36” "96.77,100,103.44, 107.13" kHz
• control module 111 and ASIC 200 settings The following is an operation description which describes control module 111 and ASIC 200 settings:
• the customer can influence ballast behavior by determining several ballast parameters.
• Software is used to determine the ballast parameters .
• the control module 111 contains 13 parameters tables in its PROM and one customer parameters table in its EEPROM. Only the manufacture can change the parameters of tables 0-12. The customer can program its own parameters in EEPROM Table 13 using a Parameter Development Kit (PDK) .
• PDK Parameter Development Kit
• Tables 0-3 Versions for two T8-32 (parallel configuration) lamps (120V line application) .
• Tables 4- 12 Versions for two T8-36 (parallel -configuration) lamps (230V line application) .
• a desired parameter table is selected by combination of micro-jumpers SO, SI, S2, S3 (connected to S0-S3 pins) to create a hexadecimal number. Insert jumper for a logic "0", and leave open for logic "1".
• the Parameter Tables Selection Table below defines the selection of the desired parameters table.
• Contro ⁇ module 111 and ASIC 200 enable ballast operation in 5 different configurations as fellows :
• ballast can be designated as belonging to one of 7 different zones or as belonging ;o all zones. Ballast zone designation is selected via A/D input ZONE. (See PLC D.E.B. Section below) .
• DC D.E.B. Ballast is controlled from DC Wall Control Unit via DC lines. (See LOCAL D.E.B. Section below) .
• Ballast is controlled from local infrared IR light & occupancy sensors. (See LOCAL D.E.B. Section below) .
• Ballast is controlled from local occupancy sensor. (See occupancy D.E.B. Section below) .
• the Ballast Configuration Table shows,, ballast configuration selection via the CNFG pin. To get the required configuration, connect a resistor between CNFG pm and GND.
• the light level stays in Last Light Level until a dimming command is sent from the wail Control Unit via PLC communication.
• the ballast receives a 17 -bit string from the Wall Control Unit (W.C.U.) via PLC Remote Controlled Communication. Bit allocation is as follows:
• the rate of communication is 1 bit per line cy ⁇ le .
• PLC communication is synchronized to the l ne pnase .
• ballast zone identity (0-7) is implemented py providing a voltage equal equidistant increments petween 0 to 2.5V to the zcne pir.
• the Zone Selection Table is shown pelow.
• the pallast starts the lamps according to the last lignt level from the EEPROM parameters table and tnen increases or decreases to the DC controlled light level present tne ZONE pin.
• This DC level is applied from the DC control unit.
• the light level is related to ZONE pin voltage according to the fallowing formula :
• the maximum light level is obtained when the ZONE pin Voltage is 2.23V (converted to 227) .
• the lamp light goes to 0 when the ZONE pin voltage drops under HOmV.
• the Ballast starts -up when ZONE pin voltage exceeds 140mV.
• the ballast will start the lamps according to the last light level saved in the EEPROM parameters table.
• the IR receiver output signal is connected to the IR pin.
• the IR transmitter sends 8 codes: 5 Preset light levels, Up, Down and Off commands.
• the ballast light level is controlled by a light sensor connected via the ZONE pin.
• the ZONE pin is feedback input converted to a digital number and compared to the sensor reference value.
• the dimming command from the IR transmitter changes the sensor reference and changes the light level py a controlled close loop mechanism to get:
• Light Sensor New Sensor Reference. Light Sensor voltage range is 0.2V to 2.45V.
• the "Occupancy OFF" command uses the RCV pin.
• Logic "1" (open circuit) at the RCV pin detected as a “No Presence” and turns the ballast off.
• Logic "0" at the RCV pm s detected as “presence” and starts-up the ballast to last light value.
• the ZONE analog input pin is also used as a "No Presence Inhibit". If ZONE pin Voltage > 2.5V then "No Presence” disabled. The ballast dims the light to the minimum light level.
• the ballast After the occupancy sensor detects a presence the room, the ballast returns to the last light level. There is no delay time between "No Presence” detection (by the control module) and the dimming operation. Occupancy D.E.B. Start up
• Ballast will start lamps according to last light level saved m the EEPROM parameters table.
• the RCV p serves as a "Presence Detection” input.
• the ballast dims the light to the defined “Dim Light Level” on the ZONE pm.
• the dim light level is saved at the "No Presence Detected” moment according to following formula:
• Dim Light Level [Maximum Light Level] x [ZONE Voltage at Initialization Time] 2.23V.
• the ballast returns to the maximum light level after occupancy sensor detects a presence the room (logic "0" at ZONE p ) .
• Ballast will start lamps to "Maximum Light Level" .
• the ballast operates only at the maximum light level. Dimming is not possible. As all other configurations, the lamp current is stabilized by closed loop control via the ILAMP feedback.*mput pm.
• the ILAMP p voltage is 0.5V at the maximum light level situation .
• ASIC 200 are used for the protection functions of the ballast .
• the CL input is used for current limit protection of PFC switch.
• the PFCD output pm PFC Drive Pulse Signal s pulse-by-pulse inhibited when the CL input exceeds 2.5V.
• the VDC A/D input pin is used for closing the DC bus (PFC Output) loop and also as a hardware over- voltage protection sense input. (Input to analog comparator) .
• the PFCD output is pulse-by-pulse inhibited when the VDC pin voltage exceeds 2.5V.
• the VDC input is used for software over-voltage protection.
• the PFCD output s pulse-by-pulse inhibited (by software) when the VDC p voltage exceeds 2.4V.
• the CT input is used to keep the half bridge at a zero voltage switching (ZVS) operation. If the load becomes capacitive, the CT input will partially block the HSD or LSD outputs (increase dead times order to keep ZVS operation . If the limitation causes total disappearance of HSD pulses 16 times, then 4 cycles are enabled without interfering with the CT input. This total cycle of 20 ⁇ > 16+4 ) will repeat itself 16 times and if the malfunction does not? disappear, it will activate the abnormal function.
• ZVS zero voltage switching
• the SD input is used to sense catastrophic failures of the ballast .
• the SD input exceeds the Schmidt Trigger positive going threshold (2.2V-3.5V) according to catastrophic ballast failure occurrence, then hardware immediately inhibits (shuts down) theHSD & LSD outputs and software activates the abnormal function.
• the controller will try to start-up the ballast again 2 ' seconds after shutdown. If no abnormal indication is detected 2 seconds after ignition of the lamps, the abnormal protection procedure automatically resets an internal failure counter. If the failure is still detected, the controller will try to start-up the ballast 10 times with 3 second intervals between attempts. After 10 tries, the HSD & LSD outputs will be permanently inhibited. CT protection is also monitored as a catastrophic failure.
• An abnormal condition of CT protection initiates the same abnormal protection procedure.

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