EP1143320A1 - Arrangement for providing a reference voltage - Google Patents

Arrangement for providing a reference voltage Download PDF

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Publication number
EP1143320A1
EP1143320A1 EP01410026A EP01410026A EP1143320A1 EP 1143320 A1 EP1143320 A1 EP 1143320A1 EP 01410026 A EP01410026 A EP 01410026A EP 01410026 A EP01410026 A EP 01410026A EP 1143320 A1 EP1143320 A1 EP 1143320A1
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EP
European Patent Office
Prior art keywords
transistor
impedance
type
circuit
coupled
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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EP01410026A
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German (de)
French (fr)
Inventor
Michel Barou
Marius Reffay
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STMicroelectronics SA
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STMicroelectronics SA
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Publication of EP1143320A1 publication Critical patent/EP1143320A1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • G05F3/222—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/227—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage producing a current or voltage as a predetermined function of the supply voltage

Definitions

  • the present invention relates generally to reference voltage supply circuits, and in particular a circuit providing a stable reference voltage despite sudden variations in supply voltage.
  • the present invention applies in particular to amplifiers video feeding a cathode ray tube.
  • FIG. 1 represents a video amplifier 2 comprising an operational amplifier 4, the positive terminal of which receives a reference voltage V REF produced by a circuit 6.
  • the output of the amplifier 4 is coupled to its negative terminal via d 'a resistor 8 (R2).
  • the negative terminal also receives a video signal V IN via a resistor 10 (R1).
  • the amplifier 4 produces a voltage V OUT intended to control the cathode of a cathode-ray tube which can be represented by a capacitive load 12 (C).
  • the amplifier 4 also has two supply poles connected respectively to ground and to a positive supply voltage V ALIM .
  • Circuit 6, which is used here to establish a reference for the black level, is also supplied by the voltage V ALIM , although this has not been shown for reasons of clarity.
  • Circuit 6 is provided to compensate for variations in the supply voltage V ALIM .
  • these variations due for example to a change in temperature, are slow and the circuit 6 is designed so as not to affect them on the reference voltage V REF .
  • the supply voltage V ALIM can change suddenly, for example following a peak in current consumption, and this sudden change in supply voltage can result in a momentary change in the supply voltage. reference.
  • FIG. 2 illustrates an example of such a malfunction in the context of the video amplifier of FIG. 1.
  • the input signal V IN is at a constant level before an instant t 0 , then presents a sequence rapid variations of great amplitude. Such variations may correspond, in the example illustrated, to the display of a series of narrow vertical lines on the screen, alternately white and black.
  • the output voltage V OUT reproducing, after amplification, the inverse of the signal V IN , also varies rapidly, which, due to the relatively low impedance of the load C, forces the power source to provide a high current from time t 0 .
  • the supply voltage V ALIM varies accordingly by a value ⁇ V ALIM (positive in the example shown).
  • the signal V IN becomes stable again, the current calls cease on the power source, the voltage V ALIM increases by ⁇ V ALIM and returns to its initial value.
  • the voltage V REF increases by the value ⁇ V REF at time t 2 and the signal V OUT then becomes equal to: -K (V IN + V REF + ⁇ V REF ) + V REF + ⁇ V REF .
  • an object of the present invention is to provide a circuit which provides a reference voltage particularly stable.
  • Another object of the present invention is to provide such a circuit which is easy to realize in the form of a circuit integrated.
  • this invention provides a circuit for supplying a voltage of reference, comprising a first bipolar type transistor, whose transmitter provides the reference voltage and whose collector is connected to a first power pole, a second transistor MOS type, the drain of which is connected to the base of the first transistor and whose source is connected to a second supply pole, a control block, one output of which is connected to the gate of the second transistor and one input of which is connected to the emitter of the first transistor, a capacitor connected to the output of the control unit and coupled to the first power pole through a first impedance, and a second impedance connected on the one hand to the drain of the second transistor and secondly at the point of connection between the capacitance and the first impedance.
  • the second impedance is a first resistance.
  • the second impedance corresponds to the transconductance of a third transistor, MOS type, diode mounted.
  • the control unit includes fourth and fifth transistors bipolar, of the type of the first transistor, whose bases are connected together, their respective collectors being connected to a first and a second current sources, the fourth transistor, diode mounted, being smaller than the fifth transistor, and the output of the corresponding control block to the collector of the fifth transistor, a sixth transistor, bipolar of a different type from that of the first transistor, connected as a diode and placed between the emitter of the fourth transistor and the second power pole, a seventh transistor, bipolar of a different type from that of first transistor, disposed between the emitter of the fifth transistor and the second power pole, whose base is coupled to the second power pole via a second resistor, an eighth transistor, bipolar of the same type as the first transistor, the emitter of which is coupled to the base of the seventh transistor via a third resistor, whose collector is connected to the first pole supply, and the base of which is coupled to the second supply pole through a fourth resistance and to the input of the control block via a fifth transistor, bipolar of a different
  • the first and second current sources are respectively ninth and tenth bipolar transistors of a different type of that of the first transistor, whose emitters respective are coupled to the first power pole via of sixth and seventh resistors, the collectors respective of the ninth and tenth transistors being connected to the collectors of the fourth and fifth transistors, and their respective bases being connected so as to form a mirror of current with an eleventh transistor of the same type, which is mounted in diode and which is coupled to the first and second power poles respectively through eighth and ninth resistances.
  • MOS type transistors are NMOS, the first transistor is of the NPN type, and the first and second supply poles respectively represent a positive potential and the mass.
  • the present invention also provides an integrated circuit comprising such a circuit for supplying a reference voltage.
  • FIG. 3 represents a circuit 6 having the above drawbacks.
  • the circuit 6 illustrated provides a reference voltage V REF from a supply voltage V ALIM and comprises a bipolar transistor 14 of the NPN type whose collector receives the voltage V ALIM and whose emitter supplies the voltage V REF .
  • An N-type MOS transistor 16 has its drain connected on the one hand to the base of the transistor 14 and on the other hand to the voltage V ALIM via an impedance 18 (Z1).
  • the source of transistor 16 is connected to ground (GND).
  • a control block 20 is connected between the gate of the transistor 16 and the emitter of the transistor 14. The control block 20 is provided for controlling the transistor 16 so as to compensate for variations in the voltage V REF .
  • a capacitance 23 (Cp) connects the drain and the gate of the transistor 16.
  • a capacitance 24 (C ⁇ ) is also shown, which is of low value and which represents the parasitic capacitance between the source and the gate of the transistor 16.
  • A is called the connection point between the drain of transistor 16 and the base of transistor 14.
  • the gain of transistor 14 is equal to 1 (so-called “follower” circuit) or in "common collector”), so that a variation ⁇ V A of the voltage V A at point A is equal to the variation ⁇ V REF of the voltage V REF .
  • ⁇ I the current variation in the impedance 18 caused by a variation ⁇ V ALIM of the supply voltage
  • the voltage variation ⁇ V A is equal to ⁇ I.Z A where Z A represents the overall impedance present between point A and mass.
  • C .DELTA.I the current flowing through the capacitor C p
  • .DELTA.I A variation of the current flowing through the transistor 16
  • .DELTA.I .DELTA.I .DELTA.I C + A .
  • ⁇ I A gm. ⁇ V ⁇
  • ⁇ V ⁇ also representing the voltage between the gate and the source of this transistor.
  • ⁇ V p + ⁇ V ⁇ ⁇ V A.
  • the impedance Z A is equal to ⁇ V A / ⁇ I, i.e. ( ⁇ V p + ⁇ V ⁇ ) / ( ⁇ I C + ⁇ I A ).
  • the present invention aims to solve this problem.
  • FIG. 4 represents a first embodiment of a circuit 26 according to the present invention.
  • the circuit 26 supplies a reference voltage V REF and receives a supply voltage V ALIM .
  • the structure of circuit 26 is substantially the same as that of the previous circuit, but we have tried to ensure that variations in voltage V A at point A do not affect the output voltage V REF .
  • an impedance 28 of value Z 2 has been placed between the connection point A and the connection point B, which is the connection point between the impedance 18 (Z 1 ) and the capacitance 23 (C p ) .
  • the impedance 28 (Z 2 ) is chosen so that Z 2 is substantially equal to 1 / gm. (1 + C ⁇ / C p ), the voltage variation ⁇ V A due to the current variation ⁇ I, and the variation ⁇ V REF of the reference voltage V REF are substantially zero, and the present invention makes it possible to produce a circuit providing a reference voltage which hardly varies when V ALIM varies suddenly.
  • the impedance 28 is formed by a resistor only.
  • the values gm, C ⁇ and C p can be determined with precision and such resistance is easy to achieve. This embodiment is particularly simple to implement and provides a marked improvement over the prior art. However, it does not allow perfect cancellation of ⁇ V REF .
  • the resistance constituting the impedance 28 must be proportional to the inverse of the transconductance of the transistor 16 and the values of these elements do not change from the same way with temperature.
  • the resistors and transistors are not produced during the same technological stages and dispersions can lead to derives from the value of the resistance compared to that of the transconductance of transistor 16.
  • FIG. 5 represents a circuit 30 according to a second embodiment of the present invention, which makes it possible to obtain a variation ⁇ V REF substantially zero, independently of the dispersions due to manufacture, even in the case of an embodiment in integrated form.
  • the impedance 28 is produced by means of a diode-mounted MOS transistor and of the same type as the transistor 16.
  • FIG. 6 illustrates in more detail an embodiment of the circuit 30 of FIG. 5.
  • the control block 20 comprises two bipolar transistors 32 and 34 of NPN type, the bases of which are connected together.
  • the transistor 32 is connected as a diode and the transistor 34 has a larger emitter than the transistor 32.
  • the collectors of the transistors 32 and 34 are respectively connected to the collectors of two bipolar transistors 36 and 38, of PNP type.
  • Transistors 36 and 38 of identical size, have their bases connected to the base of a transistor 40 of the same type and of the same size, connected as a diode and coupled between the supply voltage and the ground by means of resistors. 42 and 44, respectively.
  • the emitters of transistors 36 and 38 are coupled to the supply voltage respectively by resistors 46 and 48.
  • the emitters of transistors 32 and 34 are respectively connected to the emitters of two bipolar PNP transistors 52 and 54.
  • the collectors of the transistors 52 and 54 are connected to ground.
  • the base of the transistors 52 is connected to ground.
  • the base of transistor 54 is coupled to ground via a resistor 56, and coupled to the emitter of a bipolar NPN transistor 60 via a resistor 58.
  • the collector of transistor 60 is connected to the supply voltage. Its base receives a fraction of the voltage V REF obtained using a divider bridge formed by a resistor 62 and a resistor 64, connected respectively to the ground and to the emitter of the transistor 14.
  • the junction point of the resistor 64 and the emitter of transistor 14 corresponds to the input of the control block 20.
  • the structure and operation of the control block 20 are known to those skilled in the art and they will not be described further.
  • the circuit 30 can be constructed with components of standard size and type, and it can easily be produced in integrated form.
  • the impedance 28 is made by a diode-mounted transistor.
  • the adaptation from the circuit of FIG. 6 to the first embodiment, in which an appropriate resistor replaces transistor 28, is part of the present invention.
  • the present invention thus makes it possible to produce a circuit providing a reference voltage which does not vary or very little when its supply voltage varies even in the case of an abrupt variation.
  • the circuit according to the present invention is small and easy to make in integrated form.
  • circuits have been described which provide a positive reference voltage, but the skilled person will easily adapt the present invention to a circuit which provides a negative voltage, among other things by replacing the NMOS transistors by PMOS transistors, and by reversing the type of bipolar transistors.
  • the supply pole of the circuit denoted GND does not necessarily represent the ground and the reference voltage V REF can be unconnected to ground and therefore "floating" with respect thereto.
  • impedance realization Z2 only two examples have been described. The invention is not limited to these exemplary embodiments only and those skilled in the art will determine easily other suitable types of impedance.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
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Abstract

L'invention concerne un circuit (26) de fourniture d'une tension de référence (VREF), comprenant un premier transistor (14) de type bipolaire, dont l'émetteur fournit la tension de référence et dont le collecteur est relié à un premier pôle d'alimentation (VALIM), un deuxième transistor (16) de type MOS, dont le drain est relié à la base du premier transistor et dont la source est reliée à un deuxième pôle d'alimentation (GND), un bloc de commande (20) dont une sortie est reliée à la grille du deuxième transistor et dont une entrée est reliée à l'émetteur du premier transistor, une capacité (23) connectée à la sortie du bloc de commande et couplée au premier pôle d'alimentation par l'intermédiaire d'une première impédance (18), et une deuxième impédance (28) connectée d'une part au drain du deuxième transistor et d'autre part au point de liaison (B) entre la capacité et la première impédance. <IMAGE>The invention relates to a circuit (26) for supplying a reference voltage (VREF), comprising a first transistor (14) of bipolar type, the emitter of which supplies the reference voltage and the collector of which is connected to a first supply pole (VALIM), a second MOS type transistor (16), the drain of which is connected to the base of the first transistor and the source of which is connected to a second supply pole (GND), a control block (20) an output of which is connected to the gate of the second transistor and an input of which is connected to the emitter of the first transistor, a capacitor (23) connected to the output of the control block and coupled to the first power supply pole by through a first impedance (18), and a second impedance (28) connected on the one hand to the drain of the second transistor and on the other hand to the connection point (B) between the capacitor and the first impedance. <IMAGE>

Description

La présente invention concerne de façon générale des circuits de fourniture de tension de référence, et en particulier un circuit fournissant une tension de référence stable en dépit de variations brutales de tension d'alimentation.The present invention relates generally to reference voltage supply circuits, and in particular a circuit providing a stable reference voltage despite sudden variations in supply voltage.

La présente invention s'applique notamment à des amplificateurs vidéo alimentant un tube cathodique.The present invention applies in particular to amplifiers video feeding a cathode ray tube.

Ainsi, la figure 1 représente un amplificateur vidéo 2 comprenant un amplificateur opérationnel 4 dont la borne positive reçoit une tension de référence VREF produite par un circuit 6. La sortie de l'amplificateur 4 est couplée à sa borne négative par l'intermédiaire d'une résistance 8 (R2). La borne négative reçoit également un signal vidéo VIN par l'intermédiaire d'une résistance 10 (R1). L'amplificateur 4 produit une tension VOUT destinée à commander la cathode d'un tube cathodique qui peut être représentée par une charge capacitive 12 (C). L'amplificateur 4 présente en outre deux pôles d'alimentation connectés respectivement à la masse et à une tension d'alimentation VALIM positive. Le circuit 6, qui sert ici à établir une référence pour le niveau de noir, est également alimenté par la tension VALIM, bien que cela n'ait pas été représenté pour des raisons de clarté. Thus, FIG. 1 represents a video amplifier 2 comprising an operational amplifier 4, the positive terminal of which receives a reference voltage V REF produced by a circuit 6. The output of the amplifier 4 is coupled to its negative terminal via d 'a resistor 8 (R2). The negative terminal also receives a video signal V IN via a resistor 10 (R1). The amplifier 4 produces a voltage V OUT intended to control the cathode of a cathode-ray tube which can be represented by a capacitive load 12 (C). The amplifier 4 also has two supply poles connected respectively to ground and to a positive supply voltage V ALIM . Circuit 6, which is used here to establish a reference for the black level, is also supplied by the voltage V ALIM , although this has not been shown for reasons of clarity.

Le circuit 6 est prévu pour compenser les variations de la tension d'alimentation VALIM. Dans certaines applications, ces variations, dues par exemple à un changement de température, sont lentes et le circuit 6 est conçu pour ne pas les répercuter sur la tension de référence VREF. Dans certaines applications cependant, la tension d'alimentation VALIM peut varier brutalement, par exemple à la suite d'un pic de consommation de courant, et cette variation brutale de tension d'alimentation peut se traduire par une variation momentanée de la tension de référence.Circuit 6 is provided to compensate for variations in the supply voltage V ALIM . In certain applications, these variations, due for example to a change in temperature, are slow and the circuit 6 is designed so as not to affect them on the reference voltage V REF . In certain applications, however, the supply voltage V ALIM can change suddenly, for example following a peak in current consumption, and this sudden change in supply voltage can result in a momentary change in the supply voltage. reference.

La figure 2 illustre un exemple d'un tel dysfonctionnement dans le cadre de l'amplificateur vidéo de la figure 1. En figure 2, le signal d'entrée VIN est à un niveau constant avant un instant t0, puis présente une suite de variations rapides de grande amplitude. De telles variations peuvent correspondre, dans l'exemple illustré, à l'affichage d'une suite d'étroites raies verticales sur l'écran, alternativement blanches et noires. La tension de sortie VOUT, reproduisant, après amplification, l'inverse du signal VIN, varie également rapidement, ce qui, du fait de l'impédance relativement faible de la charge C, oblige la source d'alimentation à fournir un fort courant à partir de l'instant t0. La tension d'alimentation VALIM varie en conséquence d'une valeur ΔVALIM (positive dans l'exemple représenté). Cette variation de tension est trop rapide pour être compensée immédiatement par le circuit 6, et la tension VREF varie, comme on le verra par la suite, d'une valeur ΔVREF qui dépend de la valeur ΔVALIM. Comme la tension reçue sur la borne positive de l'amplificateur 4 a varié de ΔVREF, le signal VOUT, qui était égal à -K(VIN + VREF) + VREF devient : VOUT = -K(VIN + VREF + ΔVREF) + VREF + ΔVREF,    où K (égal à R2/R1) est le gain du circuit 2.FIG. 2 illustrates an example of such a malfunction in the context of the video amplifier of FIG. 1. In FIG. 2, the input signal V IN is at a constant level before an instant t 0 , then presents a sequence rapid variations of great amplitude. Such variations may correspond, in the example illustrated, to the display of a series of narrow vertical lines on the screen, alternately white and black. The output voltage V OUT , reproducing, after amplification, the inverse of the signal V IN , also varies rapidly, which, due to the relatively low impedance of the load C, forces the power source to provide a high current from time t 0 . The supply voltage V ALIM varies accordingly by a value ΔV ALIM (positive in the example shown). This voltage variation is too rapid to be immediately compensated by the circuit 6, and the voltage V REF varies, as will be seen later, by a value ΔV REF which depends on the value ΔV ALIM . As the voltage received on the positive terminal of amplifier 4 has varied by ΔV REF , the signal V OUT , which was equal to -K (V IN + V REF ) + V REF becomes: V OUT = -K (V IN + V REF + ΔV REF ) + V REF + ΔV REF , where K (equal to R2 / R1) is the gain of circuit 2.

A un instant t1 qui dépend de la valeur ΔVREF et de la faculté de "récupération" du circuit 6, la tension VREF retrouve sa valeur nominale et le signal VOUT redevient VOUT = -K(VIN + VREF) + VREF. At an instant t 1 which depends on the value ΔV REF and on the "recovery" option of circuit 6, the voltage V REF returns to its nominal value and the signal V OUT becomes again V OUT = -K (V IN + V REF ) + V REF .

A un instant t2, le signal VIN redevient stable, les appels de courant cessent sur la source d'alimentation, la tension VALIM augmente de ΔVALIM et reprend sa valeur initiale. La tension VREF augmente de la valeur ΔVREF à l'instant t2 et le signal VOUT devient alors égal à : -K(VIN + VREF + ΔVREF) + VREF + ΔVREF. At an instant t 2 , the signal V IN becomes stable again, the current calls cease on the power source, the voltage V ALIM increases by ΔV ALIM and returns to its initial value. The voltage V REF increases by the value ΔV REF at time t 2 and the signal V OUT then becomes equal to: -K (V IN + V REF + ΔV REF ) + V REF + ΔV REF .

Un peu plus tard, à un instant t3, la tension VREF retrouve sa valeur nominale et le signal de sortie VOUT redevient -K(VIN + VREF) + VREF.A little later, at an instant t 3 , the voltage V REF returns to its nominal value and the output signal V OUT becomes again -K (V IN + V REF ) + V REF .

Ces variations de la tension de référence VREF sont très gênantes. Dans l'exemple illustré, la déformation du signal VOUT qui a lieu entre les instants t2 et t3, produit une traínée lumineuse particulièrement inesthétique.These variations in the reference voltage V REF are very troublesome. In the example illustrated, the distortion of the signal V OUT which takes place between the instants t 2 and t 3 , produces a particularly unaesthetic light trail.

En conséquence, un objet de la présente invention est de prévoir un circuit qui fournisse une tension de référence particulièrement stable.Accordingly, an object of the present invention is to provide a circuit which provides a reference voltage particularly stable.

Un autre objet de la présente invention est de prévoir un tel circuit qui soit facile à réaliser sous forme de circuit intégré.Another object of the present invention is to provide such a circuit which is easy to realize in the form of a circuit integrated.

Pour atteindre ces objets, ainsi que d'autres, la présente invention prévoit un circuit de fourniture d'une tension de référence, comprenant un premier transistor de type bipolaire, dont l'émetteur fournit la tension de référence et dont le collecteur est relié à un premier pôle d'alimentation, un deuxième transistor de type MOS, dont le drain est relié à la base du premier transistor et dont la source est reliée à un deuxième pôle d'alimentation, un bloc de commande dont une sortie est reliée à la grille du deuxième transistor et dont une entrée est reliée à l'émetteur du premier transistor, une capacité connectée à la sortie du bloc de commande et couplée au premier pôle d'alimentation par l'intermédiaire d'une première impédance, et une deuxième impédance connectée d'une part au drain du deuxième transistor et d'autre part au point de liaison entre la capacité et la première impédance. To achieve these and other objects, this invention provides a circuit for supplying a voltage of reference, comprising a first bipolar type transistor, whose transmitter provides the reference voltage and whose collector is connected to a first power pole, a second transistor MOS type, the drain of which is connected to the base of the first transistor and whose source is connected to a second supply pole, a control block, one output of which is connected to the gate of the second transistor and one input of which is connected to the emitter of the first transistor, a capacitor connected to the output of the control unit and coupled to the first power pole through a first impedance, and a second impedance connected on the one hand to the drain of the second transistor and secondly at the point of connection between the capacitance and the first impedance.

Selon un mode de réalisation de la présente invention, la deuxième impédance est une première résistance.According to an embodiment of the present invention, the second impedance is a first resistance.

Selon un mode de réalisation de la présente invention, la deuxième impédance correspond à la transconductance d'un troisième transistor, de type MOS, monté en diode.According to an embodiment of the present invention, the second impedance corresponds to the transconductance of a third transistor, MOS type, diode mounted.

Selon un mode de réalisation de la présente invention, le bloc de commande comprend des quatrième et cinquième transistors bipolaires, du type du premier transistor, dont les bases sont connectées ensemble, leurs collecteurs respectifs étant reliés à une première et une seconde sources de courant, le quatrième transistor, monté en diode, étant plus petit que le cinquième transistor, et la sortie du bloc de commande correspondant au collecteur du cinquième transistor, un sixième transistor, bipolaire d'un type différent de celui du premier transistor, connecté en diode et disposé entre l'émetteur du quatrième transistor et le second pôle d'alimentation, un septième transistor, bipolaire d'un type différent de celui du premier transistor, disposé entre l'émetteur du cinquième transistor et le second pôle d'alimentation, dont la base est couplée au second pôle d'alimentation par l'intermédiaire d'une deuxième résistance, un huitième transistor, bipolaire du même type que le premier transistor, dont l'émetteur est couplé à la base du septième transistor par l'intermédiaire d'une troisième résistance, dont le collecteur est relié au premier pôle d'alimentation, et dont la base est couplée au second pôle d'alimentation par l'intermédiaire d'une quatrième résistance et à l'entrée du bloc de commande par l'intermédiaire d'une cinquième résistance.According to an embodiment of the present invention, the control unit includes fourth and fifth transistors bipolar, of the type of the first transistor, whose bases are connected together, their respective collectors being connected to a first and a second current sources, the fourth transistor, diode mounted, being smaller than the fifth transistor, and the output of the corresponding control block to the collector of the fifth transistor, a sixth transistor, bipolar of a different type from that of the first transistor, connected as a diode and placed between the emitter of the fourth transistor and the second power pole, a seventh transistor, bipolar of a different type from that of first transistor, disposed between the emitter of the fifth transistor and the second power pole, whose base is coupled to the second power pole via a second resistor, an eighth transistor, bipolar of the same type as the first transistor, the emitter of which is coupled to the base of the seventh transistor via a third resistor, whose collector is connected to the first pole supply, and the base of which is coupled to the second supply pole through a fourth resistance and to the input of the control block via a fifth resistance.

Selon un mode de réalisation de la présente invention, les première et seconde sources de courant sont respectivement des neuvième et dixième transistors bipolaires d'un type différent de celui du premier transistor, dont les émetteurs respectifs sont couplés au premier pôle d'alimentation par l'intermédiaire de sixième et septième résistances, les collecteurs respectifs des neuvième et dixième transistors étant reliés aux collecteurs des quatrième et cinquième transistors, et leurs bases respectives étant reliées de manière à former un miroir de courant avec un onzième transistor du même type, qui est monté en diode et qui est couplé aux premier et second pôles d'alimentation respectivement par l'intermédiaire de huitième et neuvième résistances.According to an embodiment of the present invention, the first and second current sources are respectively ninth and tenth bipolar transistors of a different type of that of the first transistor, whose emitters respective are coupled to the first power pole via of sixth and seventh resistors, the collectors respective of the ninth and tenth transistors being connected to the collectors of the fourth and fifth transistors, and their respective bases being connected so as to form a mirror of current with an eleventh transistor of the same type, which is mounted in diode and which is coupled to the first and second power poles respectively through eighth and ninth resistances.

Selon un mode de réalisation de la présente invention, les transistors de type MOS sont des NMOS, le premier transistor est du type NPN, et les premier et second pôles d'alimentation représentent respectivement un potentiel positif et la masse.According to an embodiment of the present invention, MOS type transistors are NMOS, the first transistor is of the NPN type, and the first and second supply poles respectively represent a positive potential and the mass.

La présente invention prévoit également un circuit intégré comprenant un tel circuit de fourniture d'une tension de référence.The present invention also provides an integrated circuit comprising such a circuit for supplying a reference voltage.

Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles :

  • la figure 1, précédemment décrite, représente le schéma d'un amplificateur vidéo comportant un circuit fournissant une tension de référence ;
  • la figure 2, précédemment décrite, illustre un exemple de fonctionnement de l'amplificateur vidéo de la figure 1 ;
  • la figure 3 représente le schéma d'un circuit fournissant une tension de référence ;
  • la figure 4 représente schématiquement un premier mode de réalisation d'un circuit fournissant une tension de référence selon la présente invention ;
  • la figure 5 représente schématiquement un deuxième mode de réalisation d'un circuit fournissant une tension de référence selon la présente invention ; et
  • la figure 6 représente plus en détail un schéma électrique du circuit de la figure 5.
    • These objects, characteristics and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
  • FIG. 1, previously described, represents the diagram of a video amplifier comprising a circuit supplying a reference voltage;
  • Figure 2, previously described, illustrates an example of operation of the video amplifier of Figure 1;
  • FIG. 3 represents the diagram of a circuit providing a reference voltage;
  • FIG. 4 schematically represents a first embodiment of a circuit providing a reference voltage according to the present invention;
  • FIG. 5 schematically represents a second embodiment of a circuit providing a reference voltage according to the present invention; and
  • FIG. 6 represents in more detail an electrical diagram of the circuit of FIG. 5.

    • De mêmes références désignent de mêmes éléments en figures 3 à 6. Seuls les éléments nécessaires à la compréhension de la présente invention ont été représentés.Same references denote same items in Figures 3 to 6. Only the elements necessary for understanding of the present invention have been shown.

    La figure 3 représente un circuit 6 présentant les inconvénients ci-dessus. Le circuit 6 illustré fournit une tension de référence VREF à partir d'une tension d'alimentation VALIM et comprend un transistor bipolaire 14 de type NPN dont le collecteur reçoit la tension VALIM et dont l'émetteur fournit la tension VREF. Un transistor MOS 16 de type N a son drain relié d'une part à la base du transistor 14 et d'autre part à la tension VALIM par l'intermédiaire d'une impédance 18 (Z1). La source du transistor 16 est reliée à la masse (GND). Un bloc de commande 20 est connecté entre la grille du transistor 16 et l'émetteur du transistor 14. Le bloc de commande 20 est prévu pour commander le transistor 16 de manière à compenser les variations de la tension VREF. Une capacité 23 (Cp) relie le drain et la grille du transistor 16. On a également représenté une capacité 24 (Cπ), qui est de faible valeur et qui représente la capacité parasite entre la source et la grille du transistor 16. Dans la suite de la description, on appelle A le point de liaison entre le drain du transistor 16 et la base du transistor 14. Pour des raisons de simplicité, on considère que le gain du transistor 14 est égal à 1 (montage dit "suiveur" ou en "collecteur commun"), de sorte qu'une variation ΔVA de la tension VA au point A est égale à la variation ΔVREF de la tension VREF.FIG. 3 represents a circuit 6 having the above drawbacks. The circuit 6 illustrated provides a reference voltage V REF from a supply voltage V ALIM and comprises a bipolar transistor 14 of the NPN type whose collector receives the voltage V ALIM and whose emitter supplies the voltage V REF . An N-type MOS transistor 16 has its drain connected on the one hand to the base of the transistor 14 and on the other hand to the voltage V ALIM via an impedance 18 (Z1). The source of transistor 16 is connected to ground (GND). A control block 20 is connected between the gate of the transistor 16 and the emitter of the transistor 14. The control block 20 is provided for controlling the transistor 16 so as to compensate for variations in the voltage V REF . A capacitance 23 (Cp) connects the drain and the gate of the transistor 16. A capacitance 24 (C π ) is also shown, which is of low value and which represents the parasitic capacitance between the source and the gate of the transistor 16. In the rest of the description, A is called the connection point between the drain of transistor 16 and the base of transistor 14. For reasons of simplicity, we consider that the gain of transistor 14 is equal to 1 (so-called "follower" circuit) or in "common collector"), so that a variation ΔV A of the voltage V A at point A is equal to the variation ΔV REF of the voltage V REF .

    Si l'on appelle ΔI la variation de courant dans l'impédance 18 entraínée par une variation ΔVALIM de la tension d'alimentation, la variation de tension ΔVA est égale à ΔI.ZA où ZA représente l'impédance globale présente entre le point A et la masse. Si l'on appelle ΔIC le courant qui traverse la capacité Cp, et ΔIA la variation du courant qui traverse le transistor 16, on a, en négligeant le courant dans la base du transistor 14, ΔI = ΔIC + ΔIA. D'autre part, si on considère que tout le courant traversant Cp passe totalement dans Cπ et si l'on appelle ΔVp et ΔVπ les variations des tensions Vp et Vπ aux bornes des capacités Cp et Cπ , on a, en cas de variations faibles pouvant être assimilées à des différentielles : ΔIC = Cp.ΔVp = Cπ.ΔVπ. If we call ΔI the current variation in the impedance 18 caused by a variation ΔV ALIM of the supply voltage, the voltage variation ΔV A is equal to ΔI.Z A where Z A represents the overall impedance present between point A and mass. If we call C .DELTA.I the current flowing through the capacitor C p, and .DELTA.I A variation of the current flowing through the transistor 16, there was, neglecting the current in the base of transistor 14, .DELTA.I = .DELTA.I .DELTA.I C + A . On the other hand, if we consider that all the current flowing through C p passes completely through C π and if we call ΔV p and ΔV π the variations of the voltages V p and V π across the capacitors C p and C π , we have, in the event of small variations which can be assimilated to differentials: ΔI VS = C p .ΔV p = C π .ΔV π .

    Par ailleurs, gm étant la transconductance du transistor 16, on a ΔIA = gm.ΔVπ , ΔVπ représentant aussi la tension entre la grille et la source de ce transistor. En outre, on a ΔVp + ΔVπ = ΔVA. L'impédance ZA est égale à ΔVA/ΔI, soit (ΔVp + ΔVπ)/(ΔIC + ΔIA). Ainsi, on tire des formules précédentes l'expression : ZA = (ΔVp + ΔVπ)/(Cπ ΔVπ + gm.ΔVπ) Il découle également des formules précédentes que ΔVp est égal à Cπ/Cp.ΔVπ . On a ainsi : ZA = (Cπ/Cp + 1)/(Cπ + gm). Comme Cπ a en général une valeur faible devant gm, la formule précédente devient : ZA = (Cπ/Cp + 1)/gm Furthermore, gm being the transconductance of transistor 16, we have ΔI A = gm.ΔV π , ΔV π also representing the voltage between the gate and the source of this transistor. In addition, we have ΔV p + ΔV π = ΔV A. The impedance Z A is equal to ΔV A / ΔI, i.e. (ΔV p + ΔV π ) / (ΔI C + ΔI A ). Thus, the expression: Z AT = (ΔV p + ΔV π) /(VS π ΔV π + gm.ΔV π ) It also follows from the above formulas that ΔV p is equal to C π / C p .ΔV π . We thus have: Z AT = (C π /VS p +1) / (C π + gm). As C π generally has a low value before gm, the above formula becomes: Z AT = (C π /VS p + 1) / gm

    Pour une variation ΔI donnée, la variation ΔVA est ainsi ΔVA = [(Cπ/Cp + 1)/gm].ΔI, ce qui provoque la variation indésirable décrite précédemment de la tension VREF. La présente invention vise à résoudre ce problème.For a given variation ΔI, the variation ΔV A is thus ΔV A = [(C π / C p + 1) / gm] .ΔI, which causes the undesirable variation described above of the voltage V REF . The present invention aims to solve this problem.

    La figure 4 représente un premier mode de réalisation d'un circuit 26 selon la présente invention. Le circuit 26 fournit une tension de référence VREF et reçoit une tension d'alimentation VALIM. La structure du circuit 26 est sensiblement la même que celle du circuit précédent, mais on a cherché à faire en sorte que les variations de la tension VA au point A ne se répercutent pas sur la tension de sortie VREF. Pour ce faire, on a disposé une impédance 28 de valeur Z2 entre le point de liaison A et le point de liaison B, qui est le point de liaison entre l'impédance 18 (Z1) et la capacité 23 (Cp).FIG. 4 represents a first embodiment of a circuit 26 according to the present invention. The circuit 26 supplies a reference voltage V REF and receives a supply voltage V ALIM . The structure of circuit 26 is substantially the same as that of the previous circuit, but we have tried to ensure that variations in voltage V A at point A do not affect the output voltage V REF . To do this, an impedance 28 of value Z 2 has been placed between the connection point A and the connection point B, which is the connection point between the impedance 18 (Z 1 ) and the capacitance 23 (C p ) .

    Avec les notations précédentes, on a toujours ΔI = ΔIC + ΔIA avec ΔIC = Cp.ΔVp = Cπ.ΔVπ = Cπ .ΔIA/gm. Dans le circuit de l'invention, cependant, le courant AIA traverse désormais l'impédance 28 et le transistor 16, ce qui fait que ΔVA = ΔVp + ΔVπ - Z2.ΔIA. With the previous notations, we always have ΔI = ΔI C + ΔI A with ΔI C = C p .ΔV p = C π .ΔV π = C π .ΔI A / gm. In the circuit of the invention, however, the current AIA now passes through the impedance 28 and the transistor 16, so that ΔV A = ΔV p + ΔV π - Z 2 .ΔI A.

    Il en découle que :

    Figure 00080001
    It follows that:
    Figure 00080001

    Si l'on choisit l'impédance 28 (Z2) de manière que Z2 soit sensiblement égale à 1/gm.(1 + Cπ/Cp), la variation de tension ΔVA due à la variation de courant ΔI, et la variation ΔVREF de la tension de référence VREF sont sensiblement nulles, et la présente invention permet de réaliser un circuit fournissant une tension de référence qui ne varie pratiquement pas lorsque VALIM varie brusquement.If the impedance 28 (Z 2 ) is chosen so that Z 2 is substantially equal to 1 / gm. (1 + C π / C p ), the voltage variation ΔV A due to the current variation ΔI, and the variation ΔV REF of the reference voltage V REF are substantially zero, and the present invention makes it possible to produce a circuit providing a reference voltage which hardly varies when V ALIM varies suddenly.

    Dans un mode de réalisation, l'impédance 28 est formée par une résistance seulement. Les valeurs gm, Cπ et Cp peuvent être déterminées avec précision et une telle résistance est facile à réaliser. Ce mode de réalisation est particulièrement simple à mettre en oeuvre et procure une amélioration nette par rapport à l'art antérieur. Cependant, il ne permet pas une annulation parfaite de ΔVREF.In one embodiment, the impedance 28 is formed by a resistor only. The values gm, C π and C p can be determined with precision and such resistance is easy to achieve. This embodiment is particularly simple to implement and provides a marked improvement over the prior art. However, it does not allow perfect cancellation of ΔV REF .

    En effet, la résistance constituant l'impédance 28 doit être proportionnelle à l'inverse de la transconductance du transistor 16 et les valeurs de ces éléments n'évoluent pas de la même manière avec la température. En outre, si le circuit de la présente invention est réalisé sous forme intégrée, les résistances et les transistors ne sont pas produits au cours des mêmes étapes et des dispersions technologiques peuvent entraíner une dérive de la valeur de la résistance par rapport à celle de la transconductance du transistor 16.Indeed, the resistance constituting the impedance 28 must be proportional to the inverse of the transconductance of the transistor 16 and the values of these elements do not change from the same way with temperature. In addition, if the circuit of the present invention is realized in integrated form, the resistors and transistors are not produced during the same technological stages and dispersions can lead to derives from the value of the resistance compared to that of the transconductance of transistor 16.

    La figure 5 représente un circuit 30 selon un second mode de réalisation de la présente invention, qui permet d'obtenir une variation ΔVREF sensiblement nulle, indépendamment des dispersions dues à la fabrication, même dans le cas d'une réalisation sous forme intégrée. Dans ce mode de réalisation, l'impédance 28 est réalisée au moyen d'un transistor MOS monté en diode et de même type que le transistor 16. Le transistor 28 est calculé pour présenter une transconductance gm' telle que 1/gm.(1 + Cπ/Cp) = 1/gm'. Par exemple, si l'on utilise des transistors 28 et 16 présentant des canaux de même longueur et de largeurs W et W', respectivement, on obtiendra la relation précédente avec : W/W' = (1 + Cπ/Cp) Les transistors 28 et 16 sont fabriqués en même temps et des modifications de leurs caractéristiques à la suite d'éventuelles dispersions technologiques seront identiques. Ainsi, dans ce mode de réalisation, la tension VREF restera très stable même si la tension VALIM varie brutalement.FIG. 5 represents a circuit 30 according to a second embodiment of the present invention, which makes it possible to obtain a variation ΔV REF substantially zero, independently of the dispersions due to manufacture, even in the case of an embodiment in integrated form. In this embodiment, the impedance 28 is produced by means of a diode-mounted MOS transistor and of the same type as the transistor 16. The transistor 28 is calculated to have a transconductance gm 'such that 1 / gm. (1 + C π / C p ) = 1 / gm '. For example, if we use transistors 28 and 16 having channels of the same length and widths W and W ', respectively, we will obtain the previous relationship with: W / W ' = (1 + C π /VS p ) The transistors 28 and 16 are manufactured at the same time and changes in their characteristics as a result of possible technological dispersions will be identical. Thus, in this embodiment, the voltage V REF will remain very stable even if the voltage V ALIM varies suddenly.

    Les formules précédentes ont, comme on l'a vu, été obtenues au moyen d'approximations, ce qui fait que l'annulation de ΔVREF ne va peut être pas être rigoureusement nulle en pratique. Si cela est souhaité, un calcul complet et une détermination exacte de l'impédance 28 sont à la portée de l'homme de l'art.The above formulas have, as we have seen, been obtained by means of approximations, which means that the cancellation of ΔV REF may not be rigorously zero in practice. If desired, a complete calculation and an exact determination of the impedance 28 is within the skill of the art.

    La figure 6 illustre plus en détail un mode de réalisation du circuit 30 de la figure 5. Pour des raisons de clarté, on n'a pas représenté la capacité parasite Cπ du transistor 16. Le bloc de commande 20 comprend deux transistors bipolaires 32 et 34 de type NPN, dont les bases sont connectées ensemble. Le transistor 32 est connecté en diode et le transistor 34 a un émetteur plus grand que le transistor 32. Les collecteurs des transistors 32 et 34 sont respectivement reliés aux collecteurs de deux transistors 36 et 38 bipolaires, de type PNP. Les transistors 36 et 38, de taille identique, ont leurs bases reliées à la base d'un transistor 40 de même type et de même taille, connecté en diode et couplé entre la tension d'alimentation et la masse par l'intermédiaire de résistances 42 et 44, respectivement. Les émetteurs des transistors 36 et 38 sont couplés à la tension d'alimentation respectivement par des résistances 46 et 48. Les émetteurs des transistors 32 et 34 sont connectés respectivement aux émetteurs de deux transistors 52 et 54, bipolaires de type PNP. Les collecteurs des transistors 52 et 54 sont connectés à la masse. La base du transistors 52 est connectée à la masse. La base du transistor 54 est couplée à la masse par l'intermédiaire d'une résistance 56, et couplée à l'émetteur d'un transistor 60 bipolaire de type NPN par l'intermédiaire d'une résistance 58. Le collecteur du transistor 60 est relié à la tension d'alimentation. Sa base reçoit une fraction de la tension VREF obtenue à l'aide d'un pont diviseur formé par une résistance 62 et une résistance 64, connectées respectivement à la masse et à l'émetteur du transistor 14. Le point de jonction de la résistance 64 et de l'émetteur du transistor 14 correspond à l'entrée du bloc de commande 20. La structure et le fonctionnement du bloc de commande 20 sont connus de l'homme de l'art et ils ne seront pas décrits plus avant. Le circuit 30 peut être construit avec des composants de taille et de type standard, et il peut facilement être réalisé sous forme intégrée.FIG. 6 illustrates in more detail an embodiment of the circuit 30 of FIG. 5. For reasons of clarity, the parasitic capacitance C π of the transistor 16 has not been shown. The control block 20 comprises two bipolar transistors 32 and 34 of NPN type, the bases of which are connected together. The transistor 32 is connected as a diode and the transistor 34 has a larger emitter than the transistor 32. The collectors of the transistors 32 and 34 are respectively connected to the collectors of two bipolar transistors 36 and 38, of PNP type. Transistors 36 and 38, of identical size, have their bases connected to the base of a transistor 40 of the same type and of the same size, connected as a diode and coupled between the supply voltage and the ground by means of resistors. 42 and 44, respectively. The emitters of transistors 36 and 38 are coupled to the supply voltage respectively by resistors 46 and 48. The emitters of transistors 32 and 34 are respectively connected to the emitters of two bipolar PNP transistors 52 and 54. The collectors of the transistors 52 and 54 are connected to ground. The base of the transistors 52 is connected to ground. The base of transistor 54 is coupled to ground via a resistor 56, and coupled to the emitter of a bipolar NPN transistor 60 via a resistor 58. The collector of transistor 60 is connected to the supply voltage. Its base receives a fraction of the voltage V REF obtained using a divider bridge formed by a resistor 62 and a resistor 64, connected respectively to the ground and to the emitter of the transistor 14. The junction point of the resistor 64 and the emitter of transistor 14 corresponds to the input of the control block 20. The structure and operation of the control block 20 are known to those skilled in the art and they will not be described further. The circuit 30 can be constructed with components of standard size and type, and it can easily be produced in integrated form.

    Dans le circuit de la figure 30, l'impédance 28 est réalisée par un transistor monté en diode. Cependant, l'adaptation du circuit de la figure 6 au premier mode de réalisation, dans lequel une résistance appropriée remplace le transistor 28, fait partie de la présente invention.In the circuit of figure 30, the impedance 28 is made by a diode-mounted transistor. However, the adaptation from the circuit of FIG. 6 to the first embodiment, in which an appropriate resistor replaces transistor 28, is part of the present invention.

    La présente invention permet ainsi de réaliser un circuit fournissant une tension de référence qui ne varie pas ou très peu lorsque sa tension d'alimentation varie même dans le cas d'une variation brusque. Le circuit selon la présente invention est de taille réduite et facile à réaliser sous forme intégrée.The present invention thus makes it possible to produce a circuit providing a reference voltage which does not vary or very little when its supply voltage varies even in the case of an abrupt variation. The circuit according to the present invention is small and easy to make in integrated form.

    Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaítront à l'homme de l'art.Of course, the present invention is capable of various variants and modifications which will appear to the man of art.

    En particulier, on a décrit des circuits qui fournissent une tension de référence positive, mais l'homme du métier adaptera sans difficultés la présente invention à un circuit qui fournit une tension négative, entre autre en remplaçant les transistors NMOS par des transistors PMOS, et en intervertissant le type des transistors bipolaires.In particular, circuits have been described which provide a positive reference voltage, but the skilled person will easily adapt the present invention to a circuit which provides a negative voltage, among other things by replacing the NMOS transistors by PMOS transistors, and by reversing the type of bipolar transistors.

    De même, le pôle d'alimentation du circuit noté GND ne représente pas nécessairement la masse et la tension de référence VREF peut être non reliée à la masse et donc "flottante" par rapport à celle-ci.Likewise, the supply pole of the circuit denoted GND does not necessarily represent the ground and the reference voltage V REF can be unconnected to ground and therefore "floating" with respect thereto.

    Aussi, seuls deux exemples de réalisation de l'impédance Z2 ont été décrits. L'invention n'est pas limitée à ces exemples de réalisation seulement et l'homme de l'art déterminera sans peine d'autres types d'impédance appropriés.Also, only two examples of impedance realization Z2 have been described. The invention is not limited to these exemplary embodiments only and those skilled in the art will determine easily other suitable types of impedance.

    Claims (7)

    Circuit (26, 30) de fourniture d'une tension de référence (VREF), comprenant : un premier transistor (14) de type bipolaire, dont l'émetteur fournit la tension de référence et dont le collecteur est relié à un premier pôle d'alimentation (VALIM), un deuxième transistor (16) de type MOS, dont le drain est relié à la base du premier transistor et dont la source est reliée à un deuxième pôle d'alimentation (GND), un bloc de commande (20) dont une sortie est reliée à la grille du deuxième transistor et dont une entrée est reliée à l'émetteur du premier transistor, une capacité (23) connectée à la sortie du bloc de commande et couplée au premier pôle d'alimentation par l'intermédiaire d'une première impédance (18), et une deuxième impédance (28) connectée d'une part au drain du deuxième transistor et d'autre part au point de liaison (B) entre la capacité et la première impédance. Circuit (26, 30) for supplying a reference voltage (V REF ), comprising: a first bipolar type transistor (14), the emitter of which supplies the reference voltage and the collector of which is connected to a first supply pole (V ALIM ), a second MOS type transistor (16), the drain of which is connected to the base of the first transistor and the source of which is connected to a second supply pole (GND), a control block (20), one output of which is connected to the gate of the second transistor and one input of which is connected to the emitter of the first transistor, a capacitor (23) connected to the output of the control unit and coupled to the first supply pole via a first impedance (18), and a second impedance (28) connected on the one hand to the drain of the second transistor and on the other hand to the connection point (B) between the capacitor and the first impedance. Circuit selon la revendication 1, caractérisé en ce que la deuxième impédance (28) est une première résistance.Circuit according to claim 1, characterized in that the second impedance (28) is a first resistor. Circuit selon la revendication 1, caractérisé en ce que la deuxième impédance (28) correspond à la transconductance d'un troisième transistor, de type MOS, monté en diode.Circuit according to Claim 1, characterized in that the second impedance (28) corresponds to the transconductance of a third transistor, of MOS type, mounted as a diode. Circuit selon l'une quelconque des revendications précédentes, caractérisé en ce que le bloc de commande (20) comprend : des quatrième (32) et cinquième (34) transistors bipolaires, du type du premier transistor, dont les bases sont connectées ensemble, leurs collecteurs respectifs étant reliés à une première et une seconde sources de courant, le quatrième transistor, monté en diode, étant plus petit que le cinquième transistor, et la sortie du bloc de commande correspondant au collecteur du cinquième transistor (34), un sixième transistor (52), bipolaire d'un type différent de celui du premier transistor, connecté en diode et disposé entre l'émetteur du quatrième transistor et le second pôle d'alimentation (GND), un septième transistor (54), bipolaire d'un type différent de celui du premier transistor, disposé entre l'émetteur du cinquième transistor (34) et le second pôle d'alimentation (GND), dont la base est couplée au second pôle d'alimentation par l'intermédiaire d'une deuxième résistance (56), un huitième transistor (60), bipolaire du même type que le premier transistor, dont l'émetteur est couplé à la base du septième transistor par l'intermédiaire d'une troisième résistance (58), dont le collecteur est relié au premier pôle d'alimentation (VALIM), et dont la base est couplée au second pôle d'alimentation (GND) par l'intermédiaire d'une quatrième résistance (62) et à l'entrée du bloc de commande par l'intermédiaire d'une cinquième résistance (64). Circuit according to any one of the preceding claims, characterized in that the control block (20) comprises: fourth (32) and fifth (34) bipolar transistors, of the type of the first transistor, the bases of which are connected together, their respective collectors being connected to a first and a second current sources, the fourth transistor, mounted as a diode, being smaller than the fifth transistor, and the output of the control block corresponding to the collector of the fifth transistor (34), a sixth transistor (52), bipolar of a different type from that of the first transistor, connected as a diode and disposed between the emitter of the fourth transistor and the second power supply pole (GND), a seventh transistor (54), bipolar of a type different from that of the first transistor, disposed between the emitter of the fifth transistor (34) and the second supply pole (GND), the base of which is coupled to the second pole d 'supply via a second resistor (56), an eighth transistor (60), bipolar of the same type as the first transistor, the emitter of which is coupled to the base of the seventh transistor via a third resistor (58), the collector of which is connected to the first pole d power supply (V ALIM ), the base of which is coupled to the second power supply pole (GND) via a fourth resistor (62) and to the input of the control unit via a fifth resistance (64). Circuit selon la revendication 4, caractérisé en ce que les première et seconde sources de courant sont respectivement des neuvième (36) et dixième (38) transistors bipolaires d'un type différent de celui du premier transistor, dont les émetteurs respectifs sont couplés au premier pôle d'alimentation (VALIM) par l'intermédiaire de sixième (46) et septième (48) résistances, les collecteurs respectifs des neuvième et dixième transistors étant reliés aux collecteurs des quatrième (32) et cinquième (34) transistors, et leurs bases respectives étant reliées de manière à former un miroir de courant avec un onzième transistor (40) du même type, qui est monté en diode et qui est couplé aux premier et second pôles d'alimentation respectivement par l'intermédiaire de huitième (42) et neuvième (44) résistances.Circuit according to Claim 4, characterized in that the first and second current sources are respectively ninth (36) and tenth (38) bipolar transistors of a type different from that of the first transistor, the respective emitters of which are coupled to the first supply pole (V ALIM ) via sixth (46) and seventh (48) resistors, the respective collectors of the ninth and tenth transistors being connected to the collectors of the fourth (32) and fifth (34) transistors, and their respective bases being connected so as to form a current mirror with an eleventh transistor (40) of the same type, which is mounted as a diode and which is coupled to the first and second supply poles respectively via the eighth (42) and ninth (44) resistors. Circuit selon l'une quelconque des revendications précédentes, caractérisé en ce que les transistors de type MOS sont des NMOS, le premier transistor est du type NPN, et en ce que les premier et second pôles d'alimentation représentent respectivement un potentiel positif et la masse.Circuit according to any one of the preceding claims, characterized in that the MOS type transistors are NMOS, the first transistor is of the NPN type, and in that the first and second supply poles respectively represent a positive potential and the mass. Circuit intégré comprenant un circuit selon une des revendications 1 à 6.Integrated circuit comprising a circuit according to one of claims 1 to 6.
    EP01410026A 2000-03-15 2001-03-14 Arrangement for providing a reference voltage Withdrawn EP1143320A1 (en)

    Applications Claiming Priority (2)

    Application Number Priority Date Filing Date Title
    FR0003320 2000-03-15
    FR0003320A FR2806489B1 (en) 2000-03-15 2000-03-15 REFERENCE VOLTAGE SUPPLY CIRCUIT

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    EP1143320A1 true EP1143320A1 (en) 2001-10-10

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    EP (1) EP1143320A1 (en)
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    JP2003124757A (en) * 2001-10-16 2003-04-25 Texas Instr Japan Ltd Method and device for reducing influence of earely effect

    Citations (3)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    US4859963A (en) * 1988-05-24 1989-08-22 Maxim Integrated Products High speed low gain stable amplifier
    EP0440434A2 (en) * 1990-01-31 1991-08-07 Fujitsu Limited Constant voltage generating circuit
    FR2781317A1 (en) * 1998-07-17 2000-01-21 St Microelectronics Sa Low impedance voltage source for powering integrated circuits uses linked MOS transistors in control and power stages to reduce power consumption to zero when no charge is received

    Family Cites Families (3)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    FR2718259A1 (en) * 1994-03-30 1995-10-06 Philips Composants Regulator circuit providing a voltage independent of the power supply and the temperature.
    US5955874A (en) * 1994-06-23 1999-09-21 Advanced Micro Devices, Inc. Supply voltage-independent reference voltage circuit
    US6285244B1 (en) * 1999-10-02 2001-09-04 Texas Instruments Incorporated Low voltage, VCC incentive, low temperature co-efficient, stable cross-coupled bandgap circuit

    Patent Citations (3)

    * Cited by examiner, † Cited by third party
    Publication number Priority date Publication date Assignee Title
    US4859963A (en) * 1988-05-24 1989-08-22 Maxim Integrated Products High speed low gain stable amplifier
    EP0440434A2 (en) * 1990-01-31 1991-08-07 Fujitsu Limited Constant voltage generating circuit
    FR2781317A1 (en) * 1998-07-17 2000-01-21 St Microelectronics Sa Low impedance voltage source for powering integrated circuits uses linked MOS transistors in control and power stages to reduce power consumption to zero when no charge is received

    Also Published As

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    US6407624B2 (en) 2002-06-18
    US20010043115A1 (en) 2001-11-22
    FR2806489B1 (en) 2002-06-28
    FR2806489A1 (en) 2001-09-21

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