EP1133857A1

EP1133857A1 - Method for disturbance compensation of a signal generated by discrete multitone-modulation and circuit arrangement for implementing said method

Info

Publication number: EP1133857A1
Application number: EP99960912A
Authority: EP
Inventors: Heinrich Schenk; Dietmar STRÄUSSNIGG; Stefan Schneider
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 1998-11-24
Filing date: 1999-11-17
Publication date: 2001-09-19
Also published as: CN1118169C; WO2000031937A1; US6647076B1; JP3739655B2; CN1328739A; JP2002531008A

Abstract

The invention relates to a method for disturbance compensation of a signal generated by discrete multitone-modulation. The signal generated by discrete multitone-modulation is provided with a plurality of carrier frequencies and each carrier frequency is provided with a signal vector. A reference signal vector being a signal vector of the plurality of signal vectors generates an error signal vector. Said error signal vector is added to each remaining signal vector of the plurality of signal vectors in order to achieve disturbance compensation. A set of adjustable coefficients is allocated to each signal vector of the plurality of signal vectors other than the reference signal vector and is multiplied with said error signal vector before addition.

Description

description

Method for compensating for interference in a signal generated with discrete multitone modulation and circuit arrangement for carrying out the method

The invention relates to a method for compensating for disturbances in a signal generated with discrete multitone modulation according to the preamble of claim 1 and a method according to the preamble of claim 9 and a circuit arrangement for carrying out the method according to the preamble of claim 6.

Discrete multitone modulation (DMT) - also multi-carrier modulation - is a modulation method that is particularly suitable for the transmission of data via linearly distorting channels. Compared to so-called single-carrier methods such as, for example, amplitude modulation, which has only one carrier frequency, a large number of carrier frequencies are used in the discrete multitone modulation. Each individual carrier frequency is modulated in amplitude and phase according to quadrature amplitude modulation (QAM). A large number of QAM-modulated signals are thus obtained. A certain number of bits can be transmitted per carrier frequency. Discrete multitone modulation is used, for example, for digital broadcasting DAB (Digital Audio Broadcast) under the name OFDM (Orthogonal Frequency Division Multiplex) and for the transmission of data over telephone lines under the name ADSL (Asymmetry Digital Subscriber Line).

With ADSL, data is transmitted from a switching center to an analogue connected subscriber over the telephone network using a DMT-modulated signal. It is determined by ETSI and ANSI standards that each carrier frequency has approximately 4 kHz bandwidth and transports up to 15 bits / s / Hz at most. The actual number of bits / s / Hz can be different for each carrier frequency, as a result of which the data rate and the transmission spectrum can be adapted to the transmission channel.

A DMT transmission system has an encoder that combines the bits of a serial digital data signal to be transmitted into blocks. A complex number is assigned to a certain number of bits in a block. A carrier frequency f _λ = i / T with i = 1, 2, ..., N / 2 of the discrete multitone modulation is represented by a complex number, with all carrier frequencies f _x being distributed equidistantly. T is the duration of a block. The carrier frequencies represented by signal vectors are transformed into the time domain by an inverse Fourier transformation and there directly represent N samples of a DMT signal to be transmitted. If N is to be used for the fast inverse Fourier transformation (IFFT = Inverse Fast Fourier Transformation) a power of two is chosen.

After the inverse fast Fourier transformation, a cyclic prefix is carried out, the last M (M <N) of the samples being appended to the beginning of a block. As a result, a periodic signal is simulated to a receiver when the transient process generated by a transmission channel has decayed after M samples according to a time T-MI N. The equalization effort in the receiver can be greatly reduced by the cyclic prefix, since after demodulation in the receiver it is only necessary to multiply by the inverse transmission function of the transmission channel in order to eliminate the linear distortions of the transmission channel. This requires one complex or four real multiplications for each carrier frequency. With ADSL, the transmission channel is a two-wire line (copper twin wire). The two-wire line takes a long time to settle in relation to the length of a block. On the other hand, the additional transmission capacity required by the cyclic prefix should be as small as possible.

With a block length of N = 512, a cyclic prefix of M = 32 is specified for ADSL. However, the settling process of the two-wire line has not yet subsided after M = 32 values. This causes interference in the receiver that cannot be eliminated by a frequency domain equalizer.

Such interference can be reduced in the receiver using special signal processing measures.

For this purpose, a time domain equalizer (TDEQ = Time Domain Equalizer) is connected upstream of a demodulator. The time domain equalizer is designed as a digital transversal filter whose coefficients are adjustable. The task of the time domain equalizer is to shorten the transient response of the transmission channel. Accordingly, the number of pulse response values of the digital transversal filter must be as small as possible the M samples of the cyclic prefix. The design of such time domain equalizers can be found in Al-Dhahir, N., Cioffi, JM, "Optimum Finite-Length Equalization for Multicarrier Transceivers", IEEE Trans. On Comm., Vol.44, No.l, Jan.1996. However, the high additional circuit complexity for the time domain equalizer is disadvantageous due to the large number of coefficients (between 20 to 40 coefficients) that the digital transversal filter used as the time domain equalizer has. Another disadvantage of such time domain equalizers is the high computing effort that ner filter length of 20 to 40 coefficients is approximately 50 to 100 million multiplications per second and requires a correspondingly high circuit complexity. In addition, each coefficient must be set to adapt the digital transversal filter.

The technical problem on which the invention is based is therefore to specify a method for compensating for interference in a signal generated with discrete multitone modulation and a circuit arrangement for carrying out the method, which require less circuit complexity than time domain equalizers and as a simple and fast algorithm or are to be implemented as a simple circuit.

This problem is solved by a method for compensating for disturbances in a signal generated with discrete multitone modulation with the features of claim 1 or by a method with the features of claim 9 and by a circuit arrangement for carrying out the method with the features of claim 6 . Advantageous refinements result from the respective subclaims.

The invention relates to a method for compensating

Interference with a signal generated with discrete multitone modulation. The signal generated with discrete multitone modulation has a plurality of carrier frequencies and each carrier frequency has a signal vector. An error signal vector is generated from a reference signal vector, which is a signal vector from the plurality of signal vectors. The error signal vector is added to each of the remaining signal vectors of the plurality of signal vectors to compensate for interference. Each of the signal vectors of the plurality of signal vectors other than the reference signal vector is a set of adjustable coefficient assigned by which the error signal vector is multiplied before addition. The error signal is advantageously calculated in a simple step of the method and added to the other carrier frequencies in a further simple step. Because the interference of each individual carrier frequency is dependent on one another, it is sufficient to calculate the error signal from a carrier frequency. In contrast to time domain equalization, the method can be carried out very simply as an algorithm.

The adjustable coefficients are particularly preferably adapted in accordance with the transmission conditions of the carrier frequency which has the signal vector assigned to the adjustable coefficient. This adaptation of the coefficients advantageously achieves better suppression of interference which may be contained in the signal vector.

In a preferred embodiment, the adjustable coefficients are set using an iterative algorithm for minimizing errors.

In a particularly preferred embodiment, the adjustable coefficients are set using the mean square error algorithm.

The reference signal vector is preferably mapped into a discrete-value reference signal vector and the discrete-value reference signal vector is subtracted from the reference signal vector to generate the error signal vector.

Furthermore, the invention relates to a circuit arrangement for compensating for interference in a signal generated with discrete multitone modulation, the discrete multi sound modulation generated signal in the frequency domain has a plurality of carrier frequencies and wherein each carrier frequency has a signal vector. A reference signal vector is fed to a first decision circuit, which maps the reference signal vector into a discrete-value reference signal vector. A subtractor circuit subtracts the reference signal vector and the discrete-value reference signal vector from one another to form an error signal vector. The error signal vector is supplied to a plurality of adders which add the error signal vector to every other signal vector except for the reference signal vector. Each of the plurality of adders is preceded by multiplier circuits which multiply the first error signal vector by adjustable coefficients.

The adjustable coefficients are preferably adjustable by means of a manipulated variable.

A power of two is particularly preferably selected for the manipulated variable, as a result of which the adjustable ones are set

Coefficients can be carried out by a simple shift register.

The invention also relates to a method for compensating for interference in a signal generated with discrete multitone modulation, interference from the other signal vectors of the plurality of signal vectors being approximately calculated from the error signal vector, and the calculated interference from the respective signal vector of the plurality of signal vectors be subtracted to compensate for interference. Advantageously, no adaptive setting of coefficients is necessary. This means that there can be no convergence problems during the adaptation. Further advantages, features and possible applications of the invention result from the following description of exemplary embodiments in conjunction with the drawing. In the drawing shows

Fig.l shows a first embodiment of the circuit arrangement for compensating for interference in a signal generated with discrete multitone modulation;

2 shows an embodiment of the circuit arrangement for forming the weighting coefficients of the error signal; and

3 shows a diagram with the signal-to-noise ratio at the input of the decision-maker; and

4 shows a second embodiment of the circuit arrangement for compensating for interference in a signal generated with discrete multitone modulation;

Figure 1 shows an embodiment of the circuit arrangement for compensating for interference in a signal generated with discrete multitone modulation. A serial-parallel converter 1 receives digital samples of a signal IN generated with discrete multitone modulation. The serial-to-parallel converter 1 forms blocks from the supplied digital samples, one block having a multiplicity of N parallel signals which are fed to a demodulator 2. N should be a power of two.

The demodulator 2 is a fast Fourier transformer, which converts the large number of N parallel signals supplied in the time domain into a large number of n carrier frequencies fO - fn in the frequency domain, each carrier frequency in the case of discrete multitone modulation with the quadrature amplitude Modulation (QAM) is modulated. Each carrier frequency has a signal vector 20a, 20b to 2na, 2nb.

For example, with ADSL (Asymmetry Digital Subscriber Line) of 256 carrier frequencies, each with a frequency spacing of 4.3125 kHz, the carrier frequencies 7 to 250 corresponding to a frequency spectrum of 30.1875 kHz to 1078.125 kHz are used for signal transmission.

Each signal vector has two elements, one

Represent the real part and an imaginary part of a complex number. The amount and phase of the complex number correspond to the carrier frequency (frequency channel, channel) with QAM modulated signal.

Corresponding to the large number of signal vectors or carrier frequencies, n frequency range equalizers 30,... 3n (FDEQ = Frequency Division Equalizer) are provided for equalizing the signal vectors 20a, 20b to 2na, 2nb. A frequency domain equalizer is used for channel equalization of a signal vector. For this purpose, each frequency range equalizer can be adapted to the transmission characteristic of the transmission channel that is specific for a carrier frequency. An equalized signal vector ao, bo or a _n , b _{n is present} at the output of each frequency domain equalizer 30,..., 3n.

Each frequency range equalizer 30, ..., 3n is followed by a decision circuit 40 or 4n. A decision circuit decides which signal state in the signal state space of the carrier frequencies modulated with QAM is assigned to a supplied signal vector. A signal state corresponds to a value-discrete signal vector which has a value-discrete amplitude and a value-discrete phase. Crucial for the correct assignment of a signal vector a discrete-value signal vector is a signal vector that is as little disturbed by the transmission as possible.

Each decision circuit 40, ..., 4n is followed by a decoder circuit 50 or 5n. A decoder circuit decodes the binary signals OUT0 to OUTn contained in the signal vector from a value-discrete signal vector supplied.

Any signal vector a ₀ , b ₀ is used as the reference signal vector. The first signal circuit 40 converts the reference signal vector into a discrete-value reference signal vector a ₀ ", b ₀ '. The reference signal vector is used to correct all other signal vectors. This is possible due to the interdependence of the individual signal vectors.

An error signal vector is generated from the reference signal vector and is used to correct all other signal vectors. For this purpose, the real part a ₀ and the value-discrete real part a ₀ 'of the reference signal vector are fed to a first subtractor circuit 6 and subtracted from one another. At the output of the first subtractor circuit 6 there is a real part Δ a _{0 of} a complex number which represents the error signal contained in the error signal vector Δa ₀ , Δb ₀ . The imaginary part b ₀ and the value-discrete imaginary part b ₀ 'of the reference signal vector are supplied to a second subtracting circuit 7 in accordance with the real parts. At the output of the second subtractor circuit 7 there is an imaginary part Δb _{0 of} the complex number which represents the error signal contained in the error signal vector Δa ₀ , Δb ₀ .

The formula for forming the elements of the error signal vector from the elements of the reference signal vector is: Δα ₀ = ^a o ^{~ a} O ^{and Δ} * o = ^b o ^{~ b} 'o

The error signal vector Δa ₀ , Δb ₀ is adapted to the signal vector to be corrected and added to the signal vector which corresponds to a channel to be corrected for correction.

This method is described below using the example of any channel that corresponds to a signal vector a _n , b _n . In terms of the method, every channel except the channel which has the reference signal vector is corrected.

The real part Δ a _{0 of} the error signal vector is fed to a first multiplier circuit 8 and in parallel to a second multiplier circuit 11. The first multiplier circuit 8 multiplies the real part Δ a _{0 of} the error signal vector by a first coefficient C _aa ⁿ - the second multiplier circuit 11 multiplies the real part Δ a _{0 of} the error signal vector by a second coefficient C _a b ⁿ .

The imaginary part Δb _{0 of} the error signal vector is fed to a third multiplier circuit 9 and in parallel to a fourth multiplier circuit 10. The third multiplier 9 multiplies the imaginary part .DELTA.b ₀ of the error signal vector with a third coefficient C ⁿ _ba> The fourth multiplier 10 multiplies the imaginary part .DELTA.b ₀ of the error signal vector with a fourth coefficient Cbb "•

The output signal of the first multiplier circuit 8 and the third multiplier circuit 9 is fed to a first adder circuit 12. A real part a _{n of} the signal vector, which is present at the output of a frequency domain equalizer 3n, is also applied to the first adder circuit 12. leads. The first adder circuit adds the three supplied signals to an error-corrected real part a _n * of the signal vector.

The output signal of the second multiplier circuit and the fourth multiplier circuit are fed to a second adder circuit 13. The second adder circuit 13 is also supplied with an imaginary part b _{n of} the signal vector which is present at the output of the second frequency range equalizer 3n. An error-corrected imaginary part b _n * of the signal vector is present at the output of the second adder circuit 13, which adds the three supplied signals.

The procedure described above can be expressed by the following formulas:

«„. = « _* + - Δα ₀ + C; _fl - Δb ₀ b ,, = b _m + C _β " _b - Δa ₀ + Cl - Δb ₀

The error-corrected real part a _n * and the error-corrected imaginary part b _n * of the signal vector are fed to a second decision circuit 4n, which converts the error-corrected real part a _n * and the error-corrected imaginary part b _n * into a value-discrete real part a _n * 'or into a value-discrete I converts binary part b _n * 'of a value-discrete signal vector a _n *', b _n * '.

The discrete-value signal vector a _n * ', b _n *' is fed to a second decoder circuit 5n. The second decoder circuit 5n decodes signals from the supplied signal vector.

For each signal vector except the reference signal vector, the error signal vector is in accordance with the method weighted channel to be corrected and added to the signal vector representing the channel.

The weighting coefficients C _aa ^n, C _ba ^n, C _from ⁿ and C _bb ⁿ to weighting of the error signal vector can be adjusted using an iterative algorithm for error minimization, such as the metal at Square Error algorithm (MSE) algorithm stepwise (k denotes a discrete point in time):

(*) = C (k - l) ~ g. Aa ₀ (k) - Δα „(*) _b (k) = C _b ⁿ _b (k - l) - g- Δb ₀ (*) • Δb„ (*)

(1) C _a " _b (k) = C _a " _b (k - l) - g. A ₀ (k) - Ab „(k) _a (k) = _a (k - l) - g- Ab ₀ (k) - A _n (k)

To calculate the weighting coefficients C _aa ⁿ , C _ba ⁿ , C _ab ⁿ and Cb ⁿ according to the formulas (1), both the error signal vector Δa ₀ , Δb _{0 of} the reference signal vector and an error signal vector Δa _n , Δb _{n of} the _n to be corrected are used -th channel required. The error signal vector Δa _n , Δb _{n of} the nth channel to be corrected is formed in accordance with the error signal vector of the reference channel.

When a signal vector is to be suppressed only in the lower frequency range extends a simplified algorithm with symmetrical weighting coefficients C ⁿ _aa, _ba C ^n, C ⁿ and _a C _bb ⁿ from. This can be the case, for example, when using a time domain equalizer connected upstream of the demodulator 2 and the serial-parallel converter 1. The requirements for the time domain equalizer are then lower than the requirements for a time domain equalizer without interference compensation. The weighting coefficient C _aa ^n, C _ba ^n, C _from ⁿ and C ⁿ _bb loading expected in this case as follows: Ci (*) = CL (* - l)

(2a) C £ (*) = -Ci (* - 1)

The symmetry of the weighting coefficients advantageously reduces the storage space required for storing the weighting coefficients.

In this case, the setting algorithm is as follows:

(*) = (* - 1) - g ^■ (Aa ₀ (k) ^■ Δα „(*) + Δb ₀ (k) ^■ Ab„ (*))

: 2b) i (*) = (* - 1) - g ^■ (Δα ₀ (*) • Δb „(*) - Δb ₀ (*) ^• Δ„ (*))

The circuit arrangements shown in Figure 2 to calculate ^n, the weighting coefficients C _aa, _ba C ^n, C ⁿ and C _from _bb ⁿ after the MSE algorithm corresponding to the formulas (1).

Each of the circuit arrangements has a first multiplier 100 which multiplies the real part Δa ₀ or the imaginary part Δb _{0 of} the error signal vector of the reference channel by the real part Δa _n or the imaginary part Δb _n of the error signal vector formed from the channel to be corrected.

A second multiplier 101 connected downstream of the first multiplier 100 multiplies the result of the first multiplier 100 by a manipulated variable g, which is formed in a circuit block 102.

The manipulated variable g is chosen as a power of two 2 ^{~ μ} to simplify the multiplication. As a result, a simple shift register can be used for the second multiplier 101. A further simplification can be achieved in that only the sign is used for the real part Δai and the imaginary part Δbi of an error signal vector (this also applies to the simplified algorithm according to the formulas (2b)). The first multiplication 100 is thus reduced to a one-bit operation.

The output signal of the second multiplier 101 is fed to the negative input of a comparator 103, the output of which is fed back to the positive input via a delay element 104.

FIG. 3 shows the signal-to-noise ratio (SNR = signal-to-noise ratio) for various methods for compensating for interference at the input of each decision circuit 40,..., 4n. Without time domain equalizer and interference suppression, an SNR of -40 to -20 dB is achieved over a frequency range up to approx. 1.1 MHz. With the inventive method for compensating for interference (= interference suppressor), an SNR of -70 to about -45 dB is achieved, which corresponds to an improvement of an average of 25 to 30 dB. With a time domain equalizer, which has 32 coefficients and is connected in front of the demodulator 2, an SNR of -70 to approx. -50 dB is achieved.

FIG. 4 shows a second exemplary embodiment of the circuit arrangement for compensating for disturbances in a signal generated with discrete multitone modulation. All elements that are identical to the elements of the first exemplary embodiment are also provided with the same reference symbols.

Only the differences between the first and second embodiments are described below. The error signal vector Δa ₀ , Δb _{0 of} the reference signal vector is fed to a device 200 which adapts the error signal vector to the channels to be corrected.

For this purpose, parameters for the error frequency response are first calculated from the error signal vector, which are then used to correct the other channels.

If the circuit arrangement is viewed as a 2nd order system, the frequency response of the interference or error per channel can be calculated using the following equation:

Error _n = (c, + c ₂ z _n ) - ^Qn

EE <2_mod _π

n channel index

Error _n Error of the nth channel z _n z _n = e ^jω "^'Ta with T _a as sampling time (e.g. at

ADSL 2.208 MHz) FEQ _n coefficients of the frequency domain equalizer of the nth channel FEQ_mod _n coefficients of a modified frequency domain equalizer of the nth channel, wherein FEQ _{n is} transformed into the frequency domain by means of inverse Fourier transformation and the part of the impulse response that occurs within the cyclic - Prefix lies, "is cut off"

The parameters c _λ and c ₂ can be calculated from the reference channel - for example the 0th channel - using the above equation: eÄ / er ₀ = (c, + c ₂ - z ₀ ) - ~ ° EO, _mod ₀

Since this equation is complex, two equations - a real and an imaginary equation - result for the calculation of the two unknown parameters Ci and c ₂ . The error frequency response can thus be calculated analytically for each additional channel and used to correct the respective channel. This method advantageously does not require any adaptation of coefficients during a transmission. Only once the parameters cl and c2 and thus the error frequency responses of the other channels have to be calculated from the reference channel. This means that no convergence problems can occur due to the adjustment time saved.

After the calculation of the parameters ci and c ₂ and the error frequency response of each channel, the error signal vector in the device 200 is modified either with l / FEQ_mod, if correction is carried out before the frequency domain equalizers, or with FEQ / FEQ_mod, if it is corrected after the frequency domain equalizers .

The error signal vector adapted in this way is then added to the n-th channel with the adder circuits 201 and 202 for interference compensation.

Claims

claims

1. A method for compensating for interference in a signal generated using discrete multitone modulation, the signal generated using discrete multitone modulation having a multiplicity of carrier frequencies and each carrier frequency having a signal vector (a ₀ , b ₀ to a _n , b _n ) has, characterized in that

an error signal vector (Δa ₀ , Δb ₀ ) is generated from a reference signal vector (a ₀ , b ₀ ), which is a signal vector from the multiplicity of signal vectors (a ₀ , b ₀ to a _n , b _n ),

- the error signal vector is added to each of the remaining signal vectors of the plurality of signal vectors (a _n , b _n ) to compensate for interference (12, 13), and - each of the signal vectors of the plurality of signal vectors

(ai, bi to a _n , b _n ) in addition to the reference signal vector (a ₀ , b ₀ ), a set of adjustable coefficients (C _aa ⁿ , C _ba ⁿ , C _bb ⁿ , C _ab ⁿ ) is assigned with which the error signal vector (Δa ₀ , Δb ₀ ) is multiplied before the addition (12, 13).

2. The method according to claim 1, characterized in that the adjustable coefficients (C _aa ⁿ , C _ba ⁿ , C _bb ⁿ , C _ab ⁿ ) corresponding to the transmission conditions of the carrier frequency, which the adjustable coefficients (C _aa ⁿ , C _ba ⁿ , C _bb ⁿ , C _a ⁿ ) assigned signal vector (a _n , b _n ) can be adapted.

3. The method according to claim 2, characterized in that the adjustable coefficients (C _aa ⁿ , C _ba ⁿ , C _bb ⁿ , C _from ⁿ ) are set with an iterative algorithm for minimizing errors.

4. The method according to claim 3, characterized in that the adjustable coefficients (C _aa ⁿ , C _ba ⁿ , C _bb ⁿ , C _ab ⁿ ) with the

Mean square error algorithm can be set.

5. The method according to any one of the preceding claims, characterized in that the reference signal vector (a _0, b ₀₎ ( ', b _0' a ₀₎ is converted into a discrete-value reference signal vector ready and the value-discrete reference signal vector (a _0, b ₀ ') is subtracted (6, 7) from the reference signal vector (a ₀ , b ₀ ) to generate the error signal vector (Δa ₀ , Δb ₀ ).

6. Circuit arrangement for compensating for interference in a signal generated with discrete multitone modulation, the signal generated with discrete multitone modulation in the frequency domain having a multiplicity of carrier frequencies and each carrier frequency having a signal vector (a ₀ , b ₀ to a _n , b _n ), characterized in that - a reference signal vector (a ₀ , b ₀ ) is fed to a first decision circuit (40) which converts the reference signal vector (a ₀ , b ₀ ) into a discrete-value reference signal vector (a ₀ ', b ₀ ') maps,

a subtractor circuit (6, 7) for forming an error signal vector (Δa ₀ , Δb ₀ ) subtracts the reference signal vector (a ₀ , b ₀ ) and the discrete-value reference signal vector (a ₀ ', b ₀ '),

- The error signal vector (Δa ₀ , Δb ₀ ) is fed to a plurality of adders (12, 13) which convert the error signal vector (Δa ₀ , Δb ₀ ) to every other signal vector (a _n , b _n ) except for the reference signal vector (a ₀ , b ₀ ) add, and

- Each of the plurality of adders (12, 13) multiplier circuits (8, 9, 10, 11) are connected upstream, which Multiply the signal signal vector (Δa ₀ , Δb ₀ ) by adjustable coefficients (C _aa ⁿ , C _ba ⁿ , C _bb ⁿ , C _ab ⁿ ).

7. Circuit arrangement according to claim 6, characterized in that the adjustable coefficients (C _aa ⁿ , C _ba ⁿ , C _bb ⁿ , C _ab ⁿ ) are adjustable by a manipulated variable (102).

8. Circuit arrangement according to claim 7, characterized in that a power of two is chosen for the manipulated variable (102).

9. A method for compensating for interference in a signal generated with discrete multitone modulation, wherein the signal generated with discrete multitone modulation has a plurality of carrier frequencies and wherein each carrier frequency has a signal vector (a ₀ , b ₀ to a _n , b _n ), characterized in that

- from the error signal vector (Δa ₀ , Δb ₀ ) disturbances of the other signal vectors of the plurality of signal vectors (a _n , b _n ) are approximately calculated, and - the calculated disturbances of the respective signal vector of the plurality of signal vectors (a _n , b _n ) are subtracted to compensate for interference (12, 13).