EP1121656A2 - Methode et appareil permettant de gerer la configuration et la fonctionnalite d'un modele de semi-conducteur - Google Patents

Methode et appareil permettant de gerer la configuration et la fonctionnalite d'un modele de semi-conducteur

Info

Publication number
EP1121656A2
EP1121656A2 EP99958445A EP99958445A EP1121656A2 EP 1121656 A2 EP1121656 A2 EP 1121656A2 EP 99958445 A EP99958445 A EP 99958445A EP 99958445 A EP99958445 A EP 99958445A EP 1121656 A2 EP1121656 A2 EP 1121656A2
Authority
EP
European Patent Office
Prior art keywords
design
file
user
integrated circuit
script
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP99958445A
Other languages
German (de)
English (en)
Inventor
James Hakewill
Mohammed Khan
Edward Plowman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARC International Ltd
Original Assignee
ARC Cores Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARC Cores Ltd filed Critical ARC Cores Ltd
Publication of EP1121656A2 publication Critical patent/EP1121656A2/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Abstract

Cette invention a trait à une méthode de gestion de la configuration, de paramètres de conception et de la fonctionnalité d'un modèle de circuit intégré (CI) à l'aide d'un langage de conception matérielle (HDL). Il est possible d'ajouter des instructions, de les retrancher ou de les produire à l'aide du concepteur et ce, de manière interactive durant le processus de conception, ainsi que de produire des descriptions HDL personnalisées du modèle de CI à l'aide de scripts reposant sur un jeu d'instruction et des données d'entrée édités par l'utilisateur. La description HDL personnalisée peut ensuite servir de base à la production de « façonneurs de fichiers » à des fins de simulation et/ou de synthèse de niveau logique. Cette méthode donne également la possibilité de produire un modèle HDL d'un dispositif complet, un microprocesseur ou un DSP. L'invention concerne également un programme informatique permettant de mettre en oeuvre la méthode susmentionnée ainsi qu'un matériel exécutant ce programme.
EP99958445A 1998-10-14 1999-10-14 Methode et appareil permettant de gerer la configuration et la fonctionnalite d'un modele de semi-conducteur Ceased EP1121656A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10427198P 1998-10-14 1998-10-14
US104271P 1998-10-14
PCT/IB1999/002030 WO2000022553A2 (fr) 1998-10-14 1999-10-14 Methode et appareil permettant de gerer la configuration et la fonctionnalite d'un modele de semi-conducteur

Publications (1)

Publication Number Publication Date
EP1121656A2 true EP1121656A2 (fr) 2001-08-08

Family

ID=22299556

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99958445A Ceased EP1121656A2 (fr) 1998-10-14 1999-10-14 Methode et appareil permettant de gerer la configuration et la fonctionnalite d'un modele de semi-conducteur

Country Status (5)

Country Link
EP (1) EP1121656A2 (fr)
KR (1) KR20010104622A (fr)
AU (1) AU1581100A (fr)
IL (1) IL142342A (fr)
WO (1) WO2000022553A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7325221B1 (en) * 2000-08-08 2008-01-29 Sonics, Incorporated Logic system with configurable interface
JP2002230065A (ja) 2001-02-02 2002-08-16 Toshiba Corp システムｌｓｉ開発装置およびシステムｌｓｉ開発方法
AU2003223746A1 (en) 2002-04-25 2003-11-10 Arc International Apparatus and method for managing integrated circuit designs
US20050049843A1 (en) * 2003-08-29 2005-03-03 Lee Hewitt Computerized extension apparatus and methods
DE102004044963A1 (de) * 2004-09-16 2006-04-06 Tatung Co., Ltd. Protokollverfahren für wiederverwendbare Hardware-IP bei einer System-on-Chip-Vorrichtung
US8156457B2 (en) 2009-09-24 2012-04-10 Synopsys, Inc. Concurrent simulation of hardware designs with behavioral characteristics
KR101635610B1 (ko) * 2015-05-15 2016-07-05 주식회사 휴윈 인쇄회로기판 전자장 및 회로 분석 시스템 및 방법
US10678975B2 (en) * 2017-11-07 2020-06-09 Amazon Tecnnologies, Inc. Code module selection for device design

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE505783C2 (sv) * 1995-10-03 1997-10-06 Ericsson Telefon Ab L M Förfarande för att tillverka en digital signalprocessor
US5812416A (en) * 1996-07-18 1998-09-22 Lsi Logic Corporation Integrated circuit design decomposition

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0022553A2 *

Also Published As

Publication number Publication date
WO2000022553A3 (fr) 2000-08-10
WO2000022553A2 (fr) 2000-04-20
IL142342A0 (en) 2002-03-10
IL142342A (en) 2005-12-18
KR20010104622A (ko) 2001-11-26
AU1581100A (en) 2000-05-01

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