EP1118120A1 - Boitier pour former un meilleur contact electrique et procedes de realisation correspondants - Google Patents

Boitier pour former un meilleur contact electrique et procedes de realisation correspondants

Info

Publication number
EP1118120A1
EP1118120A1 EP99935373A EP99935373A EP1118120A1 EP 1118120 A1 EP1118120 A1 EP 1118120A1 EP 99935373 A EP99935373 A EP 99935373A EP 99935373 A EP99935373 A EP 99935373A EP 1118120 A1 EP1118120 A1 EP 1118120A1
Authority
EP
European Patent Office
Prior art keywords
package
conductive
castellation
substrate
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99935373A
Other languages
German (de)
English (en)
Inventor
Trang N. Trinh
Mark A. Kuhlman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Conexant Systems LLC
Original Assignee
Conexant Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conexant Systems LLC filed Critical Conexant Systems LLC
Publication of EP1118120A1 publication Critical patent/EP1118120A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/09181—Notches in edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the printed circuit board [PCB] or at the walls of large holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention generally relates to a package for integrating electronic components. More particularly, the present invention relates to an electronic component package for electrically coupling one or more electrical components to a substrate.
  • Integration of one or more electrical components may be desirable for a variety of reasons. For example, it may be desirable to form a module that performs specific functions by integrating one or more electrical components such as microelectronic devices, inductors, capacitors, resistors, and the like. The modules may then be electrically attached to various substrates such as a printed circuit board (e.g., a motherboard for a computer), heat sinks, and the like.
  • a printed circuit board e.g., a motherboard for a computer
  • heat sinks e.g., a heat sinks, and the like.
  • the module generally includes a package configured to receive one or more electronic components and electrically attach to the substrate through conductive pads on a surface of the package.
  • the package also typically includes a conductive path electronically connecting at least some of the components to at least some of the pads such that the connected components are electrically coupled to the substrate.
  • packages to integrate electrical components before the components are attached to the substrate may be advantageous because, among other reasons, fewer electrical connections between the substrate and the package are required than if each electrical component were individually attached to the substrate. Also, the substrate may require less complexity because the package may be configured to provide some integration of the electrical components, thus reducing the amount of integration required at the substrate level. Also, integration costs may be reduced if at least some of the components can be integrated using the package rather than the substrate.
  • Packages for providing electrical connections between various electrical components and the substrate and methods for forming the packages are generally known in the art. For example, leadframe packages may be used to electrically connect one or more electrical components to the substrate.
  • Modules including leadframes generally include one or more electrical components attached to the leadframe and several conductive leadframe pins that serve as electrical contacts between the components and the substrate.
  • the leadframe module is attached to the substrate by soldering the leadframe pins to conductive bond pads resident on the substrate or the like.
  • Using leadframes to form electrical contacts between the electrical components and the substrate may be disadvantageous for several reasons. For example, it may be expensive to add leadframes to the respective modules. Also, the addition of the leadframe tends to increase the overall size of the module, which can increase material and fabrication labor costs associated with module manufacturing. Also, at high frequencies (e.g., RF) the leadframe pins may cause high inductance for the module; such high inductance may degrade module performance or performance of the electronic components attached thereto.
  • RF radio frequency
  • Modules including leadless chip carrier (LCC) packages to electrically connect one or more electronic components to the substrate are also known in the art.
  • the LCC package may include several conducting and insulating layers, wherein the conducting layers of the LCC may be connected to the electrical components, other conducting layers of the LCC, and conductive bond pads attached to the LCC to integrate the components and couple them to the substrate.
  • the module, and consequently the electronic components are coupled to the substrate by placing the bond pads of the LCC over solder pads of the substrate and causing conductive material (e.g., solder) to attach to both the LCC and the substrate.
  • One method for attaching the LCC module to the printed circuit board and forming electrical contacts between the module and the circuit board includes forming conductive castellations around the perimeter of the LCC and applying conductive material such as solder or conductive epoxy to the conductive castellations and the substrate solder pads.
  • the conductive castellations also suitably provide a conductive path between electrical components attached to the LCC and the substrate, the various conductive layers of the LCC, and the like.
  • the conductive castellations on the LCC are generally formed by drilling or punching holes through the LCC to form cylindrically-shaped vias, applying a conductive surface to the interior portion of the vias, and sawing or cutting through the vias to expose a portion of the via, thereby creating semi-cylindrical, conductive features around the perimeter of the LCC module.
  • Modules including LCC packages) that have conductive castellations about the module's perimeter may be advantageous for several reasons. In particular, high inductance problems associated with leadframe packages are reduced because the LCC package is attached directly to the substrate, thus reducing the conductive path length between the module and the substrate and the associated inductance.
  • Packages including conductive castellations may also be advantageous because test pads electrically connected to the castellations may be conveniently formed on a surface (e.g., a top surface) of the module. These test pads may be used to measure or test for continuity between the castellations of the package and the bond pads of the substrate and to test the electrical performance of the module and components attached thereto. Also, the conductive castellations of the device may be used to electrically connect two or more conductive layers within the LCC without additional device fabrication steps. In addition, using castellations to form electrical contact between the LCC device and the printed circuit board allows relatively easy visual inspection of the device's electrical connections between the module and the printed circuit board because the electrical connections are formed at the outside edge of the module.
  • conductive castellations may not provide a reliable conductive path between the electrical components and the substrate, between various conducting layers of the package, and the like.
  • the unreliability may be due to the sawing or cutting across the vias during castellation formation, which may cause the conductive surface initially attached to the interior portion of the vias to delaminate or to become stressed and susceptible to delamination. Conductive surfaces that have become stressed may delaminate due to, for example, temperature cycling which may occur during module use.
  • the delamination of the conductive surface may create electrical opens in the castellations of the LCC module. Electrical opens in the castellations of the module may in turn create electrical opens between the electrical components attached to the package and the bond pads on the printed circuit board, between various conductive layers of the package, and the like.
  • An LCC package may alternatively include solder contacts or the like at an interior portion of the package, that is, away from the perimeter of the package, and use conductive features, located at an interior portion of the package, to electronically connect various conductive layers of the package and electrical components attached thereto to the substrate.
  • the solder contacts of the package are typically in the form of conductive pads or balls; accordingly, the module including the LCC package having internal conductive pads is often referred to as a ball grid array module.
  • the pads of the ball grid array module are generally configured to electrically couple to bond pads on the substrate surface.
  • Ball grid array modules may be advantageous because the interior conductive features may be more reliable than conductive castellations. In contrast to castellations, the conductive elements of the ball grid array module are not sawed or otherwise cut; therefore, the conductive features remain generally intact during package formation. Consequently, the conductive features of the module and electrical connections made thereby are less susceptible to conductive material delamination and resulting electrical opens.
  • Ball grid array modules may, however, also suffer from several shortcomings.
  • the integrity of electrical contacts between the module and the substrate may be difficult to determine because the contact between the ball or contact pad of the module and the bond pad of the substrate is difficult to visually inspect (as mentioned above, the electrical contact is not formed at the outside edge of the module).
  • continuity and other electrical measurements between the module and the printed circuit board may be difficult to test or measure because the package typically does not include test pads electrically connected to the conductive features. Therefore a package that overcomes the shortcomings associated with prior art packages used to connect various electrical components to a substrate and methods for forming the same are required.
  • the present invention provides a package having improved electrical contacts for electrically coupling the package to a substrate and for electrically coupling the package to electrical components. While the way in which the present invention addresses the drawbacks of now known packages will be described in greater detail below, in general, in accordance with various aspects of the present invention, the inventive package provides improved electrical contacts that are reliable and easy to visually or otherwise inspect.
  • the package includes conductive castellations configured to electrically connect to conductive portions of the substrate and conductive features at an interior portion of the package. The conductive features are configured to electrically connect electrical components attached to the package and conductive layers of the package to the castellations.
  • the castellations are electrically connected to bond pads on a lower surface of the package, and the package bond pads are configured to electrically connect to conductive portions of the substrate.
  • test pads may be electrically connected to the castellations to allow continuity and other electrical measurements of a module including the package.
  • Figure 1 is an exploded view of a portion of an exemplary package and a portion of a substrate
  • Figure 2 is a perspective view of a portion of an exemplary package attached to a substrate.
  • the present invention generally relates to an apparatus for connecting electronic components, such as, for example, integrated circuits, resistors, capacitors, and the like, to a substrate.
  • inventive apparatus may include a variety of forms, the present invention will generally be described herein below as a package having one or more conductive layers configured to couple to the electronic components.
  • inventive apparatus may suitably include an integral, solitary unit without extrinsic electrical components attached thereto. The solitary unit may then be attached to the substrate.
  • Figures 1 and 2 a portion of a package 10 in accordance with a preferred embodiment of the present invention is shown.
  • package 10 is preferably configured to provide reliable electrical contacts to the electrical components attached to package 10 and to provide electrical contacts that are relatively easy to visually inspect.
  • package 10 includes a castellation 20, a conductive feature 30, and a contact pad 40.
  • Package 10 also suitably includes conductive layers such as conductive traces 50, 60, 70 and a test pad 80.
  • the various conductive layers are typically separated by a suitable insulating material, or a dielectric composition such as ceramic or glass materials, silicon materials, and the like.
  • package 10 may include any number of castellations 20, features 30, bond pads 40, test pads 80, and the like wherein the number of each element is generally determined by the module function and complexity. Furthermore, the specific configuration, size, and interconnecting arrangement of the conductive elements may vary from application to application.
  • Package 10 is generally configured to receive several electronic components on at least one surface of package 10 and to provide electrical connections between at least some of the components and a substrate 90.
  • the components are typically selected such that when the components are attached to package 10 and integrated with each other (e.g., by traces 50, 60, 70 and features 30 of package 10), the combination of the components (e.g. a semiconductor die 85) and package 10 forms a module that can be mechanically attached and electrically connected to substrate 90.
  • package 10 may include electrical components, such as resistors, capacitors, inductors, and the like, integral with package 10. Such integral components may be formed on the surface of package 10, interior to package 10, or any combination thereof.
  • an electrical path connecting the components to substrate 90 generally includes castellations 20, conductive features 30 (which generally connect various conductive layers of package 10), package bond pads 40, and conductive layers such as traces 50, 60, 70.
  • castellations 20 conductive features 30 (which generally connect various conductive layers of package 10), package bond pads 40, and conductive layers such as traces 50, 60, 70.
  • Using both features 30 and castellation 20 to form an electrical path between the components and substrate 90 provides a relatively reliable path that is relatively easy to visually inspect.
  • the path is reliable because the paths between various layers of package 10 are formed in an interior position of package 10.
  • the contact is relatively easy to inspect because the contact is formed at castellation 20 on the perimeter of package 10.
  • a specific conductive path for the component or portion thereof varies from application to application.
  • the path includes a conductive layer coupled to the component (e.g., die 85) and feature 30, a conductive layer such coupled to feature 30 and Contact Pad 40, and conductive material coupled to pad 40 and substrate 90.
  • this conductive path joining features 30 and contact pad 40 is formed at a bottom portion, and more preferably on a bottom surface 95 of package 10. Forming the electrical connection between pad 40 and feature 30 on bottom surface 95 creates a particularly reliable connection between the component and bond pad 40.
  • Protective insulating material may be added to package 10 to prevent unwanted electrical shorting or the like.
  • insulating material such as solder mask is applied to surface 95 of package 10 to prevent unwanted electrical shorting between conducting layers (e.g. trace 50) of package 10 and conducting portions of substrate 90.
  • substrate 90 may vary according to the particular application.
  • substrate 90 may be configured to provide package 10 and the module with a heat sink.
  • substrate 90 may include ceramic material or a laminated board such as a printed circuit board configured to perform various electronic functions.
  • the various configurations of substrate 90 suitably include conductive portions configured to facilitate electrical coupling between substrate 90 and package 10.
  • package 10 includes castellation 20 about the perimeter of package 10.
  • Castellation 20 generally includes a depression 100 on the perimeter of package 10 and a conductive material 110 attached to or integral with depression 100.
  • conductive material 110 may be integral with depression 100, in preferred embodiments of the present invention, conductive material 110 is coated or deposited onto the surface of depression 100.
  • Depression 100 may be in any form; however, depression 100 is preferably substantially partial or semi-cylindrical and spans substantially the entire height of package 10. In a particularly preferred embodiment of the present invention, the radius of the substantially cylindrical portion is approximately 10 mils before depression 100 is coated with material 110, and depression 100 may be coated with, for example, approximately 1 mill of conductive material 110.
  • the shape and size of castellations 20 may vary according to the specific configuration and/or function of package 10. For example, it may be desirable to have fewer and/or larger castellations for a particular application.
  • Conductive material 110 may include a variety of one or more materials and be coated, deposited, or the like onto or into depression 100 in a variety of ways.
  • conductive material 110 includes material that is wettable to materials used to mechanically bond and electrically connect package 10 to substrate 90. Such materials preferably include metals and are preferably deposited onto depression 100 by plating material 110 onto the exposed surface of depression 100. However other methods of depositing materials, including physical and chemical vapor deposition methods may suitably be used to deposit various films to form conductive material 110.
  • copper or gold is plated onto depression 100.
  • Conductive material 110 may include multiple films, and the films may perform various functions.
  • conductive material 110 may include a seed layer (not shown) applied to depression 100.
  • the seed layer preferably includes electroless copper.
  • Conductive material 110 may also include additional layers of nickel, gold, or the like to enhance wetting between conductive material 110 and material which forms a bond between castellation 20 and substrate 90.
  • Castellation 20 may be formed in a variety of ways.
  • castellation 20 is formed by drilling, punching, etching, or otherwise creating vias proximate the perimeter of package 10.
  • the vias are then typically coated with conductive material 110.
  • the vias are preferably coated with conductive material 110 by depositing electroless and electrolytic copper onto the surfaces of the vias.
  • the vias are coated by immersing package 10 in an electroless copper bath to coat package 10 with approximately 1 microinch of copper.
  • Package 10 may then be placed in an electrolytic copper bath to plate approximately 1 mil of copper onto package 10.
  • the copper may then be patterned and etched, using methods now known or hereafter devised by those skilled in the art, leaving the vias, and if desired, other portions of package 10 coated with copper.
  • conductive traces, electrical components, or a combination thereof may also be formed on the surface of package 10 during the patterning and etching steps of conductive castellation 20 formation.
  • castellation 20 may be formed by sawing or otherwise cutting through the via to form a substantially semi-cylindrical or substantially partial-cylindrical, conductive castellation 20.
  • castellation 20 may be formed by coating depression 100 with conductive material 110 after the vias are cut to form castellations 20.
  • depression 100 described above is formed by cutting through a substantially cylindrical via
  • the via may be of any suitable shape.
  • package 10 surface may be patterned with a square or other geometric shape, and the via may be formed by etching package 10 material to form a via with a corresponding cross section.
  • Conductive feature 30 is generally configured to form part of an electrical path between the component and substrate 90. As noted above and in accordance with the preferred embodiment of the present invention, conductive feature 30 is located at an interior portion of package 10 to increase reliability of the electrical path between the components, various conductive layers of package 10, and contact pad 40.
  • Feature 30 may also be suitably configured to facilitate integration of one or more electronic components electrically connected or integral to package 10. Electrical integration may be obtained by electrically connecting the components or portions thereof to other components or portions thereof through conductive layers (e.g., traces 50, 60, 70) of package 10 and coupling at least a portion of the conductive layers to at least a portion of conductive features 30.
  • the electrical components are typically attached and electrically connected to the surface of package 10 by attaching the component to bond pads (not shown) that may be suitably attached to or integrated with, for example, trace 70.
  • the components or portions thereof may then be suitably integrated by electrically coupling at least a portion of a first component to conductive feature 30 and connecting at least a portion of a second component to the same conductive feature 30 and the like.
  • any number of conductive layers may be electrically coupled to any number of features 30.
  • one conductive feature 30 may be electrically coupled to traces 50, 60, 70 and other features 30 may be connected to various subsets of electrical traces 50, 60, 70 or other conductive layers.
  • conductive layers such as traces 50, 60, 70 and electrical components
  • castellation 20 (e.g., die 85) attached to package 10 may be electrically connected to each other through castellation 20, according to preferred embodiments of the present invention, package 10 need not solely rely on castellation 20 as an interconnecting element. Rather, as noted above, various conductive layers of package 10 are preferably connected to each other using features 30. Consequently, the reliability of electrical paths connecting the conductive layers and the electrical components to substrate 90 are not dependent on the structural and electrical integrity of castellation 20. Nevertheless, as described in more detail below, it is preferable to have castellation 20 substantially intact, at least prior to module attachment to substrate 90, because, among other reasons, a substantially intact castellation 20 may enhance adhesion of materials used to attach package 10 to substrate 90. In addition, castellation 20 provides a conductive path that allows electrical testing of various electrical connections of package 10.
  • Conductive feature 30 may be formed during and in similar fashion to castellation 20 formation.
  • conductive feature 30 is formed by creating a via by drilling, etching, or the like through at least a portion of package 10.
  • conductive feature 30 is typically configured to penetrate through one or more conductive layers such as traces 50, 60, 70 such that the conductive layers may be electrically connected to form a conductive path between the layers and components attached to package 10.
  • conductive feature 30 typically includes a substantially conductive material surrounding the via.
  • conductive feature 30 includes about one microinch of electroless copper and about one mil of electroplated copper.
  • conductive layers such as traces 50, 60, 70 may be used to integrate one or more electronic components attached to or integral with package 10 or to electrically connect features 30 to bond pads 40.
  • the conductive layers are formed from materials with relatively low electrical resistance such as metals and the like.
  • the conductive layers include traces of patterned copper metal.
  • the conductive layers may be formed by any now known or hereafter developed method. For example, the layers may be formed by plating the conductive material onto a surface of package 10, patterning the conductive material with a composition resistant to an etchant, and etching the conductive material with the etchant.
  • the conductive layers may include a variety of forms. Preferably, at least a portion of the conductive layer includes a via pad 130, which is electrically connected to at least one conductive feature 30 of package 10.
  • Package 10 may include any number of conductive layers, which number is usually determined by the module's level of component integration. As stated above, not all conductive layers need to be electrically connected to all conductive vias 30 of package 10. For example, conductive layers such as traces 60, 70 may not include via pads 130 connected to one or more conductive features 30.
  • the conductive layers of package 10 are typically coupled to various features 30, during the formation of features 30 v by drilling through a portion of the conductive layer such as via pad 130 and coating the drilled portion with conductive material to form conductive feature 30.
  • the conductive layers are electrically coupled to features 30 by forming a conductive intersection between the layer and various features 30.
  • conductive trace 50 may be electrically coupled to feature 30 by forming a via through pad 130 connected to trace 50 and applying conductive material to pad 130 and the via.
  • Conductive layers may also connect features 30 to bond pad 40.
  • An electrical connection between package 10 and substrate 90 is generally formed to electrically couple castellation 20, Contact Pad 40, and a bond pad 140 of substrate 90.
  • Contact Pad 40 may be formed from a variety of materials and may be located at various locations on the surface of package 10.
  • pad 40 is formed of conductive material such as copper and is located on a bottom portion of package 10, and more preferably at the bottom perimeter of package 10.
  • Contact Pad 40 may be in the form of various shapes such as partial spheres and the like, pad 40 is preferably formed in a shape having a substantially rectangular cross section.
  • package 10 is electrically and mechanically attached to substrate 90 by aligning castellation 20 over bond pad 140 and applying conductive material or otherwise forming an electrical connection between castellation 20 and bond pad 140.
  • a piece of solder 150 may be used to attach package 10 to substrate 90 as well as electrically connect castellation 20 to bond pad 140.
  • a portion of solder 150 is placed between pad 40 and pad 140 to assist mechanical attachment of package 10 to substrate 90.
  • bond pad 140, Contact Pad 40, or a combination thereof may include solder or similar material which when heated, pressed against another conductive surface, or the like, forms a mechanical attachment and an electrical connection between substrate 90 and package 10.
  • conductive epoxy or the like may be used to mechanically attach and electrically connect package 10 to substrate 90.
  • conductive material 110 of castellation 20 preferably includes material that is wettable with respect to the material, such as solder or epoxy, used to attach package 10 to substrate 90. If the attachment material wets conductive material 110, the attachment material will generally adhere to conductive material 110 and be drawn up by capillary forces toward top surface 120 of package 10 as the material wets castellation 20. Solder piece 150, which wets conductive material 110 and is drawn up castellation 20, is illustrated in Figure 2.
  • Forming an electrical connection and a mechanical attachment between package 10 and substrate 90 at castellations 20, and more particularly at castellations 20 located at the perimeter of package 10, allows a person to visually inspect the electrical connection between package 10 and substrate 90.
  • the person may be able to determine whether castellation 20 is correctly aligned over bond pad 140, whether solder piece 150 was properly applied to both castellation 20 and bond pad 140, whether solder 150 wetted and adhered to castellation 20, and the like.
  • Package 10 may also include test pads 80 electrically connected to castellation 20 to allow the person to readily test for or measure continuity or other electrical parameters between various locations of package 10, between various locations of package 10 and various locations on substrate 90, any combination thereof, and the like.
  • test pad 80 may be located on any surface of package 10, as long as test pad location 80 allows the user to make desired electrical measurements.
  • test pad 80 is located on a top portion, and more preferably on top surface 120 of package 10.
  • pad 80 is proximate castellation 20. Placing pad 80 near castellation 20 may provide an additional benefit of increasing adhesion of conductive material 110 to depression 100.
  • top, bottom, and the like have been used throughout this application to refer to various directions or portions of the apparatus. These terms are used for reference to the drawing figures only and are not meant to limit possible configurations of the apparatus described hereinabove.
  • the present invention is set forth herein in the context of the appended drawing figures, it should be appreciated that the invention is not limited to the specific forms shown.
  • the device may include various numbers of conductive layers, features, and castellations, depending on the intended use for the apparatus.
  • Various other modifications, variations, and enhancements in the design and arrangement of the device as set forth herein may be made without departing from the spirit and scope of the present invention as set forth in appended claims.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

Cette invention se rapporte à un boîtier permettant de connecter des composants électriques à un substrat, ce boîtier comportant des parties crénelées conductrices sur son pourtour. Les parties crénelées sont configurées pour être connectées électriquement au substrat et à des éléments conducteurs à l'intérieur du boîtier. Les composants électriques peuvent être à leur tour connectés électriquement aux parties crénelées. On peut utiliser ce boîtier pour former un module en connectant électriquement les composants électriques au boîtier et en intégrant ces composants par connexion de divers composants ou de parties de ceux-ci à d'autres composants ou parties de ceux-ci.
EP99935373A 1998-09-30 1999-06-29 Boitier pour former un meilleur contact electrique et procedes de realisation correspondants Withdrawn EP1118120A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US163781 1988-03-03
US16378198A 1998-09-30 1998-09-30
PCT/US1999/014800 WO2000019532A1 (fr) 1998-09-30 1999-06-29 Boitier pour former un meilleur contact electrique et procedes de realisation correspondants

Publications (1)

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EP1118120A1 true EP1118120A1 (fr) 2001-07-25

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EP99935373A Withdrawn EP1118120A1 (fr) 1998-09-30 1999-06-29 Boitier pour former un meilleur contact electrique et procedes de realisation correspondants

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EP (1) EP1118120A1 (fr)
WO (1) WO2000019532A1 (fr)

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Publication number Priority date Publication date Assignee Title
JP4138211B2 (ja) * 2000-07-06 2008-08-27 株式会社村田製作所 電子部品およびその製造方法、集合電子部品、電子部品の実装構造、ならびに電子装置
US7506438B1 (en) 2000-11-14 2009-03-24 Freescale Semiconductor, Inc. Low profile integrated module interconnects and method of fabrication
CN102142411B (zh) * 2010-02-01 2012-12-12 华为终端有限公司 一种印刷电路组装板芯片封装部件以及焊接部件
US10128592B1 (en) * 2017-05-12 2018-11-13 Northrop Grumman Systems Corporation Integrated circuit interface and method of making the same

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US4551746A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
US5314606A (en) * 1993-02-16 1994-05-24 Kyocera America, Inc. Leadless ceramic package with improved solderabilty

Non-Patent Citations (1)

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Title
See references of WO0019532A1 *

Also Published As

Publication number Publication date
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