Classifications

• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/58—After-treatment
  • C23C14/5806—Thermal treatment
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/02—Pretreatment of the material to be coated
  • C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
  • C23C14/025—Metallic sublayers
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
  • C23C14/14—Metallic material, boron or silicon
  • C23C14/18—Metallic material, boron or silicon on other inorganic substrates
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/02—Pretreatment of the material to be coated
  • C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
  • C23C16/0281—Deposition of sub-layers, e.g. to promote the adhesion of the main coating of metallic sub-layers
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
  • C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
  • C23C16/14—Deposition of only one other metal element
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
  • H01L21/76846—Layer combinations

Definitions

• This invention relates generally to the fabrication of electronic devices, and particularly to a novel barrier film for electronic and electro-optic materials.
• Integrated circuits are composed of many millions (sometimes billions) of components such as transistors, resistors, and capacitors. These individual components are laid out in a two dimensional array on a substrate such as silicon or gallium arsenide. The two dimensional arrays are often stacked one on top of another to form a three dimensional IC . As in any circuit, these components, and the several layers, must be connected to one another electrically. Interconnection on the two dimensional surfaces is accomplished by depositing strips of metal that act as connecting "wires.” Likewise, the layers are interconnected by metal plugs deposited in via holes made between layers. These steps in the manufacturing process are commonly referred to as "metallization.”
• silicon is the substrate material of choice
• aluminum is the metal of choice for two dimensional IC metallization
• tungsten is the metal of choice for filling via holes for multiple layer interconnection. Silicon is preferred because it is cheap and abundant.
• Aluminum and tungsten are chosen because they have adequate electrical conductivity and they can be made not to diffuse into the substrate during the many annealing operations inherent in the IC manufacturing process.
• the electrical conductivity of aluminum and tungsten is limited, the "wires" and plugs must be made thick enough to ensure minimal resistance to electric current between components and between layers.
• the large size of these conductors has recently become an issue for IC designers and fabricators interested in placing a greater density of circuit elements on an IC .
• the lateral dimensions of the circuit elements must be reduced. This reduction in IC element size has two detrimental effects on the resulting IC .
• Copper which is a much better conductor of electricity than aluminum, is available as an alternative metallization material. Because of copper's greater electrical conductivity, copper imposes less resistance to the flow of electrons than aluminum or tungsten conductors having equivalent dimensions. The increasing density of components on today's ICs requires the smaller sized conductors that are only achievable by the use of highly conductive metallization materials .
• copper has one notable problem. It has a tendency to diffuse into silicon at elevated temperatures. This has precluded copper as a metallization candidate because ICs must be annealed several times during the manufacturing process. In order for copper metallization to be feasible, a technique must be developed that will prevent the diffusion of copper into silicon. Among the possible solutions currently under development within the semiconductor industry the most prevalent is the use of nitrides of the transition metals titanium and tungsten. The thickness of the metal-nitride layer required to stop copper diffusion into silicon effectively is in the range of tens to hundreds of nanometers, or hundreds to thousands of Angstroms (A) .
• An object of this invention is to provide a barrier film which is extremely thin, yet permits metallization using copper and other high conductivity metallic conductors which would otherwise have a tendency to diffuse into a substrate formed of a semiconducting or insulating material .
• Still another object is to provide a procedure for forming an extremely thin diffusion barrier, which produces consistent results rapidly and reliably, and which is not highly dependent upon the accurate maintenance of operating conditions such as time and temperature.
• Still another object is to provide a process for forming an extremely thin diffusion barrier which eliminates voids and mechanical stresses that can have detrimental effects on the substrate, the diffusion barrier, or the metallization layer. Disclosure of the Invention
• a semiconductor device is fabricated by forming, on a surface of a substrate material, a barrier film having a monolayer of metal atoms immediately adjacent the surface of the substrate material.
• a metallic conductor which has a tendency to diffuse into the substrate material, is then deposited onto the barrier film.
• Metallic conductors which have a tendency to diffuse into substrates of semiconductor or insulating materials include, for example, pure copper, copper alloys (e.g., Cu-Al , Cu-Si- Al) , copper doped with a dopant (e.g., aluminum) that impedes electromigration, gold, silver, or platinum.
• a "monolayer” is understood to refer to a two- dimensional array of atoms having the thickness of one atomic layer; although the monolayer may have minuscule defects such as minute portions with a thickness that exceeds one atomic layer and/or minute portions that are voids, the average thickness nonetheless essentially is an atomic layer providing essentially complete coverage of the directly underlying substrate surface regions.
• the monolayer which is extremely thin by definition, serves as a barrier film, inhibiting diffusion of the metallic conductor into the substrate material.
• the material upon which the monolayer of atoms is formed is often generally referred to herein as a "substrate" for such formation, and it will be appreciated that the term “substrate” as used herein can encompass a bulk wafer or, alternatively, a layer that is grown, deposited, formed or bonded upon another body.
• substrate can encompass a bulk wafer or, alternatively, a layer that is grown, deposited, formed or bonded upon another body.
• the present invention is especially concerned with substrates that are semiconductor or insulating materials.
• a monolayer is produced by depositing a metal halide upon a surface of a semiconducting or insulating substrate material where it first reacts with the substrate material and dissociates, releasing gaseous by-products formed of substrate atoms and halogen atoms of the precursor compound.
• This reaction is self-limiting resulting in formation of a monolayer of metal atoms on the substrate that thereafter enables a homoepitaxial film formed of the metal halide molecules to form thereon as the deposition process proceeds.
• This deposition operation can be carried out by various methods, but is preferably carried out by molecular beam epitaxy, or alternatively by r.f. sputtering.
• a temporary heteroepitaxial film has been formed on the substrate where the diffusion barrier is ultimately desired.
• the temporary heteroepitaxial film is subjected to a selective removal procedure, whereby the homoepitaxial portion of the deposited film having the halogen constituents is selectively eliminated while the monolayer of metal atoms remains behind attached to the surface of the substrate material.
• the removal procedure preferably is an annealing operation.
• chemical etching which is selective to remove the homoepitaxial portion of the deposited film while leaving the monolayer of metal atoms also can be used.
• the metal atom monolayer strongly adheres to the substrate material, and is not adversely affected by extended annealing times, high annealing temperatures, or chemical etching conditions.
• the precursor compound preferably comprises a metal halide, e.g., a barium, strontium, cesium or rubidium- halide salt.
• the thickness of the monolayer basically corresponds to the diameter of the metal atom constituent (s) of the monolayer.
• Metal atoms of barium, strontium, cesium, rubidium, and so forth have a thickness (i.e., the diameter of the largest electron orbital) of less than 5 A, so it can be appreciated that an extremely thin diffusion barrier layer is achieved by this invention.
• the semiconducting substrate materials that can be processed according to this invention include mono- or polycrystalline, doped or undoped, semiconductors, such as silicon, germanium, indium phosphide, gallium arsenide, silicon carbide, gallium nitride, aluminum nitride, indium antinomide, lead telluride, cadmium telluride, mercury-cadmium telluride, lead selenide, lead sulfide, tertiary combinations of these materials, and so forth.
• semiconductors such as silicon, germanium, indium phosphide, gallium arsenide, silicon carbide, gallium nitride, aluminum nitride, indium antinomide, lead telluride, cadmium telluride, mercury-cadmium telluride, lead selenide, lead sulfide, tertiary combinations of these materials, and so forth.
• the insulating substrate materials that can be processed according to this invention include doped or undoped silicon oxides (e.g., silicon dioxide), silicon nitride, phosphosilicate glass (PSG) , borophosphosilicate glass (BPSG) , barium fluoride, strontium fluoride, calcium fluoride, and so forth.
• a multiplicity of monolayers are formed contiguous with each other upon the substrate surface. This embodiment can become advantageous such as where a substrate is involved having a relatively greater surface roughness and it is necessary to account for any discontinuities in the surface profile by sufficiently building-up the diffusion layer to blanket the surface topography presented and provide complete coverage.
• MBE deposition can be used to sequentially deposit additional monolayers of metal atoms using an elemental source of the metal .
• a diffusion barrier film thickness can be assembled up to any desired thickness, but preferably is maintained at or below not more than 100 A, more preferably not more than 20 A to meet the primary objective of providing an extremely thin yet effective diffusion barrier.
• a semiconductor device is obtained by this invention in which a monolayer or several monolayers of metal atoms separates a metallic conductor from other materials in the device, such as semiconductor or insulating materials, in which the extremely thin diffusion barrier film serves as an effective barrier preventing atoms of the metallic conductor from diffusing into such other materials and either impairing the device or rendering it totally inoperative.
• FIG. 1 is a schematic cross-section depicting diffusion of copper into a silicon substrate, where no diffusion barrier is present;
• FIG. 2 is a graph illustrating the projected requirement in diffusion barrier thickness by the Semiconductor Industry Association;
• FIG. 3 is a schematic cross-section depicting the effect of a diffusion barrier in accordance with the invention
• FIG. 4 is a schematic diagram illustrating the process of deposition of a diffusion barrier precursor compound, and a metallization layer, onto a substrate by molecular beam epitaxy;
• FIGS. 5A-E is a schematical illustration showing the interfacial structure of the diffusion barrier on an atomic level as it is being formed on a semiconductor substrate after various process steps according to an inventive process;
• FIG. 6 is a schematic diagram illustrating the process of deposition of a diffusion barrier precursor compound onto a substrate by r.f. sputtering.
• FIG. 7A is a schematical illustration showing the interfacial structure of the barrier film on an atomic level where the barrier film is comprised of a plurality of contiguous monolayers
• FIG. 7B shows another embodiment of the invention where the barrier film is a composite monolayer formed of different types of metal atoms
• FIG. 7C shows yet another embodiment where the barrier film is comprised of a plurality of contiguous monolayers in which different monolayers thereof are formed of different types of metal atoms .
• FIG. 8 is a schematic cross-sectional view showing a diffusion barrier in accordance with the invention preventing diffusion of a copper plug into silicon substrate and into a silicon dioxide insulating layer overlying the substrate.
• FIG. 1 illustrates a typical attempt at copper metallization of a silicon semiconductor substrate 10.
• the substrate which is made up of silicon atoms 12, has two laterally delineated copper interconnect strips 14 deposited on its surface.
• copper atoms 16 tend to diffuse into the substrate, impairing its semiconducting properties, and usually rendering it totally inoperative, by effectively creating an electrical short circuit. Similar diffusion occurs at an interface between a copper conductor and a Si0 2 insulating layer, for example in the case in which an attempt is made to deposit a conducting copper plug in a via hole in the Si0 2 insulating layer.
• This invention provides an effective diffusion barrier having a thickness well below 100 A, and below 5 A in one exemplary embodiment, which is far below the minimum thickness projected by the industry data depicted in FIG. 2.
• the extremely thin diffusion barrier layers achievable by this invention potentially could be useable long after alternative technologies become obsolete.
• FIG. 3 a portion of an integrated circuit is schematically illustrated on an atomic level that comprises a silicon substrate 18 made up of silicon atoms 20, and having laterally delineated copper interconnect strips 22.
• a monolayer of barium (Ba) atoms 24 is interposed between the conductor strips 22 and the surface of the substrate 18 and effectively prevents diffusion of the copper atoms into the silicon.
• the layer of Ba atoms need only have a thickness of one atomic layer, i.e., a monolayer of approximately 5 x 10 "10 meters (5A) in thickness, in order to provide the desired barrier to diffusion of the conductor into the adjoining substrate.
• a diffusion barrier comprised of metal atoms and having a thickness of not more than approximately 5A is achievable by depositing a metal halide precursor compound on a semiconductor or insulating substrate so as to form a temporary heteroepitaxial film thereon.
• the resulting temporary heteroepitaxial film created by the metal halide and the substrate surface is subjected to a post- growth anneal or chemical etching in which all of the temporary heteroepitaxial film is eliminated by removal from the substrate except for an atomic layer of the metal component, i.e., a monolayer.
• This residual monolayer of metal atoms disposed in contact with the substrate surface provides a diffusion barrier to conductor materials.
• MBE molecular beam epitaxy
• RHEED Energy Electron Diffraction
• a diffusion barrier precursor compound effusion cell for example a barium fluoride, strontium fluoride or the like effusion cell, is provided at 32, and has a shutter 33.
• a shutter 35 is also provided for the silicon wafer 26.
• the substrate 26 is placed inside the chamber 30 and positioned by rotatable holder 28 and the chamber 30 is evacuated, using ion pumps and liquid nitrogen trapping to achieve a high vacuum.
• the substrate 26 is vacuum annealed to remove any passivation layer by deoxidation, for example silicon dioxide in the case of a silicon wafer.
• the temperature of the substrate 26 is then reduced to a suitable deposition temperature, and the effusion cell 32 is heated while the substrate 26 is mechanically rotated.
• the electron beam of a RHEED diagnostic system is focused onto the substrate 26 and the RHEED pattern is monitored.
• the shutters 35 and 33 in front of the substrate holder 28 and the effusion cell 32, respectively are opened to allow precursor molecules to impinge on the substrate surface 29.
• Deposition of the precursor 27 onto the silicon surface 29 begins, and is allowed to continue until the single crystal silicon RHEED pattern disappears and is replaced by a pattern corresponding to a single crystal layer of the precursor compound.
• Deposition is halted by closing the substrate and effusion source shutters 35 and 33, respectively.
• a temporary heteroepitaxial film derived from the precursor molecules is situated on the substrate surface 29, although the nature of the interface is more complicated as will become apparent from later descriptions herein.
• the substrate 26 should be at a temperature in the range from approximately 500°C to 800°C, and ideally at approximately 750°C, though the temperature will vary depending on the particular substrate and the processing tool.
• the pressure within the deposition chamber 30 should be 10 "8 mbar or less, more preferably 10 "9 mbar or less, and still more preferably
• the time required to achieve adequate deposition of the precursor sufficient to form the temporary heteroepitaxial film on the substrate is typically one or two minutes, but is not limited thereto.
• the temperature of the substrate is raised to cause precursor molecules to detach from the temporary heteroepitaxial film on the substrate.
• precursor molecules to detach from the temporary heteroepitaxial film on the substrate.
• barium atoms adjacent to the substrate remain tightly adhered thereto as a two- dimensional monolayer, while fluorine atoms (as bonded to other barium atoms) in the temporary heteroepitaxial film are effectively re-evaporated in the form of barium fluoride and eliminated from the temporary heteroepitaxial film.
• This will cause the RHEED pattern to change in appearance. Specifically, the "reappearance" of a RHEED pattern similar to that for the single crystal substrate confirms that the precursor molecules have been evaporated.
• the substrate temperature at which the detachment of the precursor molecules with the halogen atoms from the temporary heteroepitaxial film takes place during the post-growth anneal step is not necessarily limited, but should be in the vicinity of 750°C to 1000°C, preferably 800°C.
• the monolayer of metal atoms which remains on the substrate serves as the diffusion barrier between the substrate and any metallization layer subsequently deposited upon it.
• the metallization layer can be deposited by any of various standard microelectronic metallization methods, and, in this embodiment, it can be conveniently deposited while the substrate is still in the MBE chamber by operation of the electron beam source.
• BaF 2 molecules 50 are directed and impinged onto the surface 51 of a silicon substrate 52, such as by MBE deposition.
• a silicon substrate 52 such as by MBE deposition.
• BaF 2 is used to illustrate the metal halide
• silicon is used to illustrate the (semiconductor) substrate, although other materials can be used as indicated elsewhere herein.
• the silicon surface 51 to be used as the deposition substrate has a highly planar, smooth surface to minimize the coating thickness needed to provide complete coverage thereof.
• Deoxidation annealing, chemical-mechanical- planarization (CMP) polishing or ion milling can be used in a pretreatment of the silicon surface prior to deposition of the diffusion barrier to enhance the planarity and smoothness of silicon surface, if necessary.
• CMP chemical-mechanical- planarization
• the inventive process itself provides some measure of in si tu planarization of the silicon surface during MBE deposition.
• the BaF 2 molecules react with silicon atoms 51a, 51b, 51c, and so forth, at the surface 51 of the silicon substrate 52.
• FIG. 5B depicts compound 53 as two halide atoms (white circles) bonded to a common metal atom (darkened circle) , it will be understood that this illustrative only because other gaseous metal-halides may be generated, such as tetrahalides of silicon where the substrate 52 is silicon.
• the escaping gas 53 would be GaF .
• This etching-like effect upon the surface silicon atoms serves to effectively smoothen the silicon surface.
• the barium atoms left behind bond with dangling bonds of the surface silicon atoms, forming a monoatomic layer 54 of metal atoms, i.e., a metal monolayer of barium atoms.
• This deposition step proceeds for a sufficient duration of time to form a continuous layer of barium atoms across the surface of the silicon substrate without leaving any bare spots .
• barium fluoride 50 deposition via MBE is continued from a molecular beam.
• this subsequently introduced barium fluoride adheres to the barium monolayer 54 and grows epitaxially thereon to form a temporary homoepitaxial film portion 55.
• the amount of subsequent deposition of epitaxial barium fluoride on the barium monolayer is allowed to be enough to provide a safety measure which ensures complete substrate coverage with a monolayer of barium atoms.
• a heteroepitaxial film 56 is formed on the substrate surface 51 comprising a monolayer 54 of metal (e.g., Ba) atoms as an interaction regime attached directly to the substrate surface 51 and a homoepitaxial regime 55 comprised of oriented molecular metal halide (e.g., barium fluoride) formed, in turn, on the monolayer 54.
• the homoepitaxial regime 55 of BaF 2 of the temporary heteroepitaxial film 56 is (100) -oriented on silicon (100), and (111) -oriented when the substrate is silicon (111), GaAs (100), or GaAs (111).
• XPS measurements have confirmed that barium atoms have the two above-mentioned different chemical states, i.e., the interaction (metal monolayer) and the homoepitaxial regimes, in the temporary film present at this stage of processing.
• the relative abundance of these two states has also been determined by XPS.
• the number of barium atoms in each state is determinable by normalizing integrated XPS peak intensities to HIBS measurements of the total number of barium atoms on the surface.
• the results of these analyses confirm that BaF 2 first reacts with the silicon surface during initial MBE deposition at the silicon surface and dissociates, releasing a gaseous silicon-fluorine compound.
• This reaction is self-limiting, resulting in a barium monolayer that enables subsequent BaF 2 molecules to form an epitaxial (111) -oriented film on the silicon surface. Then, a post-growth anneal affects evaporation of the barium fluoride deposited on the monolayer.
• a vacuum anneal is performed to cause evaporation of barium fluoride 57 from the temporary heteroepitaxial film such that the barium fluoride content found in the homoepitaxial portion thereof (feature 55 in FIG. 5D) is completely removed back to the monolayer 54 of barium atoms attached to the silicon surface 51.
• the homoepitaxial portion 55 of the temporary heteroepitaxial film can be removed by etching (e.g., chemical etching) which is selective between the homoepitaxial portion 55 and the monolayer portion 54 such that the former can be removed while leaving the latter intact.
• etching e.g., chemical etching
• the MBE deposition of the temporary heteroepitaxial film and the post-growth anneal can be performed in the same processing chamber without breaking the vacuum between the two procedures.
• the MBE deposition can be performed in a first processing tool, after which the vacuum is broken, and the workpiece is then transferred to another processing tool for separately performing the post-growth anneal at which time the substrate is heated up again with a vacuum being created in the second processing tool.
• the homoepitaxial portion of the temporary heteroepitaxial film serves as a protective coating over the monolayer portion of the heteroepitaxial film during such transit between separate processing tools.
• the underlying mechanism by which the metal monolayer prevents diffusion of the copper, or other highly diffusive metal, through the barrier layer into the semiconductor or insulating substrate is at least in part attributable to the fact that metal atoms are provided in the monolayer which have relatively large electron clouds which can overlap or touch each other between the metal atoms to effectively form an energy barrier against movement of copper atoms therethrough.
• the electron clouds are also spoken of as atomic orbitals occupied by electrons in different energy levels or shells, and the electron cloud is a cloud of negative charge formed of electrons of an electron density distribution corresponding to the element at issue.
• the diffusion barrier layer can be formed.
• the precursor e.g., BaF 2 or SrF 2
• the precursor can be deposited for a sufficient duration of time to ensure complete coverage of the silicon substrate.
• Such complete coverage can be achieved within relatively short period of time, e.g., about one minute using MBE deposition of a metal halide on the substrate, depending on deposition conditions.
• the length of deposition time is not critical provided it is at least high enough to establish the diffusion barrier film; deposition times of several minutes are not detrimental to the procedure, and the deposition temperature also is not critical.
• the second step all components of the precursor except for the monolayer of metal atoms, are removed by the post-growth annealing procedure.
• the metal atoms of this thin layer adhere tightly to the substrate, and consequently, the second step can be carried out over a wide range of time and temperature conditions without adversely affecting the formation and character of the diffusion barrier layer.
• BaF 2 can be used as the barrier film precursor and a silicon wafer can be used as the substrate.
• the silicon substrate first is deoxidized by vacuum annealing at 900°C for one hour to remove the silicon dioxide passivation layer. Then the substrate can be brought to a deposition temperature of 750 °C in a VG Semicon V80H MBE growth chamber at a vacuum of less than 1 x 10 "10 mbar. All temperature measurements are made from a noncontact thermocouple gauge.
• a BaF 2 effusion cell can be heated to 1050°C. While the substrate holder is mechanically rotated, an electron beam from a RHEED diagnostic system is directed toward the substrate.
• the beam is focused until the RHEED pattern of a single crystal silicon surface appears on the RHEED screen.
• the shutters in front of the substrate holder and the effusion cell are then opened to allow BaF 2 molecules to impinge on the substrate surface.
• Deposition of BaF 2 is allowed to continue until the single crystal silicon RHEED pattern disappeared and is replaced by a single crystal BaF 2 pattern.
• Deposition is then halted by closing the substrate and effusion source shutters.
• the substrate temperature is then raised to 800°C and held until a RHEED pattern similar to that of the single crystal silicon substrate reappears.
• the precursor compounds that can be used include, for example, BaF 2 , BaCl 2 , SrF 2 , SrCl 2 , CsFl, CsCl, RbF, and RbCl, and the like.
• metal halide salts that have cubic halide, e.g. a cubic fluorite, crystal structure.
• metal halides e.g., BaF 2 , BaCl 2 , SrF 2 , SrCl 2 , CsFl, CsCl, RbF, and RbCl, and the like, that have cubic crystal structure will tend to provide sources of metal atoms that are amenable to the above- discussed decomposition reaction and interaction with the silicon surface under readily implementable MBE and annealing processing conditions.
• metal halide salts may not be suitable for many processing environments as they do not normally decompose under typical MBE conditions .
• the monolayer of metal atoms alternatively can be formed in a one step operation (i.e., without a post-growth anneal step) by directly depositing an elemental form of the metal atoms, such as barium, via MBE on the surface of the semiconductor substrate. Since certain elemental metals such as barium are highly reactive, appropriate precautions have to be taken to handle, maintain and process the elemental barium in an inert environment, e.g., under an argon gas atmosphere, up until it is deposited upon the semiconductor.
• the monolayer of metal atoms directly on the semiconductor substrate by the above-described two-step decomposition reaction process involving a metal halide (i.e., MBE deposit/post-growth anneal) , and then to increase the thickness of the diffusion barrier film by depositing one or more additional monolayers of metal atoms on the original monolayer through depositing the elemental form of the metal atoms, such as barium, via MBE on the original monolayer.
• a metal halide i.e., MBE deposit/post-growth anneal
• the metal atom can be deposited from an elemental form via MBE on the surface of the silicon substrate.
• a plurality of monolayers can be formed as contiguous layers upon the substrate to form an overall thickness in the diffusion barrier layer of any desired thickness. Since thin thicknesses are desired, the diffusion barrier preferably is built up to an overall thickness that does not exceed 100A, and more preferably does not exceed 20A.
• FIG. 7A illustrates this scenario in which a plurality of monolayers 71a, 71b, and 71c are sequentially formed, upon the surface 72 of substrate 73, one on the other, in the manners described above. Then, a conductor material or other material (not shown) can be formed over the outermost monolayer 71c.
• each of monolayers 71a, 71b, and 71c are formed of the same type of metal atoms, and together, they form the barrier film. Also, while three monolayers are depicted in FIG. 7A, the plurality of monolayers can be two or more.
• FIG. 7B illustrates this embodiment of the invention where the barrier film is a composite monolayer 71 formed of different types of metal atoms 71d and 71e. Two or more different types of metal atoms can be provided in the composite monolayer 71. Then, a conductor material or other material (not shown) can be formed over the composite monolayer 71.
• the different monolayers can have the same or different types of metal atoms by appropriate selection of the precursor compounds at the different stages of processing.
• the barrier film is comprised of a plurality of contiguous monolayers 71f, 71g and 71h in which different monolayers thereof are formed of different types of metal atoms.
• layers 71f and 71h are formed of the same type of metal atoms while intervening monolayer 71g is formed of a metal atom that is different from the metal atoms in layers 71g and 71h.
• barrier film arrangements with three or more monolayers containing the different types of metal atoms must alternate through the stack of monolayers in any particular pattern.
• three monolayers are depicted in FIG. 7C, the embodiment is not limited to that plural number.
• composite monolayers, such as described in FIG. 7B can be used in combination with one or more contiguous monolayers formed thereon having a single type of metal atoms, such as shown in FIG. 7A, or different types of metal atoms in different respective monolayers, such as illustrated in FIG. 7C.
• r.f. sputtering such as depicted in FIG. 6, can be used.
• an argon-ion gun 38 directs a beam 40 onto a supply (target) 42 of barium fluoride, for example, causing deposition of barium fluoride onto a substrate 44 by sputtering.
• the post- growth annealing of the substrate can take place within the sputtering chamber in order to remove BaF 2 molecules and the fluorine atoms leaving only a thin layer of barium atoms as a monolayer adhering to the surface of the substrate.
• the metallization (conductor) layer can also be applied to the substrate while it is inside the sputtering chamber.
• Sputtering can also be used to deposit a diffusion barrier of other metal atoms, such as strontium atoms, in a similar manner.
• a combination of different types of metal atoms could be sputtered in the same monolayer or in different monolayers using different sputtering targets formed of different respective metal halide precursors.
• MBE is superior to r.f. sputtering because sputtering can cause dissociation of the barium-fluorine bond before the barium fluoride molecule reaches the substrate surface which facilitates the formation of the temporary heteroepitaxial film.
• deposition processes other than MBE and r.f. sputtering can be used, for example, physical and chemical vapor deposition, wet chemical processes, and liquid phase epitaxy.
• precursors used in metal-organic chemical vapor deposition (MOCVD) to form the diffusion barrier on a semiconductor or insulating substrate include Ba (2,2,6,6- tetramethyl-3 , 5 heptanedionate) and Sr (2 , 4-pentanedionate) .
• the diffusion barrier produced in accordance with the invention can be used not only to prevent diffusion of conductor metals into a semiconductor substrate, but also to prevent diffusion of the conductor metal into an insulating layer.
• layer 46 is a semiconductor substrate, for example, a semiconducting layer of silicon
• layer 48 which overlies layer 46, is an insulating layer of silicon dioxide (Si0 2 ) .
• a plug 45 of a metal, such as copper, is located in a via hole though insulating layer 48, and makes ohmic contact with the semiconducting layer 46 through a thin diffusion barrier layer 47 of barium formed by one of the processes described above.
• This plug is used to conduct current between layer 46 and another layer (not shown) which is separated from layer 46 by insulating layer 48.
• the sidewall of the via hole is lined with a barium diffusion barrier 49, which prevents diffusion of the copper into the insulating layer.
• the barium or strontium atoms are deposited onto an insulating layer in the same way in which they are deposited onto silicon.
• the minimization of the thickness of the side wall diffusion barrier 49 makes it possible to use copper for interconnections between layers.
• the copper interconnects can be significantly narrower than tungsten interconnects having the same current capacity, and the diffusion barrier is also very thin.
• the use of the diffusion barrier in accordance with the invention as a liner for via holes in insulating layers can contribute significantly to the minimization of the lateral dimensions of an integrated circuit of which the elements shown in FIG. 8 are a part.
• the diffusion barrier 49 is very thin, it permits the use of via holes of relatively low aspect ratio, making them easier to fill with conducting metal and eliminating voids which result in failures or rejection of ICs.
• the material used for forming the diffusion barrier can be any appropriate metal in elemental form or precursor molecular compound from which a layer of metal atoms (i.e., a monolayer) can be formed on a semiconductor or insulating substrate.
• the substrate material upon which the diffusion barrier is formed is not particularly limited and can include semiconductor materials and insulating materials used in semiconductor device fabrications.
• the semiconductor material can be, for example, Si, Ge, InP, GaAs, SiC, GaN, AlN, InSb, PbTe, CdTe, HgTe, Hg.Cd ⁇ .Te, PbSe, PbS, and tertiary combinations of these materials .
• the semiconductor material can be monocrystalline or polycrystalline .
• the semiconductor substrate can be in bulk wafer form, deposited or grown layer form (e.g., epitaxially grown), or silicon-on-insulator (SOI) form.
• the semiconductor can be doped or undoped with impurities (e.g., p-, n-doping) .
• the insulating substrate material can be, for example, SiO x , Si0 2 , BaF 2 , SrF 2 , CaF 2 , silicon nitride, PSG, or BPSG.
• a thin diffusion barrier film formed of a barium, strontium or cesium monolayer (or monolayers) can be used to line via holes in insulators made of BaF 2 , SrF 2 and CaF 2 .
• these include conventional metals and metal alloys used for wiring line, interconnects, bonding pads, and so forth, in semiconductor device or opto-electronic device fabrication.
• the present invention is especially useful for providing an in si tu barrier to electrically conductive metals which tend to diffuse into semiconductor and insulating materials common to semiconductor processing.
• These conductive metals include, for example, pure copper, copper alloys (e.g., Cu-Al, Cu-Si-Al) , copper doped with a dopant (e.g., aluminum) that impedes electromigration, gold, silver, or platinum.
• the conductor material can be deposited on the diffusion barrier by any conventional technique, including, e.g., electroplating, electroless deposition, sputtering, chemical vapor deposition, e-beam evaporation, and so forth.
• electroplating electroless deposition
• sputtering chemical vapor deposition
• e-beam evaporation and so forth.
• copper can be deposited by e-beam evaporation at lxlO "9 millibars in a heated chamber, or at lOxlO "11 millibars under a nitrogen environment.
• the conductor film can be patterned on the diffusion barrier by various techniques, such as by conventional additive or subtractive processes known and used in semiconductor processing (e.g., photolithographic processing).
• the invention can also be used to prevent diffusion of gallium and/or arsenic from gallium arsenide into silicon and other substrates.
• a principal advantage of this invention is that the thickness of the diffusion barrier layer can be made extremely thin.
• the thickness of the diffusion barrier layer according to this invention will generally be formed in the range of approximately 5 A to 100 A.
• the diffusion barrier can be made as thin as one monolayer, which will have a thickness slightly less than 5 A corresponding the atomic diameter of the metal atoms forming the diffusion barrier.
• the diffusion barrier formed of one monolayer having a thickness less than 5A in thickness will satisfactorily inhibit diffusion of copper and other conductors into the substrate.
• the thickness of the diffusion barrier layer will tend to vary.
• the diffusion barrier layer on a substrate having a surface roughness greater than 5A may be formed so as to have a thickness value in the range of approximately 5 to 100 A, with metal atoms of the diffusion barrier layer accumulating at any step edges on the substrate surface.
• the diffusion barrier film of this invention is only one monolayer or a multiple number of contiguous monolayers formed on the substrate surface, and in any event, it need not be more than approximately 100A in total thickness to achieve the objectives of this invention for current and future anticipated semiconductor device fabrication specifications.
• a large scale integrated circuit having copper conductors and a diffusion barrier film according to this invention with a thickness in the range of approximately 5A to approximately lOOA can achieve an extremely high component density, which reduces the number of layers required for a given number of components, and very low heat dissipation.
• the diffusion barrier thickness can vary from a thickness less than about 5A to a greater thickness, which can be up to about lOOA, preferably up to no more than 20A.
• Conventional alternative diffusion barriers are significantly thicker than lOOA.
• the diffusion barrier film where it is barium or strontium, or a similar metal, is compliant, i.e., it is mechanically soft and easily deformable.
• the compliance of the diffusion barrier film allows dissimilar materials to be put together without introducing defects, such as voids or mechanical stresses, at the interface which may have detrimental effects on device performance, the diffusion barrier film, or the metallization layer.
• barium and strontium, or like metals can form intermetallic compounds with copper (BaCu 12 and Cu 5 Sr are examples) , causing copper atoms to be tightly bound to the barium or strontium at the interface and unable to migrate past the barium or strontium layer into the silicon.
• barrier film based on one or more monolayers of metal atoms that is used in this invention has been illustrated herein specifically as a barrier to diffusion of metal conductors into substrate materials, it will be understood that the barrier film is not necessarily limited to that use alone, as it possesses many advantageous attributes that could be exploited in semiconductor device fabrications.
• the barrier film could be used as a barrier layer in the fabrication of semiconductor laser devices, such as those having heterojunctions and incorporating different semiconductor materials, e.g., GaAs on top of silicon.

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