EP1089084B1 - Essai en ligne du réseau d'interconnexion programmable d'un réseau de portes programmables - Google Patents

Essai en ligne du réseau d'interconnexion programmable d'un réseau de portes programmables Download PDF

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EP1089084B1
EP1089084B1 EP00308136A EP00308136A EP1089084B1 EP 1089084 B1 EP1089084 B1 EP 1089084B1 EP 00308136 A EP00308136 A EP 00308136A EP 00308136 A EP00308136 A EP 00308136A EP 1089084 B1 EP1089084 B1 EP 1089084B1
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Prior art keywords
testing
self
area
routing resources
groups
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German (de)
English (en)
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EP1089084A1 (fr
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Miron Abramovici
Charles E. Stroud
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University of Kentucky Research Foundation
Lattice Semiconductor Corp
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University of Kentucky Research Foundation
Lattice Semiconductor Corp
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G01R31/318519—Test of field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates generally to the field of testing of integrated circuit devices and, more particularly, to a method of testing the programmable interconnect network in field programmable gate arrays.
  • a field programmable gate array is a type of integrated circuit consisting of an array of programmable logic blocks interconnected by a programmable routing network and programmable input/output cells. Programming of the logic blocks, the routing network and the input/output cells is selectively completed to make the necessary interconnections that establish one configuration thereof to provide the desired system operation/function for a particular application.
  • the present inventors have recently developed methods of built-in self-testing the array of programmable logic blocks and the programmable routing network in FPGAs at the device, board and system levels. These methods are set out in detail in US-A-5 991 907, US-A-6 003 150, US-A-6 108 806 and EP-A-1 063 529. A similar method can also be found in EP-A-0 646 867.
  • On-line testing and fault tolerant operation of FPGAs is most important in high-reliability and high-availability applications, such as, space missions or telecommunication network routers in which adaptive computing systems often rely on reconfigurable hardware to adapt system operation. In such applications, the FPGA hardware must work continuously and simply cannot be taken off-line for testing, maintenance, or repair.
  • the FPGA resources When faults are detected and located in the FPGA hardware of these systems, the FPGA resources must be quickly reconfigured to continue operation in a diminished capacity or to avoid the identified faulty resources altogether. Necessarily, therefore, testing of the FPGA resources must be performed concurrently with normal system operation.
  • the method of testing field programmable gate arrays is carried out during normal on-line operation of the FPGA by configuring the FPGA resources into a working area and an initial self-testing area.
  • the working area maintains normal operation of the FPGA under test throughout testing. Within the initial and subsequent self-testing areas, however, all the resources of the programmable routing network are tested.
  • the working area is substantially unaffected by the testing, and testing time constraints are reduced since normal operation continues in the working area.
  • test patterns are generated and propagated along groups of wires under test.
  • the output patterns of a first group of wires under test are preferably compared to the output patterns of a second group of wires under test within the self-testing area receiving the same patterns.
  • the groups of wires under test include wire segments of varying lengths interconnected by configuration interconnect points.
  • configuration interconnect points There are two basic types of configuration interconnect points, including cross-points and break-points, and each generally includes a transmission gate controlled by a configuration memory bit.
  • the groups of wires under test preferably include programmable logic blocks configured to allow the propagating test patterns to pass there through without alteration.
  • the programmable logic blocks are configured as identity functions.
  • this allows both global routing resources between programmable logic blocks and local routing resources leading to each programmable logic block to be tested.
  • test result data is generated based on the outcome of the comparison. Passing test result data is generated if the corresponding test patterns match. If a mismatch occurs, a failing test result indication or data is generated.
  • a failing test result or mismatch may be caused by a fault in a wire segment, a configuration interconnect point or a programmable logic block of the groups of wires under test in the self-testing area.
  • the preferred method of the present invention further includes the step of comparing the output of the first group of wires under test to the output of the second group of wires under test and the output of a third group of neighboring wires under test. This type of multiple testing substantially eliminates the potential for not detecting equivalent faults.
  • parallel testing of the programmable routing resources may be utilized. Specifically, comparisons of the output patterns of the groups of wires under test may be made at several locations along the groups of wires under test. Advantageously, one set of test patterns may be used to test several differing groups of wires per configuration. In addition, the test result data from several compared groups of wires under test may be combined utilizing an iterative comparator. Alternatively, the test result data can be routed directly to an input/output cell of the FPGA under test. Advantageously, this latter approach provides information regarding the location of the fault in the FPGA under test, as opposed to a single pass/fail test result indication for the entire test.
  • the self-testing area of the FPGA under test may be divided into vertical and horizontal self-testing areas.
  • vertical wire segments are tested utilizing the vertical self-testing area and horizontal wire segments are tested utilizing the horizontal self-testing area.
  • programmable logic blocks in both self-testing areas, vertical wire segments in the vertical self-testing area, and horizontal wire segments in the horizontal self-testing area are all designated reserved or unusable during operation of the FPGA under test. In this manner, connections between working area programmable logic blocks may be made utilizing horizontal wire segments through the vertical self-testing area and vertical wire segments through the horizontal self-testing area.
  • the FPGA under test Upon completion of testing of the programmable routing resources located within the initial self-testing area, the FPGA under test is reconfigured so that a portion of the working area becomes a subsequent self-testing area, and the initial self-testing area becomes a portion of the working area.
  • the self-testing area roves around the FPGA under test repeating the steps of reconfiguring and testing the programmable routing resources in the self-testing areas until each portion of the working area, or the entire FPGA, is reconfigured as a subsequent self-testing area and tested.
  • the present method of testing allows for normal operation of the FPGA under test to continue within the working area throughout testing, uninterrupted by the testing conducted within the self-testing areas.
  • test and reconfiguration controller accesses the FPGA under test during normal system operation and configures the FPGA with one of a plurality of test configurations stored in the associated storage medium.
  • test patterns generated within the self-testing area provide for exhaustive testing of the groups of wires under test. The test patterns are propagated along the groups of wires under test and the output patterns compared.
  • a typical field programmable gate array generally consists of an array of programmable logic blocks interconnected by a programmable routing network and programmable input/output cells or boundary-scan ports (most FPGA's feature a boundary scan mechanism).
  • Such structures are, for example, featured in the Lucent ORCA® programmable function units, in the Xilinx® XC4000 configurable logic block, and in the ALTERA® FLEX® 8000 logic element.
  • the resources of the programmable routing network of the FPGA under test are completely tested during normal operation by configuring the FPGA into a working area and a self-testing area.
  • the working area is substantially unaffected by the testing conducted within the self-testing area.
  • test and reconfiguration controller 12 As shown in schematic block diagram in Figure 1, the steps of configuring, testing, roving, and reconfiguring the resources of an FPGA under test 10 are necessarily controlled by a test and reconfiguration controller 12.
  • an external test and reconfiguration controller 12 is utilized because present commercially available FPGAs do not allow internal access to their configuration memory. Accordingly, a configuration decompiler tool of a type known in the art is utilized to determine the intended function or mode of operation of the FPGA resources. Alternatively, this information may be extracted from the design stage and made available to the controller 12.
  • any controller e.g., internal or external to the FPGA, could be utilized with an FPGA that allows for internal access to its configuration memory and that a single test and reconfiguration controller is capable of controlling several FPGAs.
  • a one-to-one controller to FPGA ratio is utilized.
  • the preferred controller 12 may be implemented on an embedded microprocessor in communication with a storage medium or memory 14 for storing the configurations and test data.
  • the controller 12 accesses the system platform including FPGA under test 10 through its boundary-scan ports in a known manner such that access is transparent to the normal function of the FPGA 10.
  • this approach allows for complete on-line testing during normal operation of the FPGA 10 under test.
  • the controller 12 and memory 14 further exchange and store fault status data for the programmable routing resources.
  • the FPGA under test 10 is initially configured by the controller 12 into an initial self-testing area 16 and a working area 18 as shown in Figure 2.
  • the working area 18 maintains normal operation of the FPGA under test 10 throughout testing.
  • the resources of the programmable routing network are exhaustively tested.
  • the programmable routing resources include both global routing resources for carrying signals amongst the array of programmable logic blocks (PLBs), and local routing resources for carrying signals into and out of the PLBs.
  • PLBs programmable logic blocks
  • the typical global and local routing resources associated with a single PLB are shown in Figure 3 and are discussed in more detail below.
  • a first group of PLBs within the initial self-testing area 16 are configured to include a test pattern generator (TPG) 20 and an output response analyzer (ORA) 22, and a portion of the programmable routing resources are configured to include at least two groups of wires under test (WUTs) 24, 26.
  • the first group of WUTs 24 may include wire segments 27, 28, 29, 30, 31 and 32, configurable or configuration interconnect points (CIPs) 33, 34 and 35, and PLBs 36, 37.
  • a second group of WUTs 26 may include wire segments 38, 39, 40, 41 and 42 and CIPs 43, 44 and 45.
  • exhaustive test patterns generated using the TPG 20 are propagated along the groups of wires under test 24, 26.
  • the outputs of the groups of WUTs 24, 26 are compared by the ORA 22 to determine whether a fault exists within either group of WUTs 24, 26.
  • a match/mismatch result of the comparison performed by the ORA 22 is communicated as a pass/fail test result or fault status data through the boundary-scan ports of the FPGA (not shown) to the controller 12 for storage in memory 14.
  • the operation of the TPG 20 and ORA 22 in testing the groups of WUTs 24, 26 is similar to the built-in self-test techniques utilized and described in detail in the above-noted pending U.S. patent applications.
  • the exhaustive set of test patterns generated by the TPG 20 must be suitable to detect all shorts among the WUTs 24, 26 and all stuck-open faults for the closed CIPs (e.g., 33, 34, 35, 43, 44 and 45) along the WUTs.
  • the open CIPs e.g., 47, 48, 49, 50 and 51
  • the TPG 20 should also control any wire segment (e.g., 52, 53, 54 and 55) that could become shorted to a wire segment under test 24, 26.
  • a contrary test pattern or a 1(0) test pattern should be propagated along wire segments 52, 53, 54 and 55 at least once during the test.
  • a typical CIP 56 or switch includes a transmission gate 57 controlled by a configuration memory element or bit 58.
  • a typical PLB 66 includes a memory block 67, a flip-flop block 68 and a combinational output logic block 69.
  • the memory block 67 may be configured to operate as random access memory (RAM) or as a combination look-up table (LUT).
  • combinational logic within the memory block 67 may be configured to operate as special combinational operators such as a comparator, an adder or a multiplier.
  • the flip-flops in the flip-flop block 68 may operate as flip-flops or may be configured to operate as latches.
  • other programming options dealing with synchronous and asynchronous Set and Reset, Clock Enable, etc. could be provided in association with operation as flip-flops or as latches.
  • the combinational output logic block 69 typically contains a multiplexer in order to connect different wire segments to the output of the PLB 66. Usually this cell has no feed back loops and the flip-flop block 68 can be directly accessed by bypassing the memory block 67 as (shown in dashed lines in Figure 6).
  • the inputs and outputs of every module or block in this type of simple structure are easy to control and observe, thus facilitating nearly independent testing of the blocks.
  • the preferred testing architecture typically includes a second group of PLBs within the self-testing area 16.
  • the wire segments of the WUTs 24, 26 are connected to the inputs 28, 30 and outputs 29, 31 respectively of the PLBs 36, 37 of the second group of PLBs.
  • the second group of PLBs are configured as identity functions in order to pass the test patterns from input to output.
  • this allows for testing of the local as well as the global routing resources.
  • comparison-based ORAs do not suffer from the aliasing problems that occur when some faulty circuits or routing resources produce a good circuit signature. Essentially, as long as the WUTs being compared by the same ORA do not fail in the same way at the same time, no aliasing is encountered with the present comparison-based approach. Of course, such an occurrence is highly unlikely.
  • test patterns propagated along the first group of WUTs are first compared to the test patterns propagated along the second group of WUTs, and subsequently to the test patterns propagated along a third, neighboring group of WUTs.
  • this secondary check substantially eliminates the potential problem of equivalent faults within two groups of WUTs.
  • comparisons of the output patterns of the groups of WUTs 24, 26 may be made at several locations along the groups of WUTs utilizing more than one ORA 22.
  • one set of TPG 20 generated test patterns may be used to test several differing groups of WUTs per configuration.
  • an iterative comparator can be used.
  • such an iterative comparator 72 may be based upon one proposed by Sridhar and Hayes in "Design of Easily Testable BIT-Sliced Systems", IEEE Trans. on Computers, Vol. C-30, No. 11, pp. 842-54, November, 1981 as shown in the dashed lines in Figure 8.
  • each ORA 73, 74 compares the corresponding test patterns propagated along the WUTs (e.g., WUT i , WUT j and WUT k , WUT l in Figure 8) to produce test result data or a local mismatch signal (LMM).
  • the iterative comparator 72 ORs the test result indication or previous mismatch signal (PMM) from the first ORA 73 to generate an ORA mismatch signal (MM).
  • the flip-flop 75 is used to record the first mismatch encountered during the test sequence.
  • the feedback from the flip-flop output to the first ORA 73 disables further comparisons after the first error is detected. Except for this feedback signal, all the other ORA signals propagate like in an iterative logic array, using only local routing resources.
  • the various ORA outputs can be routed directly to the boundary-scan ports to retrieve the results as indicated above. This provides more information regarding the location of the fault in the FPGA as opposed to a single pass/fail test indication for the entire test resulting from the use of an iterative comparator.
  • Figure 3 illustrates a simplified view of the routing busses associated with a single PLB designated numeral 76 in an ORCA 2C series FPGA.
  • Horizontal and vertical busses are denoted by h and v, respectively.
  • the suffixes x1, x4, xH, and xL indicate wire segments that extend across I PLB, 4 PLBs, half the PLB array, and the full length of the PLB array, respectively, before encountering a break-point CIP or a boundary-scan point of the FPGA (not shown).
  • Direct busses provide connections between adjacent PLBs.
  • the four direct busses are designated dn, ds, de, and dw denoting direct north, south, east, and west, respectively.
  • vx1w For every PLB there are two sets of vertical x1 busses and two sets of horizontal x1 busses, designated vx1w, vx1e, hx1n, and hx1s.
  • Several CIPs are available to establish different connections among the wire segments as shown by circle and diamond-shaped symbols.
  • the diamond-shaped symbol 77 of a break-point CIP on a 4-bit bus represents a group of 4 individual break-point CIPs.
  • a circle-shaped symbol 78 denoting a cross-point CIP at the intersection of a vertical 4-bit bus with an horizontal 4-bit bus represents a group of 4 individual cross-point CIPs between corresponding wires in the two busses.
  • the square-shaped symbol 79 at the intersection of a 5-bit direct bus with a 4-bit x1 bus represents a more flexible matrix of cross-point CIPs shown in Figure 9B.
  • the preferred fault model utilized to test the resources of the programmable interconnect network of a typical FPGA includes CIPs stuck-closed (stuck-on) and stuck-open (stuck-off), wire segments stuck at 0 or 1, open wire segments, and shorted wire segments. Detecting the CIP faults also detects stuck-at faults in the configuration memory bits that control the CIPs as shown generally in Figure 5A. For generality, both wired-AND and wired-OR faults are considered as possible behavior for shorted wire segments. A stuck-closed CIP creates a short between its two wires.
  • a bunch of wire segments are wire segments that may have pair-wise shorts; but not every wire segment is necessarily adjacent to every other wire segment in the bunch. For example, all the vertical wire segments located between two adjacent PLB columns may be treated as a bunch even if not all shorts are physically feasible.
  • this makes the preferred testing method layout-independent and allows the bus rotations, which make the adjacency relations among wire segments of the same bunch change, to be ignored during testing.
  • the applied test patterns must verify that every wire segment and CIP is able to transmit both a 0 and a 1, and that every pair of wire segments that can be shorted can transmit both a (0,1) and a (1,0).
  • Wire segments which can be shorted include vertical and horizontal segments separated by a cross-point CIP to account for the CIP being stuck-on. Applying walking patterns, i.e., walking a 1 through a field of 0s and a 0 through a field of 1s, to the two groups of WUTs is sufficient to create all required test patterns.
  • An exhaustive set of test patterns produced by a counter will contain the set of walking test patterns as a subset. Either set detects all shorts between the WUTs.
  • a counter is utilized to generate exhaustive n-bit test patterns since the counter requires less PLBs than a generator for both n-bit walking patterns, provided that n is not too large.
  • the n WUTs may be divided into groups ofk ⁇ n wire segments to which exhaustive test patterns are applied one group at a time while the other n-k wire segments are set to constant values. Eventually all required pairs of values are applied.
  • An example illustrating the preferred method of testing is set out in detail in the above-referenced pending EP-A-1 063 529.
  • the initial self-testing area 16 of the FPGA under test 10 may be divided into a vertical self-testing area 80 and an horizontal self-testing area 81.
  • the vertical self-testing area 80 is primarily utilized to test vertical routing resources or wire segments
  • the horizontal self-testing area 81 is primarily utilized to test horizontal routing resources or wire segments.
  • spare programmable logic blocks in both self-testing areas, horizontal wire segments in the horizontal self-testing area 80, and vertical wire segments in the vertical self-testing area 81 are all designated reserved or unusable.
  • connections between divided working area PLBs are made utilizing horizontal wire segments through the vertical self-testing area 80 and vertical wire segments through the horizontal self-testing area 81.
  • the utilization of these wire segments to carry system signals through the vertical or horizontal self-testing areas 80 and 81 between divided working area PLBs limits the ability of the self-testing areas to test cross-point CIPs.
  • the preferred method of testing cross-point CIPs 82 included in groups of WUTs 84, 86 utilizes both the vertical self-testing area 80 and the horizontal self-testing area 81.
  • PLBs within the horizontal self-testing area 81 are configured to include TPG 88 and PLBs within the vertical self-testing area 80 are configured to include ORA 90.
  • TPG 88 The necessary test signals generated by TPG 88 are propagated along horizontal wire segments 92, 93 in the horizontal self-testing area 81, through the cross-point CIPs 82, and along vertical wire segments 94, 95 in the vertical self-testing area 80 for comparison by ORA 90.
  • the FPGA under test 10 Upon the completion of testing the programmable routing resources located within the initial self-testing area 16, the FPGA under test 10 is reconfigured such that the functions of the PLBs forming a portion of the working area 18 are copied to the PLBs forming the initial self-testing area 16. Once completed, the copied portion of the working area becomes a subsequent self-testing area.
  • the initial self-testing area 16 is reconfigured as an adjacent portion of the working area 18, i.e., the programmed function of an adjacent portion of the working area 18 is relocated or more specifically, copied to the initial self-testing area 16, and the adjacent portion of the working area is reconfigured as the subsequent self-testing area.
  • the subsequent self-testing area may similarly be divided into vertical and horizontal self-testing areas 81 and 82 (as shown in Figure 10) if desired. Further, the step of testing the programmable routing resources within the subsequent testing area is then repeated. This continues until each portion of the working area 18, or the entire FPGA under test 10, is reconfigured as a subsequent self-testing area and its programmable routing resources tested. In other words, the self-testing area roves around the FPGA under test 10 repeating the steps of testing and reconfiguring the programmable routing network until the entire FPGA has undergone testing.
  • normal operation of the FPGA under test 10 continues uninterrupted by the testing conducted within the self-testing areas.
  • the method of testing field programmable gate arrays is carried out during normal on-line operation of the FPGA by configuring the FPGA resources into a working area and an initial self-testing area.
  • the working area maintains normal operation of the FPGA under test throughout testing. Within the initial and subsequent self-testing areas, however, all the programmable routing resources are exhaustively tested.
  • the working area is substantially unaffected by the testing and testing time constraints are reduced since normal operation continues in the working area.

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Claims (22)

  1. Procédé pour tester des ressources d'acheminement programmables d'un tableau de portes programmable sur le champ (10) pendant une opération en ligne normale comprenant les étapes consistant à :
    configurer ledit tableau de portes programmable sur le champ (10) en une zone de test automatique initiale (16) et en une zone de travail (18), ladite zone de travail (18) maintenant un fonctionnement normal du tableau de portes programmable sur le champ (10) ;
    tester lesdites ressources d'acheminement programmables placées à l'intérieur de ladite zone de test automatique initiale (16) ; et
    parcourir ladite zone de test automatique initiale (16) en reconfigurant ledit tableau de portes programmable sur le champ (10) de telle sorte qu'une partie de ladite zone de travail (18) devienne une zone de test automatique ultérieure et qu'au moins une partie de ladite zone de test automatique initiale (16) devienne une partie de ladite zone de travail (18).
  2. Procédé selon la revendication 1, dans lequel les étapes consistant à tester et à parcourir sont répétées jusqu'à ce que chaque partie de ladite zone de travail (18) soit reconfigurée en une zone de test automatique consécutive et testée.
  3. Procédé selon la revendication 1 ou la revendication 2, dans lequel l'étape consistant à configurer ledit tableau de portes programmable sur le champ (10) en une zone de test automatique initiale (16) et en une zone de travail (18) comprend de plus une configuration d'un premier groupe de blocs logiques programmables à l'intérieur de ladite zone de test automatique initiale (16) pour fonctionner comme un générateur de modèle de test (20) et un analyseur de réponse de sortie (22), et une partie desdites ressources d'acheminement programmables à l'intérieur de ladite zone de test automatique initiale (16) sous forme d'au moins deux groupes de circuits sous test (24, 26).
  4. Procédé selon la revendication 3, dans lequel l'étape consistant à tester lesdites ressources d'acheminement programmables placées à l'intérieur de ladite zone de test automatique initiale (16) consiste à :
    propager des modèles de test générés par ledit générateur de modèles de test (20) le long desdits deux groupes au moins de circuits sous test (24, 26) ;
    comparer les sorties desdits deux groupes au moins de circuits sous test (24, 26) en utilisant ledit analyseur de réponse de sortie (22) ; et
    produire des données d'état de défaut pour lesdits au moins deux groupes de circuits sous test (24, 26).
  5. Procédé selon la revendication 4 comprenant, de plus, l'étape consistant à reconfigurer de façon répétée lesdites ressources d'acheminement programmables de façon que chaque partie desdites ressources d'acheminement programmables à l'intérieur de ladite zone de test automatique initiale (16) soit configurée sous forme desdits deux groupes au moins de circuits sous test (24, 26) au moins une fois en cours de test.
  6. Procédé selon l'une quelconque des revendications 3 à 5 dans lequel l'étape consistant à configurer une partie desdites ressources d'acheminement programmables à l'intérieur de ladite zone de test automatique initiale (16) consiste, de plus, à utiliser un groupe de segments de circuit et un groupe de points d'interconnexion de configuration desdites ressources d'acheminement programmables pour former lesdits deux groupes au moins de circuits sous test (24, 26).
  7. Procédé selon la revendication 6 dans lequel l'étape consistant à configurer ledit tableau de portes programmable sur le champ (10) en une zone de test automatique initiale (16) et en une zone de travail (18) consiste, de plus, à configurer un second groupe de blocs logiques programmables à l'intérieur de ladite zone de test automatique initiale (16) pour faire passer des modèles de test à travers elle, ledit second groupe de blocs logiques programmables formant une partie desdits deux groupes au moins de circuits sous test (24, 26), de façon à ce que des ressources d'acheminement locales desdites ressources d'acheminement programmables soient testées.
  8. Procédé selon la revendication 7 dans lequel l'étape consistant à tester lesdites ressources d'acheminement programmables placées à l'intérieur de ladite zone de test automatique initiale (16) comprend :
    l'application d'un modèle de test généré par ledit générateur de modèles de test (20) aux dits deux groupes au moins de circuits sous-test (24, 26) ;
    la comparaison des sorties desdits deux groupes au moins de circuits sous test (24, 26) en utilisant ledit analyseur de réponse de sortie (22) ; et
    la production des données d'état de défaut pour lesdits deux groupes au moins de circuits sous test (24, 26).
  9. Procédé selon la revendication 8 comprenant, de plus, l'étape consistant à reconfigurer de façon répétée lesdites ressources d'acheminement programmables à l'intérieur de ladite zone de test automatique initiale (16) de façon que chaque segment de circuit et point d'interconnexion de configuration devienne l'un desdits deux groupes au moins de circuits sous test (24, 26), une fois au moins en cours de test.
  10. Procédé selon la revendication 1 ou la revendication 2, comprenant, de plus, l'étape consistant à configurer ladite zone de test automatique initiale (16) pour inclure une zone de test automatique initiale horizontale (81) principalement pour tester des segments de circuit horizontaux et une zone de test automatique verticale (80) principalement pour tester des segments de circuit verticaux.
  11. Procédé selon la revendication 10 dans lequel l'étape consistant à parcourir ladite zone de test automatique initiale (16) inclut de reconfigurer ledit tableau de portes programmable sur le champ (10) de telle sorte qu'une partie de ladite zone de travail (18) devienne une zone ultérieure de test automatique horizontale ou verticale et ladite zone de test automatique initiale horizontale ou verticale (80, 81) devienne une partie de ladite zone de travail (18).
  12. Procédé selon la revendication 1, le procédé de test d'un tableau de portes programmable sur le champ (10) incluant des ressources d'acheminement programmables et des blocs logiques programmables, dans lequel :
    l'étape de test comprend l'application des modèles de test générés par lesdits blocs logiques programmables aux dites ressources d'acheminement programmables configurées en groupes de circuits (24, 26) sous test à l'intérieur de ladite zone de test automatique initiale (16) ;
    le procédé utilisant lesdits blocs logiques programmables pour comparer des sorties desdits groupes de circuits sous test (24, 26) à l'intérieur de ladite zone de test automatique initiale (16).
  13. Procédé selon la revendication 12 dans lequel les étapes consistant à appliquer des modèles de test, à utiliser des blocs logiques pour comparer des sorties et à reconfigurer sont répétées en continu.
  14. Procédé selon la revendication 12 ou la revendication 13 comprenant, de plus, l'étape consistant à reconfigurer de façon répétée lesdits ressources d'acheminement programmables de façon que chaque segment de circuit et chaque point d'interconnexion de configuration à l'intérieur de ladite zone de test automatique initiale (16) soient utilisés dans l'un desdits groupes de circuits sous test (24, 26), une fois au moins au cours du test.
  15. Procédé selon la revendication 12 dans lequel :
    l'étape de configuration comprend la configuration dudit tableau de portes programmable sur le champ (10) en une zone de test automatique horizontale initiale (81), en une zone de test automatique verticale initiale (80) et en une zone de travail (18) en conservant un fonctionnement normal dudit tableau de portes programmable sur le champ (10) ;
    l'étape d'application des modèles de test consiste à appliquer des modèles de test générés par lesdits blocs logiques programmables à une partie desdites ressources d'acheminement programmables configurées en groupes de circuits sous test (24, 26) à l'intérieur desdites zones de test automatique initiales (80, 81).
  16. Procédé selon la revendication 15, dans lequel les étapes consistant à appliquer des modèles de test, à utiliser des blocs logiques pour comparer des sorties et à reconfigurer sont répétées jusqu'à ce que chaque partie de ladite zone de travail (18) soit reconfigurée en une zone de test automatique consécutive et testée.
  17. Procédé selon la revendication 16 comprenant, de plus, l'étape consistant à reconfigurer de façon répétée lesdites ressources d'acheminement programmables à l'intérieur desdites zones de test automatique initiales (80, 81) de façon que chaque partie desdites ressources d'acheminement programmables à l'intérieur desdits zones de test automatique initiales (80, 81) soit utilisée dans l'un desdits groupes de circuits sous test (24, 26) au moins une fois pendant le test.
  18. Procédé selon l'une quelconque des revendications 15 à 17 dans lequel l'étape consistant à appliquer des modèles de test à une partie desdites ressources d'acheminement programmables configurées en groupes de circuits sous test (24, 26) comprend, de plus, l'utilisation d'un groupe de segments de circuit et un groupe de points d'interconnexion de configuration desdites ressources d'acheminement programmables pour former lesdits groupes de circuits sous test (24, 26).
  19. Dispositif pour tester des ressources d'acheminement programmables d'un tableau de portes programmable sur le champ (10) pendant un fonctionnement en ligne normal, comprenant :
    un contrôleur (12) en communication avec ledit tableau de portes programmable sur le champ (10) pour (a) configurer ledit tableau de portes programmable sur le champ (10) en une zone de test automatique initiale (16) et en une zone de travail (18), ladite zone de travail (18) conservant un fonctionnement normal du tableau de portes programmables par le champ (10), (b) tester lesdites ressources d'acheminement programmables placées à l'intérieur de ladite zone de test automatique initiale (16) et (c) parcourir ladite zone de test automatique initiale (16) en reconfigurant ledit tableau de portes programmable sur le champ (10) de telle façon qu'une partie de ladite zone de travail (18) devienne une zone de test automatique ultérieure et qu'au moins une partie de ladite zone de test automatique initiale (16) devienne une partie de ladite zone de travail (18) ; et
    un support de stockage (14) en communication avec ledit contrôleur (12) pour stocker une pluralité de configurations de test et de données d'état de défaut.
  20. Tableau de portes programmable sur le champ (10) comprenant :
    une pluralité de blocs logiques programmables ;
    une pluralité de ressources d'acheminement programmables interconnectant lesdits blocs logiques programmables ;
    une pluralité d'éléments d'entrée/sortie, le tableau de portes programmables sur le champ étant caractérisé en ce que
    lesdits blocs logiques programmables et lesdites ressources d'acheminement programmables sont configurés initialement en une zone de test automatique initiale (16) pour tester une partie des ressources d'acheminement programmables à l'intérieur de ladite zone de test automatique initiale (16), et en une zone de travail initiale (18) pour maintenir un fonctionnement en ligne normal du tableau de portes programmable sur le champ (10) pendant le test ; et en ce que
    lesdits blocs logiques programmables et lesdites ressources d'acheminement programmables sont configurés ultérieurement en une zone de test automatique ultérieure pour tester une partie différente des ressources d'acheminement programmables à l'intérieur de ladite zone de test automatique ultérieure, et en une zone de travail ultérieure (18) pour maintenir un fonctionnement en ligne normal du tableau de portes programmable sur le champ (10) pendant une opération de test ultérieure.
  21. Tableau de portes programmable sur le champ selon la revendication 20 dans lequel une partie desdits blocs logiques programmables à l'intérieur de ladite zone de test automatique initiale (16) sont configurés pour fonctionner comme un générateur de modèles de test (20) et un analyseur de réponse de sortie (22), et une partie desdites ressources d'acheminement programmables à l'intérieur de ladite zone de test automatique initiale (16) est configurée sous forme de deux groupes au moins de circuits sous test (24, 26).
  22. Tableau de portes programmable sur le champ (21) selon la revendication 21 dans lequel ledit générateur de modèles de test (20) génère un ensemble de modèles de test pour tester lesdits deux groupes au moins de circuits sous test (24, 26) ; et
       dans lequel ledit analyseur de réponse de sortie (22) compare les sorties desdits deux groupes aux moins de circuits sous test (24, 26) et produit des données d'état de défaut correspondant aux dits deux groupes au moins de circuits sous test (24, 26).
EP00308136A 1999-09-27 2000-09-18 Essai en ligne du réseau d'interconnexion programmable d'un réseau de portes programmables Expired - Lifetime EP1089084B1 (fr)

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US09/406,219 US6574761B1 (en) 1999-09-27 1999-09-27 On-line testing of the programmable interconnect network in field programmable gate arrays
US406219 1999-09-27

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US6574761B1 (en) 2003-06-03
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DE60010614D1 (de) 2004-06-17
DE60010614T2 (de) 2005-05-19

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