EP1082816A1 - Method and system for operating a multi-stage counter in one counting direction - Google Patents

Method and system for operating a multi-stage counter in one counting direction

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Publication number
EP1082816A1
EP1082816A1 EP99936340A EP99936340A EP1082816A1 EP 1082816 A1 EP1082816 A1 EP 1082816A1 EP 99936340 A EP99936340 A EP 99936340A EP 99936340 A EP99936340 A EP 99936340A EP 1082816 A1 EP1082816 A1 EP 1082816A1
Authority
EP
European Patent Office
Prior art keywords
counter
stage
count
multistage
counting direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP99936340A
Other languages
German (de)
French (fr)
Other versions
EP1082816B1 (en
Inventor
Robert Allinger
Robert Hollfelder
Wolfgang Pockrandt
Armin Wedel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
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Publication of EP1082816A1 publication Critical patent/EP1082816A1/en
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Publication of EP1082816B1 publication Critical patent/EP1082816B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/0806—Details of the card
    • G07F7/0813—Specific details related to card security
    • G07F7/082—Features insuring the integrity of the data on or in the card
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation

Definitions

  • the invention relates to a method and an arrangement for operating a multistage counter in a counting direction.
  • any number of application areas are known in which an event count is to take place.
  • These events can include the frequency of use of a device, the passing of people or vehicles or objects, the recording of a telephone counting cycle, but also the recording of mileage, i.e. odometer in a car or operating hours counter of any device and last but not least the recorded working time or attendance time of an employee at his workplace.
  • All of these cases are characterized in that they are recorded with the highest possible accuracy, i. H. that usually a large range of values is covered by counted values.
  • Such a requirement can surely be realized with a single-stage counter that can only count up or down from its previous counter reading.
  • This can be easily achieved, for example, by means of an EEPROM, in which case an EEPROM cell must be provided for each count value, and that EEPROM is either only writable or only erasable, depending on whether an up or down count is provided.
  • Binary counter has the disadvantage, however, that if the next counter position changes, the previous counter position is reset. This means that it is very difficult to implement a multi-stage counter that only counts in one direction and cannot be manipulated at the same time.
  • EP 0 321 727 A circuit arrangement is described in EP 0 321 727, in which several EEPROM cells are arranged in a row. Again, several rows are interconnected. The memory cells in each row represent a uniform value level, the memory contents of a row being able to be erased by means of logical monitoring only if a transfer to the next higher row has taken place.
  • the arrangement disclosed in this publication has precisely the disadvantages of manipulability explained above, since unidirectional counting is not guaranteed with certainty by influencing the logic circuit.
  • EP 0 618 591 an auxiliary memory cell being provided for each next higher row for rewriting, which is programmable and also erasable again, this arrangement also being easy to manipulate, since the auxiliary memory cells both write - and can also be deleted.
  • the invention is therefore based on the object of providing a method and a circuit arrangement for operating a multistage counter in which the security against manipulation is increased. This object is achieved with the in claim
  • the indication signal according to claim 2 indicates the lack of permissibility, it being checked whether the count value of the single-stage counter is in a predetermined ratio with the count value of the multistage counter. According to claim 3, the admissibility is given when the count values match.
  • the counter 11 can thus count from 0 to 255, i. H. 256 counting points.
  • the counter 11 can thus count from 0 to 255, i. H. 256 counting points.
  • a control unit 3 which supplies the counter 11 with a count signal S11.
  • the counter 11 is changed by 1, the change taking place in the same direction as a previous change.
  • the respective counter reading of the multi-stage counter 11 is supplied to a test logic 4 as a count value signal ZU.
  • the single-stage counter 1 receives a count signal S1 from the control unit 3, whereupon it is advanced by a count value.
  • the count of the single-stage counter 1 is supplied to the control unit 3 as a control count signal ZI and thus to the test logic 4.
  • the test logic 4 compares the count value signal ZU with the control count value signal ZI and outputs a signal determined as a function of the comparison to a counter controller 5.
  • the counter controller 5 in turn emits an error signal E as a function of the test signal P received from the test logic 4.
  • the two counters 11 and 1 can be designed, for example, as EEPROM cells. It is provided that, in accordance with the known operation of a binary counter, the individual memory cells are written to or erased in accordance with the rules of counting up or down. In the same way, the one-step control counter 1 is composed of EEPROM cells, the individual cells 1 to n being consecutive, can only be written to or can only be deleted.
  • the test logic 4 checks the counts of the two counters 1 and 11 beforehand by means of the count value signal ZU and the check count signal ZI. If both are 0, for example, the test logic 4 determines that the match exists and, via the test signal P, allows the counter signal 5 to output the count signal SF.
  • both counters count from 0 to 255.
  • the test logic is now designed so that it monitors that the numerical value of the payer 11 matches the numerical value of the control payer 1 that has just been reached. That is, In the exemplary embodiment shown, the numerical value of the payer 11 must not be less than (I x 16) - 1. The same applies to an arrangement paying downwards.
  • the payer 11 must be in a range that matches the numerical value of the control payer 1.
  • the invention is not limited to the exemplary embodiment shown in the figure. Rather, it is also conceivable that, particularly in the case of a very large count range of the counter 11 to be exceeded in order to save counter cells of the single-stage counter, the counter is not operated linearly, but rather, for example, in a decade. I.e. the one-stage payer received a payment signal S11 from the payer controller 5, a control number signal S1, for example on the 10th, 100th, 1000th etc. To monitor the unmanipulated operation, the test logic 4 must be constructed accordingly, i. H. in such a case, the numerical value of the payer 11 must correspond to the order of magnitude assigned to the respective count value of the control counter 1. It is equally conceivable that the relationship between the counter of the counter 11 and the count of the control counter 1 corresponds to a logarithmic, exponential or any other suitable and desired functions. This can then be applied to both up-and-down counter arrangements.
  • the payer 11 and the control payer 1 do not necessarily have to pay in the same direction. Rather, it can also be provided that one counter counts up and the other counter counts down.
  • the only requirement for unmanipulated operation is that the control counter counts only in one direction and the test logic 4 is constructed in such a way that the count value of the counter 11 has a logical relationship with the count value of the control counter 1.

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Business, Economics & Management (AREA)
  • Computer Security & Cryptography (AREA)
  • General Business, Economics & Management (AREA)
  • Accounting & Taxation (AREA)
  • Strategic Management (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Time Recorders, Dirve Recorders, Access Control (AREA)
  • Measurement Of Radiation (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Complex Calculations (AREA)
  • Lock And Its Accessories (AREA)
  • Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Display Devices Of Pinball Game Machines (AREA)

Abstract

A method of operating a multistage counter in only one counting direction includes the step of changing a counter reading of a single-stage auxiliary counter at given counter readings of the multistage counter. The single-stage auxiliary counter and the multistage counter can only be changed in one counting direction. Respective counter readings of the multistage counter and of the single-stage auxiliary counter are registered. Values of the respective counter readings of the single-stage auxiliary counter and of the multistage counter are compared with one another, and an indicator signal is generated based on a comparison result determined in the comparing step.

Description

Beschreibungdescription
Verfahren und Anordnung zum Betreiben eines mehrstufigen Zählers in einer ZählrichtungMethod and arrangement for operating a multistage counter in one counting direction
Die Erfindung betrifft ein Verfahren und eine Anordnung zum Betreiben eines mehrstufigen Zählers in einer Zählrichtung.The invention relates to a method and an arrangement for operating a multistage counter in a counting direction.
Heutzutage sind beliebig viele Anwendungsgebiete bekannt, bei denen eine Ereigniszählung stattfinden soll. Diese Ereignisse kann die Häufigkeit der Benutzung eines Gerätes, das Passieren von Personen oder Fahrzeugen oder Gegenständen, die Erfassung eines Telefonzähltaktes, aber auch die Erfassung einer Fahrleistung, sprich Kilometerzähler bei einem PKW oder Betriebsstundenzähler eines beliebigen Gerätes und nicht zuletzt die erfaßte Arbeitszeit bzw. Anwesentheitszeit eines Arbeitnehmers an seinem Arbeitsplatz sein. All diese Fälle sind dadurch gekennzeichnet, daß sie mit möglichst hoher Genauigkeit erfaßt werden, d. h. das in der Regel ein hoher Wertebereich von Zählwerten abgedeckt wird. Weiterhin ist bei den genannten Fällen in der Regel der Wunsch vorhanden, daß das Zählergebnis nicht manipulierbar, d. h. nicht rücksetzbar ist. Eine derartige Forderung läßt sich sicher mit einem einstufigen Zähler realisieren, der nur von seinem bisherigen Zählerstand aus aufwärts oder abwärts zählen kann. Dies läßt sich einfach beispielsweise mittels eines EEPROM realisieren, wobei dann für jeden Zählwert eine EEPROM-Zelle vorzusehen ist, und daß EEPROM entweder nur beschreibbar oder nur löschbar ist, je nachdem ob eine Aufwärts- oder AbwärtsZählung vorgesehen ist.Nowadays, any number of application areas are known in which an event count is to take place. These events can include the frequency of use of a device, the passing of people or vehicles or objects, the recording of a telephone counting cycle, but also the recording of mileage, i.e. odometer in a car or operating hours counter of any device and last but not least the recorded working time or attendance time of an employee at his workplace. All of these cases are characterized in that they are recorded with the highest possible accuracy, i. H. that usually a large range of values is covered by counted values. Furthermore, in the cases mentioned, there is usually a wish that the counting result cannot be manipulated, i. H. cannot be reset. Such a requirement can surely be realized with a single-stage counter that can only count up or down from its previous counter reading. This can be easily achieved, for example, by means of an EEPROM, in which case an EEPROM cell must be provided for each count value, and that EEPROM is either only writable or only erasable, depending on whether an up or down count is provided.
Für die zuerst genannte Forderung, daß nämlich ein möglichst großer Wertebereich vom Zähler zu erfassen ist, führt dann zu dem Ergebnis, daß bei einer solchen Realisierung ein EEPROM- Speicher mit entsprechend vielen Speicherzellen vorzusehen ist. In Zahlen ausgedrückt heißt dies, daß zum Beispiel zum Erreichen eines maximalen Zählerstandes von 255 genau 255 Zählerzellen benötigt werden. Nunmehr ist es jedoch heutzutage üblich, derartige Anordnungen möglichst klein aufzubauen. Die Verwendung eines mehrstufigen Zählers mit 8 Bit, d. h. 8 Zählerzellen führt ebenfalls zu einem maximalen Zählerstand von 255. Ein derartiger mehrstufiger Zähler (8-Bit-For the first-mentioned requirement that the greatest possible range of values is to be recorded by the counter, the result is that an EEPROM memory with a corresponding number of memory cells must be provided in such an implementation. Expressed in numbers, this means that, for example, exactly 255 is required to reach a maximum counter reading of 255 Counter cells are required. Nowadays, however, it is customary to construct such arrangements as small as possible. The use of a multi-level counter with 8 bits, ie 8 counter cells, also leads to a maximum counter reading of 255. Such a multi-level counter (8-bit
Binärzähler) weist jedoch den Nachteil auf, daß bei einer Veränderung der nächsten Zählerstelle die vorangegangene Zählerstelle zurückgesetzt wird. Dies führt dazu, daß die Realisierung eines mehrstufigen Zählers, der nur in einer Richtung zählt und gleichzeitig nicht manipulierbar ist, nur sehr schwer realisierbar ist.Binary counter) has the disadvantage, however, that if the next counter position changes, the previous counter position is reset. This means that it is very difficult to implement a multi-stage counter that only counts in one direction and cannot be manipulated at the same time.
Aus der EP 0 321 727 ist eine Schaltungsanordnung beschrieben, bei der mehrere EEPROM-Zellen in einer Reihe angeordnet sind. Dabei sind wiederum mehrere Reihen zusammengeschaltet sind. Die Speicherzellen jeweils einer Reihe stellen ein einheitliches Wertigkeitsniveau dar, wobei die Speicherinhalte einer Reihe, mittels einer logischen Überwachung nur dann löschbar sind, wenn ein Übertrag in die nächst höhere Reihe erfolgt ist. Die in dieser Druckschrift offenbarte Anordnung weist genau die zuvor erläuterten Nachteile der Manipulier- barkeit auf, indem durch Einflußnahme auf die logische Schaltung das unidirektionale Zählen nicht mit Sicherheit gewährleistet ist. Eine ähnliche nur etwas aufwendiger gestaltete Anordnung ist in der EP 0 618 591 ausgeführt, wobei für jede nächst höhere Reihe zum Umschreiben eine Hilfsspeicherzelle vorgesehen ist, die programmierbar und auch wieder löschbar ist, wobei auch diese Anordnung leicht manipulierbar ist, da die Hilfsspeicherzellen sowohl schreib- als auch löschbar sind.A circuit arrangement is described in EP 0 321 727, in which several EEPROM cells are arranged in a row. Again, several rows are interconnected. The memory cells in each row represent a uniform value level, the memory contents of a row being able to be erased by means of logical monitoring only if a transfer to the next higher row has taken place. The arrangement disclosed in this publication has precisely the disadvantages of manipulability explained above, since unidirectional counting is not guaranteed with certainty by influencing the logic circuit. A similar, somewhat more complex arrangement is described in EP 0 618 591, an auxiliary memory cell being provided for each next higher row for rewriting, which is programmable and also erasable again, this arrangement also being easy to manipulate, since the auxiliary memory cells both write - and can also be deleted.
Der Erfindung liegt somit die Aufgabe zugrunde, ein Verfahren bzw. eine Schaltungsanordnung zum Betreiben eines mehrstufigen Zählers vorzusehen, bei dem die Manipulationssicherheit erhöht ist. Diese Aufgabe wird erfindungsgemäß mit den in PatentanspruchThe invention is therefore based on the object of providing a method and a circuit arrangement for operating a multistage counter in which the security against manipulation is increased. This object is achieved with the in claim
I bzw. 4 angegebenen Maßnahmen gelöst.I or 4 specified measures solved.
Durch das gleichzeitige Betreiben eines einstufigen Zählers, der nur entweder aufwärts oder abwärts zählt neben dem mehrstufigen Zähler, der das eigentliche Ereignis zählt, ist über ein Vergleich sichergestellt, daß der Zählwert des mehrstufigen Zählers zumindest in der Größenordnung, mit dem Zählwert des einstufigen Zählers übereinstimmt. Damit ist mit einfa- chen Mitteln die Möglichkeit zur Manipulation beseitigt. Ist die Übereinstimmung mit einem vorgegebenen Verhältnis zwischen den beiden Zählern nicht gegeben, so zeigt das Indikationssignal gemäß Anspruch 2 die fehlende Zulässigkeit an, wobei überprüft wird, ob der Zählwert des einstufigen Zählers mit dem Zählwert des mehrstufigen Zählers in einem vorbestimmten Verhältnis steht. Gemäß Patentanspruch 3 ist die Zulässigkeit bei Übereinstimmung der Zählwerte gegeben.By simultaneously operating a single-stage counter that only counts either upwards or downwards next to the multi-stage counter that counts the actual event, a comparison ensures that the count value of the multi-stage counter agrees at least in the order of magnitude with the count value of the single-stage counter . The possibility of manipulation is thus eliminated with simple means. If there is no correspondence with a predefined ratio between the two counters, the indication signal according to claim 2 indicates the lack of permissibility, it being checked whether the count value of the single-stage counter is in a predetermined ratio with the count value of the multistage counter. According to claim 3, the admissibility is given when the count values match.
Nachfolgend wird die Erfindung unter Bezugnahme auf die Figur beschrieben, wobei ein Ausführungsbeispiel in Form eines Blockschaltbildes dargestellt ist.The invention is described below with reference to the figure, an exemplary embodiment being shown in the form of a block diagram.
Das in der Figur dargestellte Ausführungsbeispiel weist einen -stufigen Zähler mit m = 8 auf. Dieser ist in der Darstel- lung als 8-Bit-Binärzähler zu verstehen. Der Zähler 11 kann somit von 0 bis 255 zählen, d. h. 256 Zählstellen. Der ZählerThe embodiment shown in the figure has a -step counter with m = 8. In the illustration, this is to be understood as an 8-bit binary counter. The counter 11 can thus count from 0 to 255, i. H. 256 counting points. The counter
II ist mit einer Steuereinheit 3 verbunden, die dem Zähler 11 ein Zählsignal Sll zuführt. Mit jedem Zuführen des Zählsignals Sll wird der Zähler 11 um 1 verändert, wobei die Verän- derung in gleicher Richtung wie eine vorangegangene Änderung erfolgt. Das bedeutet, daß der in der Figur symbolisch dargestellte Zähler derart gestaltet ist, daß er entweder aufwärts oder nur abwärts zählt. Der jeweilige Zählerstand des mehrstufigen Zählers 11 wird als Zählwertsignal ZU einer Prüflo- gik 4 zugeführt. Weiterhin ist ein einstufiger Zähler 1 vorgesehen, der bei diesem Ausführungsbeispiel n-Zellen mit n = 16 aufweist. Dieser in der Figur symbolisch dargestellte Zäh- ler soll so aufgebaut sein, daß er ebenfalls nur in einer Zählrichtung zählt, nämlich von 0 bis 15, d. h. 16 Zählstellen. Der einstufige Zähler 1 erhält von der Steuereinheit 3 ein Zählsignal Sl, worauf er um einen Zählwert weitergesetzt wird. Der Zählstand des einstufigen Zählers 1 wird der Steuereinheit 3 als Kontrollzählwertsignal ZI und damit der Prüflogik 4 zugeführt. Die Prüflogik 4 vergleicht das Zählwertsignal ZU mit dem Kontrollzählwertsignal ZI und gibt ein in Abhängigkeit vom Vergleich bestimmtes Signal an eine Zäh- lersteuerung 5 ab. Die Zählersteuerung 5 wiederum gibt in Abhängigkeit von dem von der Prüflogik 4 erhaltenen Prüfsignal P ein Fehlersignal E ab.II is connected to a control unit 3, which supplies the counter 11 with a count signal S11. Each time the count signal S11 is supplied, the counter 11 is changed by 1, the change taking place in the same direction as a previous change. This means that the counter symbolically shown in the figure is designed such that it counts either upwards or only downwards. The respective counter reading of the multi-stage counter 11 is supplied to a test logic 4 as a count value signal ZU. Furthermore, a single-stage counter 1 is provided, which in this exemplary embodiment has n cells with n = 16. This count symbolically represented in the figure ler should be constructed so that it also counts only in one counting direction, namely from 0 to 15, ie 16 counting points. The single-stage counter 1 receives a count signal S1 from the control unit 3, whereupon it is advanced by a count value. The count of the single-stage counter 1 is supplied to the control unit 3 as a control count signal ZI and thus to the test logic 4. The test logic 4 compares the count value signal ZU with the control count value signal ZI and outputs a signal determined as a function of the comparison to a counter controller 5. The counter controller 5 in turn emits an error signal E as a function of the test signal P received from the test logic 4.
Die beiden Zähler 11 und 1 können beispielsweise als EEPROM- Zellen ausgebildet sein. Hierbei ist vorgesehen, daß entsprechend dem bekannten Betreiben eines Binärzählers die einzelnen Speicherzellen gemäß den Regeln des Aufwärts- oder Abwärtszählen beschrieben oder gelöscht werden. Genauso ist auch der einstufige Kontrollzähler 1 aus EEPROM-Zellen zusam- mengesetzt, wobei die einzelnen Zellen 1 bis n nacheinander- folged, nur beschrieben oder nur gelöscht werden können.The two counters 11 and 1 can be designed, for example, as EEPROM cells. It is provided that, in accordance with the known operation of a binary counter, the individual memory cells are written to or erased in accordance with the rules of counting up or down. In the same way, the one-step control counter 1 is composed of EEPROM cells, the individual cells 1 to n being consecutive, can only be written to or can only be deleted.
Nunmehr wird der typische Betrieb der in der Figur dargestellten Anordnung beschrieben. Grundsätzlich ist vorgesehen, daß mit jedem Eingabesignal E von der Steuereinheit 3 ein Zählsignal Sll abgegeben werden soll. Dabei wird zuvor von der Prüflogik 4 die Zählerstände der beiden Zähler 1 und 11 mittels des Zählwertsignals ZU und des Kontrollzählwertsignal ZI überprüft. Sind beide beispielsweise 0, stellt die Prüflogik 4 fest, daß die Übereinstimmung besteht und läßt über das Prüfsignal P zu, daß über die Zählersteuerung 5 das Zählsignal SF ausgegeben wird.The typical operation of the arrangement shown in the figure will now be described. Basically, it is provided that with each input signal E the control unit 3 should emit a count signal S11. In this case, the test logic 4 checks the counts of the two counters 1 and 11 beforehand by means of the count value signal ZU and the check count signal ZI. If both are 0, for example, the test logic 4 determines that the match exists and, via the test signal P, allows the counter signal 5 to output the count signal SF.
Nunmehr ist vorgesehen, daß beide Zähler von 0 bis 255 zäh- len. Das bedeutet, daß der einstufige Kontrollzähler 1 bei jedem sechzehnten Zählsignal Sll, das an den mehrstufigen Zähler 11 geht ebenfalls von der Zählersteuerung 5 in der Steuereinheit 3 ein Kontrollzahlsignal Sl erhalt. Für den un- manipulierten Betrieb ist die Pruflogik nunmehr so ausgelegt, daß sie überwacht, daß der Zahlwert des Zahlers 11 zu dem gerade erreichten Zahlwert des Kontrollzahlers 1 paßt. D. h. bei dem dargestellten Ausfuhrungsbeispiel darf der Zahlwert des Zahlers 11 nicht kleiner sein als (I x 16) - 1 sein. Entsprechendes gilt für eine abwärts zahlende Anordnung, auch hier muß der Zahler 11 entsprechend der Zahllogik sich in einem zum Zahlwert des Kontrollzahlers 1 passenden Bereich be- finden.It is now provided that both counters count from 0 to 255. This means that the single-stage control counter 1 at every sixteenth count signal S11, which goes to the multi-stage counter 11, also from the counter controller 5 in the Control unit 3 receives a control number signal Sl. For the non-manipulated operation, the test logic is now designed so that it monitors that the numerical value of the payer 11 matches the numerical value of the control payer 1 that has just been reached. That is, In the exemplary embodiment shown, the numerical value of the payer 11 must not be less than (I x 16) - 1. The same applies to an arrangement paying downwards. Here too, according to the payment logic, the payer 11 must be in a range that matches the numerical value of the control payer 1.
Sobald die Prüflogik 4 keine Übereinstimmung feststellt, wird ein Fehlersignal F abgegeben.As soon as the test logic 4 does not find a match, an error signal F is emitted.
Die Erfindung ist jedoch nicht auf das in der Figur dargestellte Ausfuhrungsbeispiel beschränkt. Vielmehr ist auch vorstellbar, daß insbesondere bei einem sehr großen zu überschreitenden Zählwertebereich des Zahlers 11 zum Einsparen von Zählerzellen des einstufigen Zählers, dieser nicht linear betrieben wird, sondern beispielsweise dekadisch. D. h. der einstufige Zahler wurde beispielsweise beim 10., 100., 1000. usw. ein Zahlsignal Sll von der Zahlersteuerung 5 ein Kontrollzahlsignal Sl erhalten. Zur Überwachung des unmanipu- lierten Betriebes muß die Pruflogik 4 entsprechend aufgebaut sein, d. h. in einem solchen Fall muß der Zahlwert des Zahlers 11 der dem jeweiligen Zählwert des Kontrollzählers 1 zugeordneten Größenordnung entsprechen. Genauso gut ist vorstellbar, daß der Zusammenhang zwischen dem Zähler des Zahlers 11 und dem Zählwert des Kontrollzahlers 1 einer log- arithmischen, exponentiellen oder beliebig anderen geeigneten und gewünschten Funktionen entspricht. Dies ist dann sowohl auf aufwartszahlende als auch auf abwartszahlende Zähleranordnungen anwendbar.However, the invention is not limited to the exemplary embodiment shown in the figure. Rather, it is also conceivable that, particularly in the case of a very large count range of the counter 11 to be exceeded in order to save counter cells of the single-stage counter, the counter is not operated linearly, but rather, for example, in a decade. I.e. the one-stage payer received a payment signal S11 from the payer controller 5, a control number signal S1, for example on the 10th, 100th, 1000th etc. To monitor the unmanipulated operation, the test logic 4 must be constructed accordingly, i. H. in such a case, the numerical value of the payer 11 must correspond to the order of magnitude assigned to the respective count value of the control counter 1. It is equally conceivable that the relationship between the counter of the counter 11 and the count of the control counter 1 corresponds to a logarithmic, exponential or any other suitable and desired functions. This can then be applied to both up-and-down counter arrangements.
Abschließend sei darauf hingewiesen, daß der Zahler 11 und der Kontrollzahler 1 nicht zwangsläufig in der gleichen Richtung zahlen müssen. Vielmehr kann auch vorgesehen sein, daß der eine Zähler aufwärts und der jeweils andere Zähler abwärts zählt. Die alleinige Voraussetzung für einen unmanipu- lierten Betrieb ist, daß der Kontrollzähler nur in einer Richtung zählt und die Prüflogik 4 derart aufgebaut is-t, daß der Zählwert des Zählers 11 mit dem Zählwert des Kontrollzählers 1 einen logischen Zusammenhang aufweist. In conclusion, it should be pointed out that the payer 11 and the control payer 1 do not necessarily have to pay in the same direction. Rather, it can also be provided that one counter counts up and the other counter counts down. The only requirement for unmanipulated operation is that the control counter counts only in one direction and the test logic 4 is constructed in such a way that the count value of the counter 11 has a logical relationship with the count value of the control counter 1.

Claims

Patentansprüche claims
1. Verfahren zum Betreiben eines mehrstufigen Zählers in nur einer Zählrichtung mit den Schritten: - Verändern des Zählwertes eines einstufigen nur in einer Zahlrichtung veränderbaren Zählers bei vorbestimmten Zahlwertzustanden des mehrstufigen Zählers,1. Method for operating a multistage counter in only one counting direction, with the following steps: changing the count value of a one-level counter that can only be changed in one counting direction when the multistage counter has predetermined numerical value states,
- erfassen der jeweiligen Zahlwertzustande des mehrstufigen Zählers und des einstufigen Hilfszählers, - vergleichen der Werte der erfaßten Zahlwertzustande des einstufigen und des mehrstufigen Zählers, und- Detect the respective numerical value states of the multi-stage counter and the one-stage auxiliary counter, - Compare the values of the acquired numerical value states of the single-stage and multi-stage counter, and
- erzeugen eines Indikatorsignales aufgrund des Vergleichsergebnisses .- generate an indicator signal based on the comparison result.
2. Verfahren nach Anspruch 1, bei dem das Indikatorsignal die Zulässigkeit des Zählwertes des mehrstufigen Zählers anzeigt, wenn dieser in einem vorbestimmten Verhältnis zum Zählwertstand des einstufigen Zählers steht.2. The method according to claim 1, wherein the indicator signal indicates the admissibility of the count value of the multistage counter if this is in a predetermined ratio to the count value of the single-stage counter.
3. Verfahren nach Anspruch 2, bei dem das Indikatorsignal die Zulässigkeit des Zählwertes des mehrstufigen Zählers anzeigt, daß der Zählwert des mehrstufigen Zählers mit dem Zählwert des einstufigen Zählers übereinstimmt.3. The method of claim 2, wherein the indicator signal indicates the admissibility of the count of the multi-level counter that the count of the multi-level counter matches the count of the single-level counter.
4. Schaltungsanordnung zum Durchführen des Verfahrens nach einem der Ansprüche 1 bis 3, mit einem mehrstufigen nur aufwärts oder abwärts zählenden Zäh- lers (11) , bei dem der Zählwert einer Stufe beim Verändern eines Zählwertes der nachfolgenden Stufe auf einen Anfangswert zurückgesetzt wird, einem einstufigen Hilfszähler (1) , der nur aufwärts oder nur abwärts zählend betrieben wird, und der bei vorbestimmten Zählwerten des mehrstufigen Zählers (11) verändert wird, und einer Vergleichseinrichtung (4), die mit dem Zähler (11) und dem Hilfszähler (1) derart verbunden ist, daß sie die Zähl- werte (ZI und ZU) der beiden Zähler jeweils vergleicht und ein dem Vergleich entsprechendes Signal ausgibt. 4. Circuit arrangement for carrying out the method according to one of claims 1 to 3, with a multi-stage counter (11) which only counts up or down, in which the count of one stage is reset to an initial value when a count of the subsequent stage is changed, one single-stage auxiliary counter (1), which is operated only upwards or only downwards, and which is changed at predetermined count values of the multi-stage counter (11), and a comparison device (4), which with the counter (11) and the auxiliary counter (1) is connected in such a way that it values (ZI and ZU) of the two counters are compared and outputs a signal corresponding to the comparison.
EP99936340A 1998-05-28 1999-05-28 Method and system for operating a multi-stage counter in one counting direction Expired - Lifetime EP1082816B1 (en)

Applications Claiming Priority (3)

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DE19823955 1998-05-28
DE19823955A DE19823955A1 (en) 1998-05-28 1998-05-28 Method and arrangement for operating a multistage counter in one counting direction
PCT/DE1999/001570 WO1999062176A1 (en) 1998-05-28 1999-05-28 Method and system for operating a multi-stage counter in one counting direction

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CN1158763C (en) 2004-07-21
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UA44939C2 (en) 2002-03-15
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ES2214875T3 (en) 2004-09-16
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KR20010043902A (en) 2001-05-25
EP1082816B1 (en) 2004-01-02
ATE257294T1 (en) 2004-01-15
RU2235420C2 (en) 2004-08-27
JP2002517117A (en) 2002-06-11
WO1999062176A1 (en) 1999-12-02
US6698652B1 (en) 2004-03-02
DE19823955A1 (en) 1999-12-02

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