EP1060474A2

EP1060474A2 - Memory cell arrangement and method for producing the same

Info

Publication number: EP1060474A2
Application number: EP99916757A
Authority: EP
Inventors: Ulrich Zimmermann; Thomas Böhm; Manfred Hain; Armin Kohlhase; Yoichi Otani; Andreas Rusch; Alexander Trüby
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 1998-02-25
Filing date: 1999-02-25
Publication date: 2000-12-20
Also published as: WO1999044204A3; DE19807920A1; WO1999044204A2; JP2002505516A; KR20010041278A; US6472696B1; KR100604180B1

Abstract

The invention relates to a memory cell arrangement, comprising a number of memory cells (S) arranged in a semiconductor substrate (10) with bit line trenches (1a-1d) running parallel in a longitudinal direction in the main surface of the semiconductor substrate (10). Each bit line trench (1a-1d) is provided with a first conductive area (15a-15d) in the bottom and a second conductive area (20a-20e) of the same conduction type in the top, with a channel area being provided in between in the walls of each trench. Word lines (2a-2c) run in a crosswise direction along the main surface of the semiconductor substrate (10) through certain bit line trenches (1a, 1c, 1d) for controlling the transistors provided there. An additional dopant is introduced into the trench walls of the bit line trenches (1a-1d) situated between the word lines (2a-2c) in order to increase the corresponding transistor cutoff voltage for preventing leakage currents.

Description

description

Memory cell arrangement and corresponding manufacturing method

The present invention relates to a memory cell arrangement with a multiplicity of memory cells provided in a semiconductor substrate with bit line trenches running parallel in the longitudinal direction in the main surface of the semiconductor substrate, in the bottoms of which a first conductive region is provided, in the crowns of which a second conductive region of the same conductivity type as each the first conductive region is provided and in the walls of which an intermediate channel region is provided, and with word lines running in the transverse direction along the main surface of the semiconductor substrate through certain bit line trenches for driving transistors provided there.

Although applicable to memories made of any basic material, the present invention and the problems on which it is based are explained in relation to a memory based on silicon.

Initially, the memory cell arrangements were mostly based on planar concepts. Under the stipulation of a constantly increasing packing density, it was first proposed for MaskROM applications (read-only memory) and later for random access memory (RAM memory) that the cell area of the memory be introduced by introducing parallel ones

Fold longitudinal trenches and thus reduce the projection of the cell surface onto the wafer surface by up to 50%.

DE 195 10 042 discloses a read-only memory cell arrangement in which the memory cells are arranged in rows running in parallel, longitudinal trenches being provided which run essentially parallel to the rows. The Rows are alternately arranged on the main surface between adjacent longitudinal trenches and on the bottom of the longitudinal trenches. Isolation structures are provided for mutual isolation of the memory cells, each of which comprises a MOS transistor. Word lines run across the rows and are each connected to the gates of MOS transistors arranged in different rows. The minimum space requirement per memory cell is theoretically 2 F ² , where F is the minimum structure size of the technology.

From DE 195 14 834 a read-only memory cell arrangement is known which has first memory cells with a vertical MOS transistor and second memory cells without a vertical MOS transistor. The memory cells are arranged along opposite flanks of strip-shaped, parallel insulation trenches. If the width and spacing of the isolation trenches are chosen to be the same size, the minimum space requirement per memory cell is theoretically 2F ² , where F is the minimum structure size of the technology.

The problem underlying the present invention is that in such cell arrangements with line areas that run parallel to the longitudinal trenches alternately on the trench crowns and the trench bottoms, the word lines running at a certain distance from one another perpendicular to it, the silicon on the trench walls between the word lines does not is covered by gate electrodes. If charges are present in the insulation oxides, spacer oxides or other layers that are deposited in the further manufacturing process before, a channel can form there, which leads to unacceptable leakage currents between the conductive areas on the trench crowns and trench bottoms.

An attempt was made to solve this problem by providing a high basic doping of the silicon in the cell field. However, this usually has adverse effects on the vertical components. Furthermore, the charge density in the oxides was minimized, which makes the corresponding processes more expensive and cannot be reliably controlled from a previous point.

The object on which the present invention is based is therefore generally to specify a storage line arrangement which can be produced simply and reliably and a corresponding production method, these leakage currents being able to be significantly reduced without a great deal of process expenditure.

According to the invention, this object is achieved by the memory cell arrangement specified in claim 1 and the production method specified in claim 5.

The memory cell arrangement according to the invention has the advantage over the known memory cell arrangements that the leakage currents on the relevant trench walls can be significantly reduced without the process being significantly more complex. In the manufacturing method according to the invention, the vertical components are essentially protected by the word lines which have already been applied if it is ensured that the direction of implantation lies in a plane which passes essentially perpendicularly through the center of the word lines. In other words, the direction of implantation should be chosen such that there is essentially no dopant under the word lines in the vertical components already manufactured, i.e. Transistors. In addition, sensitive peripheral or planar components should be protected if necessary.

The idea on which the present invention is based is generally that an additional dopant is introduced into the trench walls of the bit line trenches which lie between the word lines in order to increase the corresponding transistor threshold voltage there to suppress leakage currents. In the respective subclaims there are advantageous developments and improvements of the memory cell arrangement specified in claim 1 or of the manufacturing method specified in claim 5.

According to a preferred further development, two implantations are carried out to introduce the additional dopant, which are inclined in opposite directions to the vertical to the main surface of the semiconductor substrate.

According to a further preferred development, the implantation is carried out in a self-adjusting manner with respect to the word lines already present. This has the advantage that masking of the word lines can be dispensed with and the additional outlay is therefore very low.

According to a further preferred development, the implantation takes place in a separate photo plane. This own photo plane should at least protect peripheral and / or planar components on which the additional implantations could have negative effects.

An embodiment of the invention is shown in the drawings and explained in more detail in the following description.

Show it:

1 shows a plan view of a cell array according to an embodiment of the memory cell arrangement according to the invention;

FIG. 2 is a vertical cross-sectional view of the cell array along line AA 'of FIG. 1; and 3 is a vertical cross-sectional view of the cell array along line BB 'of FIG. 1.

In the figures, identical reference symbols designate identical or functionally identical components.

1 is a top view of a cell array in accordance with an embodiment of the memory cell arrangement according to the invention.

In FIG. 1, la-ld bit line trenches, 2a-2c word lines, 3a-3c denote exposed tires between word lines 2a to 2c, 10 a semiconductor substrate, S a memory cell and F the minimum structure width.

1 has a multiplicity of directly adjacent memory cells provided in a semiconductor substrate 10, only the memory cell S being designated for reasons of clarity. In the longitudinal direction in the main surface of the semiconductor substrate 10, the bit line trenches la-ld run parallel to one another, in the bottoms of which a lower bit line (15a-15d in FIGS. 2 and 3) is provided. An upper bit line (20a-20d in FIGS. 2 and 3) is provided in the crowns of the bit line trenches la-ld, and a channel region is provided in the walls of the bit line trenches la-ld, namely that between the lower bit lines and the upper ones Bit lines lying respective area.

In the transverse direction A-A 'along the main surface of the semiconductor substrate 10, through certain bit line trenches la-ld, word lines 2a-2c, which are isolated at least downwards, for driving the corresponding transistors of the memory cells, the structure of which is explained in more detail in connection with FIG. 2.

The dimensional relationships in the cell field according to this embodiment of the memory according to the invention are described below. arrangement explained. The soles of the bit line trenches la-ld, the crowns of the bit line trenches la-id and the word lines 2a-2c and the strips 3a-3c between the word lines each have a minimum structure width F. Each memory cell S thus occupies an area of 2 F ".

FIG. 2 is a vertical cross-sectional view of the cell array along line A-A 'of FIG. 1.

In FIG. 2, 10 designates a semiconductor substrate, 15a-15d the lower bit lines, 20a-20e the upper bit lines, 55 the upper insulation of the upper bit lines 20a-20e with respect to the word lines 2a-2c, 22 a gate oxide and 16 an insulating trench filling material .

As can be seen from FIG. 2, the memory cells are each arranged on opposite walls of the bit line trenches la-ld. The memory cells include first memory cells (e.g. in the bit line trenches la, lc, ld) in which a first logic value is stored and which have at least one vertical transistor. This vertical transistor is realized in that the word line extends into the trench over the corresponding channel region as a gate contact. The gate oxide layer 22 is provided between the respective gate contacts and the channel regions. Furthermore, the memory cells comprise second memory cells (e.g. in the bit line trench 1b), in which a second logic value is stored and which have no vertical transistor.

FIG. 3 is a vertical cross-sectional view of the cell array along line B-B 'of FIG. 1.

As can be seen in FIG. 3, the strips between the word lines 2a-2c have a silicon region which is not covered by gates and which between undesired leakage currents the trench crowns and the trench bottoms is at risk, namely, for example, charges in an oxide to be subsequently deposited thereon.

This is where the present invention comes in. Appropriately after the gate stack structuring, a dopant corresponding to the well doping in the cell field, e.g. In the case of a p-well, boron was additionally introduced over a large area into the trench walls of the bit line trenches la-ld, which lie between the word lines 2a-2c, in order to obtain the corresponding one there

Increase transistor threshold voltage of these exposed silicon areas to suppress leakage currents.

This is done by implanting II, 12 of the additional dopant into the trench walls which run between the word lines, the direction of implantation being in a plane perpendicular to the word lines and inclined as far as possible from the vertical in order to project the area dose high the vertical trench walls without too much shading through the web edges. In particular, two implantations II, 12 are carried out for introducing the additional dopant, which are inclined in opposite directions to the vertical to the main surface of the semiconductor substrate 10, so that both trench walls are reached.

The implantation is carried out in a self-adjusting manner with respect to the word lines 2a-2c. In order to prevent the dopant from leaking into the adjacent channels, this step should be carried out after the gate stack has been annealed.

Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not restricted to these but can be modified in a variety of ways. Although described in relation to a read-only memory, the present invention is also applicable to corresponding other memories with bit line trenches.

In particular, the specified basic materials and additional materials are only examples and can be replaced by suitable other materials.

The implantation can also take place in a separate photo plane in which at least planar and / or peripheral components are protected against the implantations.

Finally, the additional dopant can in principle also be introduced in an oven process.

Claims

claims

1. A memory cell arrangement with a multiplicity of memory cells (S) provided in a semiconductor substrate (10), with: in the longitudinal direction in the main surface of the semiconductor substrate (10) parallel bit line trenches (la-ld), in the bottoms of which a first conductive region (15a) 15d) is provided, in the crowns of which a second conductive region (20a-20e) of the same conductivity type as the first conductive region is provided and in the walls of which an intermediate channel region is provided; and word lines (2a-2c) running in the transverse direction along the main surface of the semiconductor substrate (10) through certain bit line trenches (la, lc, ld) for driving transistors provided there; Because of this, an additional doping substance has been introduced into the trench walls of the bit line trenches (la-ld), which lie between the word lines (2a-2c), in order to increase the corresponding transistor threshold voltage for suppressing leakage currents.

2. Memory cell arrangement according to claim 1, characterized in that the memory cell arrangement is a fixed value memory cell arrangement with memory cells (S) with a cell size of 2F ² , where F is the minimum structure width.

3. A memory cell arrangement as claimed in claim 2, that the memory cells are arranged on opposite walls of the bit line trenches (la-ld).

4. Memory cell arrangement according to claim 2 or 3, characterized in that the memory cells (S) first memory cells in which a first logical value is stored and the at least one verti- Kalalen transistor, and second memory cells in which a second logic value is stored and which have no vertical transistor.

5. A method for producing a memory cell arrangement according to at least one of the preceding claims, comprising the steps:

Providing the semiconductor substrate (10); Forming the bit line trenches (la-ld) in the main surface of the semiconductor substrate (10);

Form the first (15a-15d) and second (20a-20d) conductive

Areas preferably by simultaneous implantation or

Diffusion;

Forming the transistors at specific locations in the respective bit line trenches (la-le); and

Forming the word lines (2a-2c); by the step of introducing, preferably implanting (II, 12), the additional dopant into the trench walls which run between the word lines in order to increase the corresponding transistor threshold voltage there.

6. The method according to claim 5, so that two implantations (II, 12) are carried out for introducing the additional dopant, which are inclined in opposite directions to the vertical to the main surface of the semiconductor substrate (10).

7. The method of claim 5 or 6, d a d u r c h g e k e n n z e i c h n e t that the implantation is carried out in a self-adjusting manner with respect to the word lines (2a-2c).

8. The method according to claim 5, 6 or 7, that the implantation is carried out in a separate photo plane.