EP1057372A1 - Ballast electronique pour intensite variable comportant un seul etage de convertisseur a reaction - Google Patents

Ballast electronique pour intensite variable comportant un seul etage de convertisseur a reaction

Info

Publication number
EP1057372A1
EP1057372A1 EP99965515A EP99965515A EP1057372A1 EP 1057372 A1 EP1057372 A1 EP 1057372A1 EP 99965515 A EP99965515 A EP 99965515A EP 99965515 A EP99965515 A EP 99965515A EP 1057372 A1 EP1057372 A1 EP 1057372A1
Authority
EP
European Patent Office
Prior art keywords
load
power
inverter
voltage
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP99965515A
Other languages
German (de)
English (en)
Inventor
Jerzy Janczak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP1057372A1 publication Critical patent/EP1057372A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H05B41/282—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices
    • H05B41/2825—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices by means of a bridge converter in the final stage
    • H05B41/2828—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices by means of a bridge converter in the final stage using control circuits for the switching elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc
    • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters
    • H05B41/295—Circuit arrangements in which the lamp is fed by power derived from dc by means of a converter, e.g. by high-voltage dc using static converters with semiconductor devices and specially adapted for lamps with preheating electrodes, e.g. for fluorescent lamps
    • H05B41/298—Arrangements for protecting lamps or circuits against abnormal operating conditions
    • H05B41/2981—Arrangements for protecting lamps or circuits against abnormal operating conditions for protecting the circuit against abnormal operating conditions
    • H05B41/2986—Arrangements for protecting lamps or circuits against abnormal operating conditions for protecting the circuit against abnormal operating conditions against internal abnormal circuit conditions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/36—Controlling
    • H05B41/38—Controlling the intensity of light
    • H05B41/39—Controlling the intensity of light continuously
    • H05B41/392—Controlling the intensity of light continuously using semiconductor devices, e.g. thyristor
    • H05B41/3921—Controlling the intensity of light continuously using semiconductor devices, e.g. thyristor with possibility of light intensity variations
    • H05B41/3925—Controlling the intensity of light continuously using semiconductor devices, e.g. thyristor with possibility of light intensity variations by frequency variation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps

Definitions

  • the present application relates generally to electronic ballasts and, in particular, to a dimmable electronic ballast with a single stage feedback power factor controller inverter which provides high input power factor and good load current crest factor for variable load dimming
  • a conventional electronic ballast typically includes a high frequency inverter which operates at a frequency high enough such that component size may be minimized and lamp performance improved
  • electronic ballasts designed to operate with commercial and residential AC power typically include a full wave rectifier, an DC energy storage capacitor which supplies the inverter, and a resonance circuit for coupling the inverter to the load (e.g., fluorescent lamps).
  • These conventional electronic ballast circuits also include a preconditioner circuit which serves several functions. For instance, the preconditioner circuit operates by boosting the rectified peak AC voltage output from the rectifier and providing a substantially constant DC voltage supply (via the DC storage capacitor) to the inverter
  • U.S. Patent No 5,404,082 to Hernandez et al. entitled "High Frequency Inverter with Power-Line-Controlled Frequency Modulation” discloses a low-cost electronic ballast for use with fluorescent lamps which utilizes a single stage feedback inverter topology.
  • the electronic ballast includes a high frequency inverter connected to a storage capacitor which is isolated from the rectifier.
  • the resonant circuit which supplies current to the lamps, is coupled from the inverter to a node between the storage capacitor and the output of the rectifier.
  • a feedback capacitor in the resonant circuit alternatively receives power from the rectifier and delivers power to the storage capacitor at the high frequency rate.
  • the inverter frequency is varied during each half cycle of the low frequency input in a direction opposite to the rectified voltage, to minimize the lamp crest factor.
  • the present invention is directed to a high frequency dimmable electronic ballast with a single stage feedback power factor controller inverter, which provides regulation of power delivered to a load at low dim levels such that sufficient lamp crest factor is maintained for load changes from 100% to 10%.
  • Sufficient load current crest factors for variable load (dimming) is obtained by operating the ballast in a closed loop configuration, whereby the average value of the load current and/or power is measured and regulated.
  • an electronic ballast comprises: a single stage feedback inverter for supplying high frequency power to a load in response to driving signals; current sensing means for sensing current flowing in the load due to the supplied load power; dimming means for generating a illumination signal corresponding to a desired power level of the load; and a controller, operatively connected to the single stage feedback inverter and dimming means, for generating the driving signals to cause the inverter to supply the desired power level to the load, whereby the controller processes the sensed load current to maintain a sufficient lamp crest factor at the desired load power level.
  • Fig. 1 is a block diagram of an electronic ballast according to an embodiment of the present invention
  • Fig. 2 is a detailed circuit diagram of an electronic ballast shown in Fig. 1 according to an embodiment of the present invention.
  • Figs 3a, 3b and 3c are diagrams of test results of the circuit shown in Fig. 2 which illustrate the lamp crest factors obtained at various dimming levels.
  • the single stage feedback inverter topology of the electronic ballast includes an alternating current source 10 (e.g., standard AC line voltage of 120 volt and a frequency of 60 hz) provides input power for operating the ballast.
  • An electromagnetic interference (EMI) filter 12 filters high frequency signals and rf noise (e.g., harmonics) generated by the ballast, thereby preventing the conduction of such noise to the AC input source.
  • An AC rectifier circuit 14 rectifies the input AC power to provide rectified DC power.
  • EMI electromagnetic interference
  • the rectified DC power is coupled via a DC coupler 16 to a DC energy storage device 18 (e.g., an electrolytic capacitor).
  • the DC energy storage device 18 maintains a DC voltage which is relatively higher than the peak of the rectified AC voltage output by the rectifier 14.
  • An inverter 20 converts the DC voltage stored in the DC storage device 18 to a high frequency voltage having a frequency which may vary between about 20Khz and 75Khz.
  • a resonance circuit 22, operatively connected to the inverter 20, is arranged to resonate at a frequency somewhat lower than the normal range of the high frequency voltage during steady state operation of the ballast.
  • a load 24 e.g. a fluorescent lamp
  • a feedback loop connects the resonant circuit 22 to a feedback node in the DC coupling circuit 16.
  • the closed loop control circuitry for regulating the power consumed by the load during variable load dimming includes a peak voltage detector 28 for detecting the peak output voltage of the load.
  • a load current sensor 30 senses the current flowing through the load.
  • a driver/controller 32 operatively connected to the peak voltage detector 28 and the load current sensor 30, receives signals from the peak voltage detector 28 and load current sensor to determine the load power.
  • the driver/controller 32 regulates the load power in accordance with dimming level signals provided by a dimming interface 34.
  • the lamp illumination level can be increased and decreased by decreasing and increasing the frequency of the square wave voltage waveform, respectively.
  • the driver/controller 32 adjusts the high frequency waveform generated by the inverter to provide the proper load voltage.
  • the drive control circuit 32 is implemented as an integrated chip which is disclosed in U.S. Patent No. 5,742,134 to Wacyk et al. entitled "Inverter Driving Scheme", the disclosure of which is incorporated herein by reference.
  • the electronic ballast of the present invention which implements the drive controller disclosed in Wacyk with the conventional single stage feedback inverter will now be discussed in further detail.
  • Fig. 2 a detailed circuit diagram of the electronic ballast of Fig. 1 is shown.
  • the source of power for the ballast is an AC power line which is connected to input terminals 1 and 2.
  • the input terminals 1 and 2 are connected to a conventional full bridge rectifier consisting of diodes Dl through D4 via an EMI filter comprising line chokes LI and L2 and capacitors Cl, C2 and C3.
  • the negative terminal (node Nl) of the rectifier is connected to circuit ground.
  • the positive terminal (node N2) of the rectifier contains the rectified AC voltage Vrec.
  • the voltage Vrec is coupled to node N3 via fast recovery diode D5.
  • Node N3 is the feedback node, i.e., the node at which the feedback loop connects the resonant circuit 22 to the DC coupling/HF rectifier circuit 16 shown in Fig. 1).
  • a fast recovery diode D6 couples the voltage at node N3 to the storage (buffer) capacitor C5, and acts to rectify the high frequency feedback signal from the resonant circuit.
  • Transistors Ml and M2 (which are N channel Mosfets) form a high frequency half-bridge inverter having an inverter output node N5.
  • the switches Ml and M2 have a pair of gates gl and g2, respectively.
  • a resistor R and capacitor C 17 are electrically connected via node N6 and serially connected between node N4 and ground.
  • a pair of capacitors C6 and C7 are electrically connected at node N6 and serially connected between node N5 and ground.
  • a Zener diode D9 shunts capacitor C7.
  • Capacitors C6 and C7 operate to decrease the rate of the rise and fall of the voltage at node N5 during operation of the inverter, thereby reducing switching losses and the level of EMI generated by the inverter.
  • the zener diode D9 establishes a pulsating voltage and node N6 which is applied to capacitor C17 to provide the requisite operating current supplied to pin VDD.
  • a DC blocking capacitor C8 and resonant inductor L3 are serially connected between nodes N5 and the primary of load transformer Tl.
  • a resonant capacitor C9 is connected across the primary of load transformer Tl.
  • a winding T3 (i.e., the resonant current sensor 26) is magnetically coupled to the resonant inductor L3 to sense at least a portion of the current flowing through the resonant inductor L3. As explained in further detail below, this current is sensed to ensure that the switches operate in zero voltage switching mode (inductive mode) so as to minimize switching losses.
  • lamp current is directly fed from the inverter output node N5 through the coupling (DC blocking) capacitor C8 and a series resonant circuit formed by choke L3, resonant capacitor C9 and feedback capacitor C4.
  • diodes D5 and D6 are nonconducting, all the lamp current flows through the feedback capacitor C4.
  • the load circuit includes a plurality of serially connected lamps LI and L2.
  • the load also includes capacitors CIO, C12 and C13 which operate to provide filament heating during a preheating stage of operation as is known to those skilled in the art.
  • Capacitor Cl 1 prevents DC power from being applied to the lamps, thereby prolonging the life of the lamps.
  • a signal proportional to the load current is magnetically coupled via current transformer T2 (i.e., the load current sensor 30) which is used by integrated circuit IC 100 (as explained in further detail below) for controlling the load power at variable load levels so as to maintain sufficient lamp crest factor.
  • the IC 100 which includes a plurality of pins, drives and controls the switches
  • Wacyk Wacyk et al.
  • a pin VDD is connected to node N6 and provides the bias voltage (approximately 12v) for operating the IC 100.
  • a resistor R10 connected between a pin RREF and ground serves to set a reference current within the Alpha IC 100. The reference current is used for, among other things, regulating the minimum inverter frequency.
  • a resistor R9 and capacitor C15 se ⁇ ally connected between a pin CF and ground, sets the frequency of a current controlled oscillator (CCO) within the IC 100.
  • a capacitor C18 connected between a pm CP is employed for timing of both the preheat cycle and the nonoscillation/standby mode.
  • a GND pm is connected directly to ground.
  • a pin Gl is connected to the gate gl of switch Ml via a parallel combination of resistor Rl and diode D7.
  • a pin G2 is connected to the gate g2 of switch M2 via a parallel combination of resistor R2 and diode D8.
  • a pin SI is directly connected to node N5 and receives the voltage at the source of switch Ml
  • a pin FVDD is connected to node N5 via a capacitor 21 and represents the floating voltage of IC 100 (capacitor 21 provides energy to the upper gate switch d ⁇ ver Ml)
  • a pm REND is electrically coupled to a node N9 which se ⁇ ally connects resistor R6 and capacitor C18 between winding T3 and ground.
  • the input voltage at pin RENT is a representative measure of the cu ⁇ ent level flowing through resonant inductor L3.
  • the cu ⁇ ent through resonant inductor L3 is measured to determine whether the inverter is in or near a capacitive mode of operation, (i.e., when the current flowing through resonant inductor L3 leads the voltage across switch Ml). In near capacitive mode of operation, the cu ⁇ ent flowing through the resonant inductor L3 is close but does not lead the voltage across switch Ml.
  • inductor cu ⁇ ent sense circuitry of IC 100 which is operatively connected to pin RIND, detects whether forward conduction or body diode conduction (from the substrate to the drain) of switch Ml or M2 occurs.
  • the inductor cu ⁇ ent sense circuitry causes the inverter frequency to ⁇ se quickly, so as to ensure that the inverter is operating within an inductive mode (i.e., the voltage across switch M2 du ⁇ ng its non conductive state is leading in phase over the cu ⁇ ent flowing through resonant inductor L3).
  • the IC 100 also regulates the amplitude of the cu ⁇ ent flowing through the resonant inductor L3 by sensing the voltage at Pm REND
  • a pm LI2 is connected to cu ⁇ ent sensing transformer T2 via resistor R8.
  • a pin LI 1 is connected to ground via a resistor R7
  • the difference in cu ⁇ ents flowing in pins LI1 and LI2 is a measure of the sensed cu ⁇ ent flowing through the load (lamps). This sensed cu ⁇ ent is processed by the IC 100 to ensure sufficient lamp crest factors are obtained du ⁇ ng full load operation and va ⁇ able dimming (as discussed below).
  • a pin VL is connected to a network consisting of a parallel connection of diode D10 and capacitor C14, and detects the peak load voltage applied to the lamps (via a portion of the secondary winding of transformer Tl).
  • the VL pin is used, inter aha, for regulating lamp power and protecting the lamp load from overvoltage conditions.
  • the cu ⁇ ent input into the VL pin is proportional to the peak lamp voltage (i.e., a cu ⁇ ent flowing in resistor R5 due to the scaled voltage at node N10).
  • the current flowing into pin VL is multiplied by internal circuitry with the differential cu ⁇ ent between pms LI1 and LI2, to produce a rectified AC signal representing the product of the lamp cu ⁇ ent and the lamp voltage which is used for regulating the power of the load.
  • load power regulation For deep dimming levels (load levels of 15% or lower), it is preferable to regulate the load power using the peak load voltage and load cu ⁇ ent measurements. It is to be understood, however, that for higher dimming levels (greater than 15%), load power regulation may be significantly achieved by processing the sensed load cu ⁇ ent.
  • the rectified AC cu ⁇ ent flows out of a pin CRECT into ground via a parallel connection of resistor R12, capacitor C20 and a se ⁇ es connection of resistor R13 and capacitor C19, whereby the AC current is converted to a DC voltage which co ⁇ esponds to the average power of the load (load voltage times load current).
  • a DIM pm is connected to a dimming control interface (not shown).
  • the voltage applied to the DIM pm co ⁇ esponds to the level of illumination as set by dimming control interface (the voltage at the DEM p is a DC voltage).
  • the desired illumination level of the lamps LI and L2 is set by the voltage at the DIM pin.
  • the voltage at the CRECT Pin is forced equal to the voltage at the DIM pin by a feedback circuit within the IC 100.
  • the feedback loop includes a lamp voltage sensing circuit (i.e , the peak detection circuit discussed above and the VL pm as well as the internal circuitry of IC 100 operatively associated with pin VL) and a lamp cu ⁇ ent sensing circuit (i.e., the transformer T2 and the LI2 pin as well as the internal circuitry of IC 100 operatively associated with pins LI1 and LI2).
  • the inverter switching frequency is adjusted based on this feedback loop whereby the CRECT pin voltage is made equal to the voltage at the DIM pin.
  • the CRECT voltage vanes between .3 and 3.0 volts and the IC 100 clamps the voltage at Dim pin to .3 and 3.0 v.
  • the signal provided at the DIM pin may be provided through different methods known by those skilled in the art such as phase angle dimming in which a portion of the phase of the AC input line voltage is cut off. Such methods convert the cutoff phase angle of the input line voltage into a DC signal applied to the DIM pin.
  • phase angle dimming in which a portion of the phase of the AC input line voltage is cut off.
  • Such methods convert the cutoff phase angle of the input line voltage into a DC signal applied to the DIM pin.
  • the voltage at the CRECT pin is zero.
  • the cu ⁇ ent flowing from the CRECT pin (which is proportional to the product of the lamp voltage and lamp cu ⁇ ent) charges capacitor C20.
  • the switching frequency of the inverter will decrease or increase until the voltage at the CRECT pm is equal to the voltage at the DEM pin.
  • a voltage of .3 volts is equal to 10% of full load output and a voltage of 3 v. co ⁇ esponds to full (100%) light output).
  • Figs. 3a, 3b, and 3c test results of the circuit of Fig. 2 illustrate that sufficient lamp crest factor is obtained for variable loads.
  • Fig. 3a shows a lamp crest factor of not more than 1.6 is obtained for load current at 100% (no dimming).
  • Fig. 3b shows a lamp crest factor of not more than 1.8 is obtained with load cu ⁇ ent at 50%.
  • Fig. 3c. shows a lamp crest factor of not more than 2.0 is obtained with load cu ⁇ ent at 10%.

Landscapes

  • Circuit Arrangements For Discharge Lamps (AREA)
  • Inverter Devices (AREA)
  • Discharge-Lamp Control Circuits And Pulse- Feed Circuits (AREA)

Abstract

La présente invention concerne un ballast électronique haute fréquence pour intensité variable comportant un seul étage de convertisseur à réaction et un régulateur de facteur de puissance qui régule la puissance que le convertisseur apporte à une charge pour des niveaux d'intensité atténuée tels qu'on conserve un facteur de crête de la lampe suffisant pour des variations de la charge comprises entre 100 % et 10 %. Pour arriver à ces facteurs de crête de courant de charge suffisant pour une charge variable (atténuation), on fait fonctionner le ballast en circuit fermé, ce qui permet de mesurer et de réguler la valeur moyenne du courant et/ou de la puissance de la charge. Selon un aspect de l'invention, le ballast électronique comporte un étage unique de convertisseur à réaction capable de fournir à une charge un courant électrique haute fréquence en réaction à des signaux de commande. Le ballast comporte également, d'une part des détecteurs d'intensité vérifiant l'intensité circulant dans la charge en raison du courant électrique de charge fourni, et d'autre part des détecteurs de tension vérifiant la tension de crête de la charge en raison du courant électrique de charge fourni. Le ballast comporte enfin, non seulement un atténuateur produisant un signal d'éclairage correspondant à un niveau de puissance attendu pour la charge, mais aussi un régulateur, qui est connecté à l'étage unique du convertisseur à réaction et à l'atténuateur, et qui génère les signaux de commande amenant le convertisseur à donner à la charge le niveau de puissance attendu. En l'occurrence, le régulateur traite l'intensité de charge détectée et la tension de charge en crête détectée de façon à entretenir un facteur de crête de la lampe suffisant pour le niveau de puissance attendu pour la charge.
EP99965515A 1998-12-29 1999-12-17 Ballast electronique pour intensite variable comportant un seul etage de convertisseur a reaction Ceased EP1057372A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US22240598A 1998-12-29 1998-12-29
US222405 1998-12-29
PCT/EP1999/010195 WO2000040058A1 (fr) 1998-12-29 1999-12-17 Ballast electronique pour intensite variable comportant un seul etage de convertisseur a reaction

Publications (1)

Publication Number Publication Date
EP1057372A1 true EP1057372A1 (fr) 2000-12-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP99965515A Ceased EP1057372A1 (fr) 1998-12-29 1999-12-17 Ballast electronique pour intensite variable comportant un seul etage de convertisseur a reaction

Country Status (4)

Country Link
EP (1) EP1057372A1 (fr)
JP (1) JP2003529891A (fr)
CN (1) CN1291415A (fr)
WO (1) WO2000040058A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001078467A1 (fr) 2000-04-10 2001-10-18 Koninklijke Philips Electronics N.V. Ballast a detecteur de crete
US6798153B2 (en) * 2001-08-02 2004-09-28 Koninklijke Philips Electronics N.V. Method of regulating power in a high-intensity-discharge lamp
US7098605B2 (en) 2004-01-15 2006-08-29 Fairchild Semiconductor Corporation Full digital dimming ballast for a fluorescent lamp
DE102005027012A1 (de) 2005-06-10 2006-12-14 Patent-Treuhand-Gesellschaft für elektrische Glühlampen mbH Schaltungsanordnung und Verfahren zum Erfassen eines Crestfaktors eines Lampenstroms oder einer Lampenbrennspannung einer elektrischen Lampe
EP2119324A1 (fr) * 2007-01-11 2009-11-18 Osram Gesellschaft mit Beschränkter Haftung Procédé pour déterminer un facteur de crête d'un courant de lampe d'une lampe électrique
ITVI20120201A1 (it) * 2012-08-03 2012-11-02 E Z M S R L Dispositivo di regolazione della luminosita' di una lampada, o dimmer.
TWI692992B (zh) * 2018-07-10 2020-05-01 泉康科技有限公司 可調式安定器及其驅動方法
US20230113700A1 (en) * 2020-03-04 2023-04-13 Redisem Ltd. Controller, Power Converter, and Associated Methods

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315214A (en) * 1992-06-10 1994-05-24 Metcal, Inc. Dimmable high power factor high-efficiency electronic ballast controller integrated circuit with automatic ambient over-temperature shutdown
KR950005283B1 (ko) * 1992-10-08 1995-05-22 주식회사디엔에프전자 보호기능과 출력전압조절 및 조도조절이 가능한 초절전형 인버터회로
US5404082A (en) * 1993-04-23 1995-04-04 North American Philips Corporation High frequency inverter with power-line-controlled frequency modulation
US5742134A (en) * 1996-05-03 1998-04-21 Philips Electronics North America Corp. Inverter driving scheme

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0040058A1 *

Also Published As

Publication number Publication date
CN1291415A (zh) 2001-04-11
WO2000040058A1 (fr) 2000-07-06
JP2003529891A (ja) 2003-10-07

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