EP1050800A1 - Unité d'exécution en pipeline - Google Patents

Unité d'exécution en pipeline Download PDF

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Publication number
EP1050800A1
EP1050800A1 EP99410044A EP99410044A EP1050800A1 EP 1050800 A1 EP1050800 A1 EP 1050800A1 EP 99410044 A EP99410044 A EP 99410044A EP 99410044 A EP99410044 A EP 99410044A EP 1050800 A1 EP1050800 A1 EP 1050800A1
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EP
European Patent Office
Prior art keywords
data
execution
register file
stage
execution unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99410044A
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German (de)
English (en)
Inventor
Andrew Cofler
Laurent Ducousso
Bruno Fel
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STMicroelectronics SA
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STMicroelectronics SA
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Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to EP99410044A priority Critical patent/EP1050800A1/fr
Publication of EP1050800A1 publication Critical patent/EP1050800A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Definitions

  • the invention relates to a pipelined execution unit in a computer system.
  • the computer system described herein uses pipelined execution units for data manipulations.
  • the pipelined execution unit obtains operands comprising data values to be manipulated, and opcode defining a manipulation to be executed. It stores resulting data values.
  • the computer system described herein has a pipelined execution unit which communicates predominantly with a data register file from which operands are fetched for manipulation, and to which resultant values are written. Normally, data values which are needed in the data register file are loaded there from a main memory via a load data queue. Resultant values which are to be written back to memory are firstly written into the data register file and then stored back to main memory from there via a store data queue.
  • a pipelined execution unit for executing instructions which identify operands and include opcode defining how the operands are to be manipulated
  • the execution unit comprising: a data operand fetch stage connected to fetch operands from a data register file; at least one execution stage connected to receive operands from the data operand fetch stage and to manipulate the operands in dependence on the opcode; and a data write back stage connected to a data register file for writing back the results of the execution stage to the data register file, wherein the data register file includes a plurality of ports distributed through the pipelined execution unit and has the property that a data value written into the data register file at one of said ports during a cycle of operation is available to be read from a different one of said ports in the same cycle.
  • the pipelined execution unit can have a first addressable read port located in the data operand fetch stage and a first write port located at the output of the execution stage so that the results of the execution stage are available to the data operand fetch stage in a single cycle of operation.
  • a second write port can be located at the output of the data operand fetch stage and connected to receive data values from a load data queue which holds data values received from a main memory.
  • a second addressable read port can be located in the execution stage so that results of the execution stage can be read from the data register file in the same cycle for storing back to memory in the same cycle that they are written to the data register file.
  • the pipelined execution unit can have first switching circuitry arranged in the execution stage to selectively connect either the output of the execution stage or the output of the second addressable read port to the store data queue such that the store data queue can be simultaneously updated with the data register file when the output of the execution stage is selected.
  • the first switching circuitry can be responsive to a data dependency control signal (Hdep).
  • a set of switches can be connected to the outputs of the first addressable read port of a data register file and to the output of the load data queue to selectively supply operands from the load data queue or from the data register file to the execution stage.
  • the set of switches can be responsive to the data dependency control signal (Hdep)which thus determines whether operands are received from the load data queue or from the data register file.
  • Hdep data dependency control signal
  • Operands may also be available in the instructions themselves as immediate values.
  • the load data queue can be connected to the data register file such that when the execution stage receives an operand from the load data queue, the data register file is simultaneously updated.
  • the pipelined execution unit can include more than one execution stage, connected in series.
  • the execution stages can comprise a combination of arithmetic logical units and/or multiply accumulate units.
  • the invention also provides a method of operating a pipelined execution unit to execute a sequence of instructions which each identify operands and include opcode defining how the operands are to be manipulated, the method comprising; writing the result of execution of an instruction to a data register file, and fetching that result from the data register file for use as an operand in a subsequent execution cycle, wherein the result is written into the data register file and fetched from the data register file in the same execution cycle.
  • a method of operating a pipelined execution unit to execute a sequence of instructions which each identify operands and include opcode defining how the operands are to be manipulated in which method an operand is fetched from a load data queue which holds data values received from a main memory and supplied to an execution stage of the pipeline simultaneously with updating a data register file connected to the pipelined execution unit.
  • a method of operating a pipelined execution unit to execute a sequence of instructions which each identify operands and include opcode defining how the operands are to be manipulated in which method the result of execution of an instruction is written to a data register file and is read out of that data register file in the same execution cycle to be stored back to memory.
  • the invention also provides a computer system which uses a pair of parallel pipelined execution units for manipulating data values.
  • the computer system of this example is arranged for the parallel execution of a plurality of instructions and is particularly suited to providing a high digital signal processing (DSP) performance.
  • Instructions are held in a program memory 11 and after passing through a control unit 12 are supplied to four parallel execution pipelines 13,14,15 and 16.
  • Pipelines 13 and 14 are shown as slot 0 and slot 1 of a data unit 18 arranged to execute instructions carrying out arithmetic operations.
  • Pipelines 15 and 16 are shown as slot 0 and slot 1 of an address unit 19 used to execute instructions for memory accesses to a data memory 20.
  • Instructions can also be supplied to a general unit 21 which shares some resources with the address unit 19.
  • the general unit 21 includes a control register file 5 and branch circuitry and is used to provide instruction branch information on line 23 to the control unit 12.
  • the two pipelines 13 and 14 in the data unit 18 share a common data register file 26 and a common guard register file 27 holding guard values which may be associated with the instructions.
  • the two pipelines also derive instructions from a common instruction dispatch queue 29 in the data unit 18 and instructions in the queue 29 are checked for data dependency by common dependency check circuitry 30 in the data unit 18.
  • This dependency check refers to data dependency between instructions taken off the queue 29 in successive cycles into the same pipeline and is referred to as a vertical dependency.
  • the sequence of operations in each of the pipeline stages of the data unit 18 are illustrated schematically as a first stage 30 which is a data operand fetch usually accessing one of the register files 26 and/or 27.
  • Two successive execution stages 31 and 32 may occur in subsequent cycles using for example ALU units 33 or a multiply and accumulate unit 34.
  • the second execution stage 32 is followed by a data write back stage 35 at which the result of an arithmetic operation is returned to the register file 26 or 27.
  • a similar pipeline exists for the other pipeline of the data unit 18.
  • both pipelines 15 and 16 access a common pointer register file 40 holding pointer values for use in load or store operations in the data memory 20.
  • the two pipelines each take their instructions from a common instruction dispatch queue 41 and a similar vertical dependency check is provided in common for both pipelines 15 and 16 through the address unit 19.
  • the vertical dependency check 42 is similar to that referred to as the vertical dependency check 30 in the data unit.
  • In executing instructions which are taken through the two pipelines 15 and 16 accesses will be made to the register file 40 and add and subtract units 43 may be used by the two pipelines.
  • Each of the pipelines in the address unit has pipeline stages as illustrated. The first stage is an address operand fetch 44 followed by an execution stage 45 and an address write back stage 46.
  • bypass circuitry 47 is provided to allow bypassing of some stages of the pipeline.
  • Both the data unit 18 and the address unit 19 are connected to the data memory 20 through a data memory interface control 50 and a data memory controller 51.
  • the data memory interface control 50 is connected by two unidirectional buses 53 to both the data unit 18 and address unit 19.
  • the interface control 50 includes a plurality of queues each connected by a bus to the bus 53. These queues include load data queues 60 and 61 for slots 0 and 1 respectively. Queues 62 and 63 hold pointer values to be transferred to data registers for slot 0 and slot 1. Queues 64 and 65 hold data values for transfer to pointer registers for slots 0 and 1.
  • the data memory controller 51 includes store data queues 70 and store address queues 71.
  • the computer system operates access decoupling in that the memory access are effected independently of the arithmetic operations carried out within the data unit 18. This reduces the problem of memory latency. In a digital signal processing system which operates regular and repeated operations, the effective memory latency can be hidden from the executing program.
  • the control unit 12 shown in Figure 1 is also arranged to provide a horizontal dependency check.
  • a data and/or guard dependency between instructions that are supplied to the parallel pipelines in the same machine cycle is referred to as a horizontal dependency.
  • the control unit 12 includes a program counter and address generator 80 to provide a memory address for an instruction fetch operation from the program memory 11.
  • the control unit includes a process status register 81 which includes two bits to indicate the instruction mode in which the machine is operating at any instant.
  • the machine may operate in a selected one of a plurality of modes including superscalar modes of variable instruction bit length or in very long instruction word (VLIW). Examples of the different modes of this example are shown in Figure 5.
  • VLIW very long instruction word
  • a pair of 16 bit instructions are supplied during each machine cycle to a decoder 82 in the control unit 12. This pair is denoted as slot 0, slot 1 with a bit sequence W0, W1 etc.
  • Each bit sequence W0, W1 is issued in one machine cycle and this mode is referred to herein as GP16 mode which is a superscalar mode.
  • a second superscalar instruction mode two instructions each having a length of 32 bits are supplied to the decoder 82 in each machine cycle. In this case both bit sequences W0 and W1 are issued in cycle 0 and bit sequences W2 and W3 are issued in cycle 1.
  • This mode is referred to herein as GP32 mode.
  • a third instruction mode four instructions are formed by the bit sequences W0, W1, W2 and W3 each of 32 bits in length. These are supplied in a single cycle as a result of a single fetch operation to the decoder 82. This is referred to herein as a VLIW mode.
  • a VLIW instruction is formed of four GP32 instructions.
  • VLIW mode dependency checks are carried out by hardware in Figure 1. Instructions which can be grouped together in a single word in VLIW mode are governed by specified rules of instruction compatibility. Although Figure 5 refers to slots 0-3 for VLIW mode, it will be understood that the four slots in question correspond to the two slots of the data unit and the two slots of the address unit. Consequently the grouping of the instructions within the VLIW word must always include zero, one or two instructions for the address unit and zero, one or two instructions for the data unit.
  • One of the address unit slots of the VLIW mode may include a control instruction for use by the general unit 21.
  • the checker 87 provides an output to the control circuit 85 to indicate if a horizontal data dependency has been located.
  • the checker 87 is fed to a selector circuit 90 which provides either an Hdep signal on line 91 or a split signal on line 92 depending on the instructions which have been decoded by the decoder 82.
  • the split signal 92 indicates that a split in the operation of a pair of parallel execution pipelines is necessary in order to resolve a horizontal dependency, and is not discussed further herein.
  • Hdep indicates that there is a dependency which can be resolved by the pipeline construction, without the need for a temporary stall in operation of the pipeline.
  • Instructions from the decoder 82 are passed to a microinstruction generator 98 which generates a plurality of parallel microinstructions which are output by a dispatch circuit 99 through lines 100 to the four parallel execution pipelines 13,14,15 and 16.
  • the format of the microinstructions is independent of the instruction mode of the machine. In the event that the split signal 96 has been enabled, a split bit will be set in the microinstruction passed to the respective execution pipeline so that the data and/or guard dependency can be resolved.
  • the horizontal dependency control 85 will provide an output on line 91 indicating Hdep rather than a split signal on line 92.
  • the signal Hdep on line 91 is provided only in relation to microinstructions supplied to the data unit 13. However, it could be supplied to the address unit as well.
  • the microinstruction generator 98 will include an indication in the microinstructions that Hdep from line 91 has been set. The Hdep indication is supplied to the instruction dispatch queue 29 of the data unit 18 as part of the microinstructions.
  • one pipeline 13 of the data unit 18 may be executing an instruction to load a value into a register in the register file 26 while the other pipeline 14 is attempting to use the value of that data register as an operand in an arithmetic operation.
  • the use of the Hdep signal in the microinstruction will indicate to the arithmetic operation attempting to locate the correct operand that it is not necessary to stall the pipeline as the value it requires as an operand will already be available from a load data queue 60.
  • Figure 2 is a diagram which illustrates schematically the principles of operation of the data unit pipelines D0, D1. Only one of the pipelines is illustrated in Figure 2.
  • Figure 2 illustrates that the data register file 26 includes addressing circuitry 26a which allows particular registers in the data register file 26 to be accessed.
  • the data unit instruction dispatch queue 29 issues addresses to the data register file 26 along address bus 200.
  • the instruction dispatch queue 29 can issue a plurality of addresses to the data registe-r file in each machine cycle.
  • Each instruction can consist of up to three source operands and one destination operand. So each instruction can issue three addresses to the data register file 26 in each machine cycle in the operand fetch stage.
  • the second execution stage may, in the same machine cycle read an operand for an earlier store operation.
  • up to eight read addresses may be issued to the data register file 26 in each machine cycle, with up to two write accesses. To allow this for two pipelines the data register file 26 has eight read ports and four write ports.
  • the data register file outputs data values from the addressed registers along data bus 202 to the execution stages 31,32.
  • the instruction dispatch queue 29 also issues opcode to the execution stages 31,32.
  • the output of the second execution stage 32 is connected back to the data register file 26 so that the results of operations of the execution stages 31,32 can be loaded into the data register file at the appropriately addressed register.
  • the operational timing of the pipeline is under control of the pipeline control unit 204.
  • the data register file 26 is additionally in communication with the load data queues 60,61 and the store data queues 70. Note that only a single load data queue is illustrated in Figure 2 for illustrative purposes.
  • the loading of data in and out of the data register file from the load data queue and to the store data queue is under control of the data memory interface control 50 and the data memory controller 51 as already mentioned earlier.
  • source addresses SREG0,SREG1,SREG2 are supplied from the IDQ 29 to the data register file 26 which correspondingly supplies operands SRC0,SRC1,SRC2 to a set of flip-flops 209 on the boundary between the DOF stage and the first execution unit 31.
  • Opcode from a microinstruction in the IDQ 29 is supplied to a flip-flop 224 on the same boundary.
  • a destination address DEST is supplied to a flip-flop 223.
  • first and second operands SRC0,SCR1 are supplied to the first execution unit 31 together with any opcode relevant to that unit.
  • the opcode is propagated through the pipeline by latching into a further flip-flop 226 on the boundary between the first and second execution stages.
  • the first execution unit 31 manipulates the first and second operands SRC0,SRC1 in accordance with the opcode and provides a result RES1 to a flip-flop 213 on that boundary.
  • the third operand SRC2 is supplied to a flip-flop 212 on the boundary between the first and second execution stages, and the destination address DEST is supplied to a flip-flop 225.
  • the third operand SRC2 is supplied to the second execution stage 32 together with the opcode.
  • the second result RES2 is generated by the second execution unit 32 and can be supplied by a multiplexor 216 to a flip-flop 217 on the boundary between the second execution stage and the data write back stage. If there is no second result, the first result from the first execution stage EX 1 is propagated through the pipeline via the multiplexor 216.
  • the destinationaddress DEST is supplied to a flip-flop 227.
  • Figure 4 illustrates the four pipeline stages 30,31,32,35 as described above with reference to Figure 1.
  • the data register file 26 includes a number of ports which are shown distributed through the pipeline to illustrate the principles of the pipeline construction.
  • the first port DRF 1 can be considered as part of the data operand fetch stage 30 of the pipeline and outputs data operands responsive to the register addresses SREG0,SREG1,SREG2.
  • the operands SRC0,SRC1,SCR2 are supplied via respective multiplexors 208 0 ,208 1 ,208 2 and flip-flops 209 0 ,209 1 ,209 2 to the first and second execution stages 31,32.
  • the multiplexors 208 0 ,208 1 ,208 2 are also connected to receive operands from the load data queues 60,61.
  • the output of the load data queues 60,61 is also connected to the write input of a second port DRF 2 of the data register file to write in operands or results at a destination register defined by the dest_reg field of an instruction in the IDQ 29.
  • the dest_reg address is supplied via a flip-flop 211. This allows data supplied to the execution stages 31,32 from the load data queues 60,61 to simultaneously update the data register file DRF 2 . Thus, when the required operands are available on the load data queues 60,61 as indicated by the Hdep signal, this allows a cycle of operation to be saved because the data can be loaded into first execution stages 31,32 while the data register file 26 is simultaneously updated.
  • the Hdep signal is derived from the microinstruction in the IDQ 29.
  • a multiplexor 210 selectively supplies the first operand SRC0 to the first execution stage 31 or an immediate value IMMED which is obtained directly from the microinstructions in the IDQ 29. This is determined by a control signal imm applied to the multiplexor 210 which is derived from code in the microinstruction itself.
  • a flip-flop 212 allows the operand SRC2 to be supplied to the second execution stage 32 if necessary.
  • a flip-flop 213 allows the result RES1 generated by the first execution stage 31 to be supplied to the second execution stage 32. This may not always be necessary, and if the second execution stage 32 is not necessary, a bypass 214 can be implemented.
  • the output of the second execution stage 32 and the bypass 214 are connected to a multiplexor 216, the output of which is used to update the data register file 26 at a third port thereof DRF 3 .
  • the address of the destination register is supplied from the IDQ as indicated by the address line dest_reg via a sequence of flip-flops 220 0 ,220 1 ,220 2 .
  • the output of the multiplexor 216 is supplied to a multiplexor 218 with attached flip-flop 219, the output of which is connected to the store data queue 70.
  • the other input of the multiplexor 218 is connected to an output from a fourth port of the data register file DRF 4 .
  • the source register addresses for a store operation are supplied to the data register file 26 at the port DRF 4 via flip-flips 222 0 and 222 1 .
  • the source register address is derived from the microinstruction.
  • the microinstruction also contains opcode which is supplied to the first execution unit via a flip-flop 224 to second execution unit 32 via a flip-flop 226.
  • opcode causing a store operation is supplied to the data register file at the port DRF 4 .
  • a data value written to a destination register of the data register file 26 at the third port DRF 3 as a result of execution by the execution stages is available as an operand in the DOF stage from the first port DRF 1 in the same cycle of operation.
  • location of DRF 4 in the second execution stage allows the update of a register in the data register file 26 (by the DWB stage at port DRF3) to be seen by the read of the same register for a store by the port DRF 4 in the EX 2 stage.
  • connection of the second port DRF 2 with respect to the load data queues 60,61 allows the data register file to be updated simultaneously as data from the load data queue is supplied to the first execution unit 31 when the Hdep signal is set as decoded from the microinstruction.
  • block DRF 3 with respect to the second execution stage 32 and the multiplexor 218 connecting its output to the store data queue 70 allows write-back to the store data queue to occur in the same cycle as updating a data register file by the results of the second execution unit 32.
  • the WR input labelled on the second port DRF 2 illustrates the updating of the data register file from the load data queue at the register identified by the dest reg address. That is, an address is supplied to the data register file at which data from the load data queues 60,61 is written.
  • the opcode-store input of the fourth port DRF 4 illustrates the store function of the data register file 26 to store data held in an addressed source register of the data register file back to memory via the store data queue 70.

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EP99410044A 1999-05-03 1999-05-03 Unité d'exécution en pipeline Withdrawn EP1050800A1 (fr)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2207090A1 (fr) * 2009-01-09 2010-07-14 STMicroelectronics R&D Ltd Appareil comprenant une pluralité d'unités logiques arithmétiques
WO2016200569A1 (fr) * 2015-06-08 2016-12-15 Qualcomm Incorporated Système, appareil et procédé pour une instruction de charge temporaire
CN109933372A (zh) * 2019-02-26 2019-06-25 西安理工大学 一种多模式动态可切换架构低功耗处理器
WO2020223575A1 (fr) * 2019-05-02 2020-11-05 Dell Products L.P. Système de déplacement de données activé par transformée de données en pipeline

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4819155A (en) * 1987-06-01 1989-04-04 Wulf William A Apparatus for reading to and writing from memory streams of data while concurrently executing a plurality of data processing operations
WO1992009025A2 (fr) 1990-11-02 1992-05-29 Analog Devices, Inc. Fichier de registres a acces multiple a transmission directe de donnees
EP0653703A1 (fr) * 1993-11-17 1995-05-17 Sun Microsystems, Inc. Jeu de registres temporaire pour un processeur superpipeline-superscalaire
US5546569A (en) 1993-02-19 1996-08-13 Intergraph Corporation Apparatus for writing data to and reading data from a multi-port RAM in a single clock cycle
EP0902360A2 (fr) 1997-09-12 1999-03-17 Siemens Microelectronics, Inc. Dispositif d'accès lecture/écriture de régistres dans une unité centrale de traitement

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4819155A (en) * 1987-06-01 1989-04-04 Wulf William A Apparatus for reading to and writing from memory streams of data while concurrently executing a plurality of data processing operations
WO1992009025A2 (fr) 1990-11-02 1992-05-29 Analog Devices, Inc. Fichier de registres a acces multiple a transmission directe de donnees
US5546569A (en) 1993-02-19 1996-08-13 Intergraph Corporation Apparatus for writing data to and reading data from a multi-port RAM in a single clock cycle
EP0653703A1 (fr) * 1993-11-17 1995-05-17 Sun Microsystems, Inc. Jeu de registres temporaire pour un processeur superpipeline-superscalaire
EP0902360A2 (fr) 1997-09-12 1999-03-17 Siemens Microelectronics, Inc. Dispositif d'accès lecture/écriture de régistres dans une unité centrale de traitement

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"METHOD TO MAINTAIN PIPELINE THROUGHPUT WHILE PIPELINE DEPTH IS ALLOWED TO VARY", IBM TECHNICAL DISCLOSURE BULLETIN,US,IBM CORP. NEW YORK, vol. 39, no. 5, pages 31-32, XP000584045, ISSN: 0018-8689 *

Cited By (14)

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US9311103B2 (en) 2009-01-09 2016-04-12 Stmicroelectronics (Research & Development) Limited Apparatus for switching a plurality of ALUs between tree and cascade configurations
EP2207090A1 (fr) * 2009-01-09 2010-07-14 STMicroelectronics R&D Ltd Appareil comprenant une pluralité d'unités logiques arithmétiques
US11561792B2 (en) 2015-06-08 2023-01-24 Qualcomm Incorporated System, apparatus, and method for a transient load instruction within a VLIW operation
WO2016200569A1 (fr) * 2015-06-08 2016-12-15 Qualcomm Incorporated Système, appareil et procédé pour une instruction de charge temporaire
CN107636611A (zh) * 2015-06-08 2018-01-26 高通股份有限公司 用于临时加载指令的系统、设备和方法
KR20180016378A (ko) * 2015-06-08 2018-02-14 퀄컴 인코포레이티드 임시적 로드 명령을 위한 시스템, 장치, 및 방법
JP2018517212A (ja) * 2015-06-08 2018-06-28 クアルコム，インコーポレイテッド 一時的なロード命令のためのシステム、装置および方法
CN109933372A (zh) * 2019-02-26 2019-06-25 西安理工大学 一种多模式动态可切换架构低功耗处理器
CN109933372B (zh) * 2019-02-26 2022-12-09 西安理工大学 一种多模式动态可切换架构低功耗处理器
US11157423B2 (en) 2019-05-02 2021-10-26 Dell Products L.P. Pipelined-data-transform-enabled data mover system
CN113692570A (zh) * 2019-05-02 2021-11-23 戴尔产品有限公司 支持管道式数据转换的数据移动器系统
TWI778350B (zh) * 2019-05-02 2022-09-21 美商戴爾產品有限公司 具管線式資料變換功能之資料移動器系統
WO2020223575A1 (fr) * 2019-05-02 2020-11-05 Dell Products L.P. Système de déplacement de données activé par transformée de données en pipeline
CN113692570B (zh) * 2019-05-02 2024-04-16 戴尔产品有限公司 支持管道式数据转换的数据移动器系统

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