Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
  • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
  • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
  • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
  • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
  • H01L23/26—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device including materials for absorbing or reacting with moisture or other undesired substances, e.g. getters
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
  • H10K59/80—Constructional details
  • H10K59/87—Passivation; Containers; Encapsulations
  • H10K59/871—Self-supporting sealing arrangements
  • H10K59/8721—Metallic sealing arrangements
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
  • H10K59/80—Constructional details
  • H10K59/87—Passivation; Containers; Encapsulations
  • H10K59/871—Self-supporting sealing arrangements
  • H10K59/8722—Peripheral sealing arrangements, e.g. adhesives, sealants
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
  • H10K59/80—Constructional details
  • H10K59/87—Passivation; Containers; Encapsulations
  • H10K59/871—Self-supporting sealing arrangements
  • H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
  • H10K59/80—Constructional details
  • H10K59/87—Passivation; Containers; Encapsulations
  • H10K59/873—Encapsulations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
  • H10K59/80—Constructional details
  • H10K59/87—Passivation; Containers; Encapsulations
  • H10K59/874—Passivation; Containers; Encapsulations including getter material or desiccant
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
  • H01L2224/732—Location after the connecting process
  • H01L2224/73251—Location after the connecting process on different surfaces
  • H01L2224/73253—Bump and layer connectors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
  • H01L2924/097—Glass-ceramics, e.g. devitrified glass
  • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/12—Passive devices, e.g. 2 terminal devices
  • H01L2924/1204—Optical Diode
  • H01L2924/12044—OLED
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
  • H10K59/80—Constructional details
  • H10K59/8794—Arrangements for heating and cooling

Definitions

• the present invention relates to the packaging of single chip integrated active matrix drivers and organic light emitting diode layers.
• the present invention is directed to a method for packaging chip displays that provide a hermetic seal and a compact design.
• Miniature displays are of great interest for head wearable and body wearable applications.
• an optical system magnifies the display so that the user perceives a very large display area.
• This large display can be used to present life-sized still and/or full motion video scenes of real, enhanced, altered, or virtual realities when coupled with the proper systems for generating such images.
• Military, security, and law enforcement agencies use such systems to view scenes in the infrared, with low light, or from remote locations to name a few.
• Surgeons can use such systems to view real-time x-ray or endoscopic images during surgery, or to remotely assist in operations.
• Engineers and designers can view and create designs in three dimensions. Architects and their clients can explore new homes and buildings that only exist as a design in a computer. Existing places and structures can be experienced through libraries of interactive stored views.
• Sophisticated entertainment systems can immerse participants in real-time interactive artificial realities.
• the large perceived display area can also present large amounts of information to the user.
• Maintenance workers can access remote sensors, manuals with illustrations, and consult face to face with distant engineering support groups without ever leaving the work site. Travelers can have large display monitors for their portable computers that would otherwise be impossible to carry or power. All of these existing and potential applications depend on ultra compact, high-resolution displays. They must be compact, lightweight, and low power to enable the design of comfortable body worn portable systems. They must have high resolution to display the necessary information content.
• OLEDs Organic light emitting diodes
• a display chip When upwardly emitting configurations of OLEDs are deposited on single chip active matrix drivers, an emissive matrix addressable display is created (hereafter referred to as "a display chip").
• display chips can be made very small (e.g., less than an inch) have very high display resolutions (1280 x 1024 pixels and higher), and be fabricated as either monochrome or color display chips.
• the display chips also have relatively few connections because image data is located serially and locally converted to the required parallel information by the on-chip addressing logic.
• Packaging for the display chips must meet several stringent requirements.
• the OLED materials used in these display chips are sensitive to minute amounts ( ⁇ lppm) of water and oxygen and must be protected from exposure to either throughout the useful lifetime of the display chip device. Since the display chip or package may be exposed to water and oxygen during operation or storage, it may also be necessary to include a desiccant or getter material inside the package to scavenge these harmful impurities.
• Currently available OLED materials are also sensitive to temperatures in excess of 100° C for more than a few minutes so packaging processing should not exceed these conditions.
• the window through which the display is viewed should be thin and very close to the OLED surface to simplify the design of the optical viewing system. Provisions for the removal of heat may be required in some applications.
• the package must be as small and compact as possible to reduce weight and minimize volume.
• hermetic packages use a box-like container with a cover that is frit sealed, brazed, or welded in place.
• the containers are frequently made of metal or ceramic and have electrical feed through to carry electrical connections from the device to the outside of the container. This type of package is excessively bulky and heavy for the applications described above. Additionally, the high temperature processing for brazing or frit scaling is too high for the OLED materials.
• wire bonding is used to connect the chip to the electrical feed through. An upward loop of the wire bond needed for reliability prevents the window from being as close to the display surface as desired.
• FED Field Emissive Displays
• Image Intensifiers are technologies requiring a hermetic seal, although for different reasons. Being driven by high vacuum requirements, the FED technology must rely on a mechanically strong seal in addition to a hermetic one.
• Two technologies have been developed to meet these requirements: a glass frit seal and a metal seal. Both leave an open window for display viewing.
• the frit seal requires an elevated temperature (450 °C typically) incompatible with OLED materials.
• Metal seals have been widely used for image intensifiers and are implemented using a high pressure to "ram" an edge into a cavity or gutter containing a soft metal such as indium. This technique is not readily applicable to a flat panel structure and would result in increased package depth at the very least.
• the packaging assembly may comprise a first cover member and a second cover member spaced from the first cover member.
• the packaging assembly may further comprise sealing means for connecting the first cover member to the second cover member.
• the sealing means, the first cover member and the second cover member form an enclosure adapted for receiving the display chip device therein.
• the sealing means may comprise at least one layer for securing the first cover member to the second cover member.
• the sealing means may comprise a first insulating assembly secured to the first cover member, a second insulating assembly secured to the second cover member, and a sealing assembly for sealing the first insulating member to the second insulator member.
• the sealing assembly may comprise a first seal assembly secured to the first insulating assembly, and a second seal assembly secured to the second insulating assembly. Additionally, the sealing assembly may further include at least one intermediate seal assembly for securing the first seal assembly to the second seal assembly.
• the at least one intermediate seal assembly may be formed from a metal. In particular, the at least one intermediate seal assembly may be formed from a low melting point metal alloy.
• At least one electrical connector may be formed on one of the first cover member and the second cover member.
• the at least one electrical connector are adapted for electrically connecting the display chip device to outside the packaging assembly.
• the at least one electrical connector may be located on the first cover member. Furthermore, the at least one electrical connector is at least partially located between the first cover member and the first insulating assembly.
• the packaging assembly may further include an absorbing means for absorbing at least one of moisture and oxygen within the enclosure.
• the absorbing means may be located on one of the first cover member and the second cover member.
• the absorbing means may include at least one layer of a getter material.
• the packaging assembly may further include heat transfer means for transferring heat from the display chip device.
• the heat transfer means may be located on one of the first cover member and the second cover member.
• the heat transfer means may include a thermal transfer assembly. The thermal transfer assembly may be in contact with the display chip device and one of the first cover member and the second cover member.
• the packaging assembly may include a sealing means having a spacer assembly, and a sealing assembly for sealing the spacer assembly to the first cover member and the second cover member.
• the sealing assembly includes an adhesive.
• a packaging assembly for a display chip device having a first cover member adapted to connected to the display chip device, and sealing means for forming a seal between the first cover member and the display chip device.
• the sealing means may includes an adhesive.
• the adhesive forms a filet between the first conductor layer and the chip display device.
• the packaging assembly may further include a second cover member.
• the second cover member is secured to the sealing means.
• the first cover member and the second cover member form an enclosure for the chip display device.
• the packaging assembly may further include at least one barrier layer located between the second cover member and the sealing means.
• a method of sealing a chip display device includes the steps of providing a first cover member, securing the chip display device to the first cover member, providing a second cover member, and sealing the second cover member to the first cover member to form a sealed enclosure for the chip display device.
• the step of sealing the second cover member to the first cover member may include the steps of securing a first insulating assembly to the first cover member, securing a second insulating assembly to the second cover member, and securing the first insulating assembly to the second insulating member with a sealing assembly.
• the step of securing the first insulating assembly to the second insulating member may include securing a first seal assembly to the first insulating assembly, securing a second seal assembly to the second insulating assembly, and securing the first seal assembly to the second seal assembly.
• the step of securing the first seal assembly to the second seal assembly may include the step of securing the first seal assembly to the second seal assembly using at least one intermediate seal assembly.
• the method includes the steps of providing a first cover member, and securing the chip display device to the first cover member.
• the step of sealing chip display device to the first cover member may include the step of using an adhesive.
• the method may further include the steps of providing a second cover member, sealing the second cover member to the first cover member to form a sealed enclosure for the chip display device.
• the method may further include the step of providing a barrier layer between the second cover member and the chip display device.
• FIG. 1 is a schematic view of a packaging assembly for a display chip device having a sealing assembly according to an embodiment of the present invention
• Fig. 2 is a side view of the packaging assembly according to another embodiment of the present invention
• Fig.3 is a side view of another packaging assembly according to another embodiment of the present invention
• Fig.4 is a side view of another packaging assembly according to another embodiment of the present invention.
• Fig. 5 is a side view of yet another embodiment of the packaging assembly according to the present invention.
• Fig. 6 is a side view of a packaging assembly according to another embodiment of the present invention.
• the display chip device 10 has conductive bumps 11 added to the electrical input/output connections. Additionally, conductive bumps 12 may be added as nonfunctional connections. The bumps 11 and 12 are added using known techniques. While Au may be the most reliable material for the bumps, other materials (solder, electrically conductive polymers, etc.) can be used.
• the packaging assembly 100 includes a first cover member 110.
• the first cover member 100 may be transparent to permit the transmission of light from the chip display device 10.
• the first cover member 100 may be formed from a thin glass, glass ceramic, sapphire or other suitable transparent insulator material.
• the first cover member 110 has conductive patterns 111 and 112 formed on a surface thereof.
• the conductive patterns 111 align with the conductor bumps 11 on the chip display device 10.
• the conductive patterns 112 align with the conductor bumps 12 on the chip display device 10.
• the conductive patterns 111 and 112 may be formed from Cr-Ni-Au or other suitable conductors using standard lithographic techniques.
• the conductive patterns 111 and 112 extend from within the packaging assembly 100 to the exterior to provide external electrical connections for the chip display device 10 located within the packaging assembly.
• the display device 10 may be secured to the first cover member through the conductor bump 11 and 12 and conductive patterns 111 and 112 by compression bonding.
• the conductive bumps 11 and 12 serve to align the display device 10 with the first cover member 110 such that the display device 10 is substantially parallel to the first cover member 110.
• the conductive bumps 12 and conductive patterns 112 are only required when there is an insufficient distribution of conductive bumps 11 around the periphery of the display chip device 10.
• the conductive bumps 11 and 12 also provide a small space between the first cover member 110 and the display chip device 10. The small space is desirable for at least two reasons. First, any water or oxygen that may be introduced between the display chip 10 or first cover member 110 during subsequent operation or storage may be conducted through the space to desiccant or getter material, described below, where it can be absorbed or reacted and made harmless.
• any particles that may reside on the first cover member 110 or display chip 10 may fit in the space and not contact the opposite surface such that particles would not be forced, by the bonding of chip 10 on to conductors 111 and 112, to penetrate the surface of the OLED layers of display chip 10 and cause defects in the display. Keeping this space small and highly uniform conveys these benefits while preserving the optical design objective of having the display surface close to the window.
• a portion of the first cover member 110 and conductive patterns 111 are covered with a first insulator layer 120.
• the first insulator layer 120 preferably surrounds the display chip device 10. Any suitable insulative material that prevents moisture from entering the packaging assembly 100 may be used such as, for example, is sputtered quartz or a CVD SiO 2 .
• a first seal assembly 130 is placed on the first insulator layer 120.
• the first insulator layer 120 prevent conductors 111 from being shorted by the first seal assembly 130.
• the first seal assembly 130 is preferably formed from a metal alloy.
• the first insulator 120 is preferentially wider than seal assembly 130 to insure the isolation of the metal in the first seal assembly 130 from the metal of the conductors 111.
• the first seal assembly 130 is formed by placing a layer of Cr on the underside of the first insulator layer 120, a layer of Ni on the underside of the Cr layer and a layer of Au on the underside of the Ni layer.
• the metal layers may be deposited by sputtering, evaporation, plating or suitable combinations of these processes. Other material combinations for the seal band may be devised by those skilled in the art.
• the first seal assembly 130 is not limited to above-described materials; rather it is contemplated that are materials are within the scope of the present invention.
• the packaging assembly 100 further includes a cap assembly 140.
• the cap assembly 140 may be fabricated as a separate assembly before it is secured to the first seal assembly 130.
• the cap assembly 140 includes a second cover member 141.
• the second cover member 141 may be formed from a suitable material that is not penetratable by moisture or oxygen.
• a second insulating layer or spacer layer 142 is secured to the second cover member 141.
• a second seal assembly 143 is formed on the spacer layer 142.
• the second seal assembly 143 is formed by depositing a layer of Cr on the upper side of layer 142, a layer of Ni on the upper side of the Cr layer, and a layer of Au on the upper side of the Ni layer. It is contemplated by the inventors of the present invention that ordering of the layers of the second seal assembly may be altered. Furthermore, it is contemplated that other suitable materials may be substituted.
• the packaging assembly 100 may be provided with a moisture absorbing assembly 150.
• the absorbing assembly 150 may comprise a desiccant or getter material layer formed on the second cover member 141, as shown in Fig. 2 layer formed on the upper side of plate 22. This desiccant is intended to remove any residual water inside the package that enters the package or is released by elements of the package after sealing.
• a getter material is intended to remove water and additional reactive vapors or gasses such as oxygen that enter the package or are released by elements of the package after sealing.
• the packaging assembly 100 may further include a heat transfer assembly 160, as shown in Fig.2.
• the heat transfer assembly 160 may include a compliant thermal conduction element that may be a layer of a thermally conductive compound (water and oxygen free grease) or a mechanical thermally conductive devices such as springs attached that provide a compliant thermally conductive pathway from the back of display chip device 10 to the second cover member 141.
• the cap assembly 140 is sealed to the first seal assembly 130 by an intermediate seal assembly 170.
• the intermediate seal assembly 170 preferably includes a low-temperature- melting-point-metal-alloy such as an InSn eutectic alloy.
• the intermediate seal assembly 170 is placed between the Au layer of the first seal assembly 130 and the Au layer of second seal assembly 143 to form a hermetic seal.
• the first seal assembly 130, the second seal assembly 143 and the intermediate seal assembly 170 are then bonded together by melting. This operation is performed in a highly dry, oxygen-free environment, such as argon, which is compatible with all of the other materials, including any getters that may be used.
• a vacuum is also a permissible and possibly desirable environment.
• the packaging assembly 200 includes a first cover member 110, a first insulator layer 120 and first seal assembly 130, as described above in connection with packaging assembly 100.
• the packaging assembly 200 includes a cap assembly 240.
• the cap assembly 240 may include a heat transfer assembly 160, as described above, and a moisture absorbing assembly 150 containing a patterned desiccant or getter material.
• the heat transfer assembly 160 makes physical contact with the back of display chip device 10 when cap 240 is in place.
• the moisture absorbing assembly 150 also serves as a reinforcing structure that maintains the integrity of the conductive bumps 11 and 12 under severe environmental conditions.
• the moisture absorbing assembly 150 may further serve to alter the fundamental resonant frequency of the package to improve its reliability in applications with high vibration tolerance requirements.
• the cap assembly 240 will now be described in connection with Fig.2. As discussed above, the cap assembly 240 may also be fabricated as a separate assembly before it is secured to the first seal assembly 130.
• the cap assembly includes a second cover member 241.
• An insulating spacer 243 is secured to the second cover member 241 using a suitable attaching structure 242, such as, for example, an adhesive.
• the attaching structure 242 may be any means of attaching spacer 243 to the second cover member 241 that both physically holds the parts together and forms a hermetic continuous boundary seal there between. This may be produced by frit scaling and/or adhesive sealing.
• the attaching structure 242 may include the sealing layers 130, 143, and 170, described above in connection with the embodiment of Fig. 1.
• the cap assembly 240 may further include a second seal assembly 244 which lies on the underside of spacer assembly 243.
• the second seal assembly 244 as a structure similar to the second seal assembly 143, described.
• the second seal assembly 244 is secured to the first seal assembly 130 using an intermediate seal assembly 170, as described.
• the packaging assembly 300 includes a first cover member 110.
• the packaging assembly 300 includes a cap assembly 310.
• the cap assembly 310 includes spacer assembly 311 that is attached to a second cover member 312 with a continuous boundary of an organic adhesive layer 313.
• the adhesive layer 313 may be a UV curable epoxy, or conventional epoxy or any other organic adhesive that forms a seal that strongly resists the transport of water or oxygen.
• the cap assembly 310 is attached to the first cover member 110 to and conductive patterns 111 and 112 through a continuous boundary of an organic adhesive layer 314.
• the adhesive layer 314 is similar to the adhesive layer 313.
• Packaging assembly 400 is depicted in Fig. 4.
• the packaging assembly 400 includes a first cover member 110, a first insulating member 120, a first seal assembly 130, a intermediate seal assembly 170, as described above in connection with the packaging assembly 100.
• a cap assembly 410 is molded or otherwise formed as a single unit.
• the cap assembly 140 may be formed of glass, ceramic, metal or other suitable material.
• a second seal assembly 420 is secured to the cap assembly 410.
• the second seal assembly 420 is similar to the second seal assembly 143, described above.
• an organic adhesive as previously described may be used in place of the above described seal assemblies.
• the second seal assembly 420 may be eliminated if cap assembly 420 is formed of a metal that is directly wetted by the intermediate and assembly 170.
• Packaging assembly 500 is depicted in Fig. 5. As described above in connection with packaging assembly 100, display chip device is secured to the first cover member 110. A sealing assembly 510 is placed along the entire perimeter of display chip device 10 forming a filet between the first cover member 110, conductive patterns 111 and 112 and display chip device 10.
• the sealing assembly 510 may be formed from an organic adhesive which may be a UV curable epoxy, or a conventional epoxy or any other organic adhesive that forms a seal that strongly resists the transport of water or oxygen. It is essential that the viscosity of material forming the sealing assembly
• An insulating assembly 610 is formed on the upper surface of conductive patterns 111 and optionally on the first cover member 110 between and around conductive patterns 111.
• the insulating assembly 610 preferably include an insulating material.
• the insulating material may be lithographically patterned sputtered quartz or CVD glass, screened and fired thick film insulator glass, shadow mask evaporated SiO, or other suitable patterned insulator materials.
• the packaging assembly 600 includes a sealing assembly 510, as described above.
• a barrier layer 620 is placed on a portion of the insulting assembly 610, on a portion of the first cover member 110, across the top portion of the display chip device 10, and on the entire outer surface sealing assembly 510.
• the barrier layer 620 serves as a barrier to the diffusion of water and oxygen from the outside of the package to the inside through material 30.
• the barrier layer 620 is preferably formed from metal.
• a second cover member or protective layer 630 which may be an organic film or other coating is deposited over the entire upper surface of the barrier layer 620.
• Protective layer 630 may be deposited by spraying, dipping, spinning, CVD or other technique provided that the portion of the first cover member 110 and the portion of conductive patterns 111 that extend beyond insulating assembly 610 toward the edge of the first cover member 110 are either uncoated by protective layer 630 or have had protective coating 630 selectively removed from those areas. Alternatively, layers
• 620 and 630 may be deposited such that they only cover a portion of the upper surface of display chip device 10 provided that at least the continuous peripheral portion of the upper surface of chip 10 is covered.
• Protective layer 630 is used to prevent mechanical or corrosive damage to barrier layer 620, which would negate the function of barrier layer 620.

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• Engineering & Computer Science (AREA)
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• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Electroluminescent Light Sources (AREA)
• Devices For Indicating Variable Information By Combining Individual Elements (AREA)

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• 1998
  • 1998-12-31 WO PCT/US1998/027884 patent/WO1999035681A1/en not_active Application Discontinuation
  • 1998-12-31 EP EP98966131A patent/EP1038312A1/de not_active Withdrawn

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