Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04Q—SELECTING
  • H04Q11/00—Selecting arrangements for multiplex systems
  • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
  • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
  • H04Q11/0478—Provisions for broadband connections
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5619—Network Node Interface, e.g. tandem connections, transit switching
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
  • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
  • H04L2012/5651—Priority, marking, classes
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/54—Store-and-forward switching systems 
  • H04L12/56—Packet switching systems
  • H04L12/5601—Transfer mode dependent, e.g. ATM
  • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
  • H04L2012/5679—Arbitration or scheduling

Definitions

• the present invention relates to techniques and devices for scheduling asynchronous transfer mode (ATM) traffic, for different bit rate services assigned to virtual circuit connections within a plurality of virtual path connections, for transmission over an ATM link.
• ATM asynchronous transfer mode
• analog voice telephone services utilize a complex network of voice traffic switches, lines and trunks to provide ubiquitous switched voice connectivity virtually throughout the world.
• the modern telephone network carries most voice traffic in digitized form, typically using time division multiplexing techniques.
• the switched voice network can carry some data traffic, using modems of ISDN interfaces.
• the telephone network cannot readily switch higher speed data traffic, therefore a variety of separate data networks evolved. Examples of such data networks include X.25, frame relay and SMDS.
• the construction, operation, maintenance and upgrading of such disparate networks for different services are increasingly complex and expensive, particularly as traffic demands continue to increase.
• ATM Asynchronous transfer mode
• the ATM standard defines a cell size of 53 bytes or octets.
• the first five bytes of each cell form a header, and the remaining 48 bytes represent payload data.
• the header of each cell includes a field for a virtual path identifier (VPI) and a Virtual circuit identifier (VCI), to identify the particular communication to which each cell relates.
• VPN virtual path identifier
• VCI Virtual circuit identifier
• ATM is intended to carry virtually any type of information that can be expressed in or converted to digital form, from voice telephone traffic, to real-time video, to high-speed file transfers, to faster than real-time video, etc.
• ATM based networks are eliminating the need for different networks to carry different types of traffic.
• transfer is asynchronous in the sense that the recurrence of cells that contain information from any particular sender is not necessarily periodic.
• Each device using the ATM network submits a cell for transfer when it has a cell to send, not when they have an assigned or available transmission time slot.
• the ATM cells ride in synchronous slots on a high-speed media, such as a SONET optical fiber.
• ATM allows any arbitrary information transfer rate up to the maximum supported by the ATM network, simply by transmitting cells more often as more bandwidth is needed.
• QoS quality of service
• real-time video transmission requires a high constant bit rate to maintain synchronism, whereas packet data communications do not.
• VCC virtual circuit connection
• devices currently available utilize only virtual circuit connection or VCC based routing.
• UNI user network interface
• CBR constant bit rate
• ABR available bit rate
• VPC virtual path connection
• CBR service takes precedence over ABR traffic.
• the interface transmits a cell for that circuit. If the circuit presents no data to send, the interface sends cells from the circuits assigned ABR service if there is such a circuit whose service time is due at this time.
• the various circuits are differentiated as different virtual circuit connections (VCCs) having different VCC identifiers, both internally in the interface and in the headers of the transmitted cells.
• VCCs virtual circuit connections
• the user network interface runs a VCC based scheduler, to schedule transmission of cells for the various services.
• the scheduler maintains a CBR table. This table includes a VCC identifier for each circuit subscribing to CBR service in the order that service is scheduled for the respective circuits. Constant bit rate service takes precedence over available bit rate service.
• a table pointer traverses the CBR table at the link cell rate.
• each CBR circuit receives a percentage of the CBR link bandwidth proportional to the number of listings for the circuit in the table divided by the total number of listings in the table. For example, if VCI appears in every other slot in the table (half the slots of the table), then the user network interface schedules an opportunity for that VCC to transmit a cell every other cell transmit time.
• the virtual circuit connection VCI has the opportunity to use half of the link bandwidth.
• the schedule reads a listing from the CBR table, it also reads a listing from the ABR table.
• Each listing in the ABR table comprises head and tail link list pointers. These link list pointers point to the beginning and end of a link list of VCC identifiers for circuits subscribing to available bit rate service.
• the scheduler moves the accessed link list of VCC identifiers to a work list. In this manner, the scheduler accumulates a work list of ABR circuit identifiers as the interface runs through cell times of the ATM link. Whenever a cell transmit opportunity is not used by a constant bit rate service, the scheduler ideally would go through the accumulated work list until it finds a virtual circuit having a cell to send and enables transmission of the cell from that circuit.
• the CBR table is static.
• the ABR table is dynamic. If the processing through the ABR work list enables an ABR service type circuit to actually transmit a cell, then the scheduler removes the served circuit VCC from the work list. This VC is put back on the ABR table, but at a specifically selected point further down the table. The selection of that point in the table effectively reschedules the service for the sequence of listed ABR circuits. The distance that the listing is moved down the table depends on the type of flow control algorithm in use.
• the prior art system assumed all traffic was within one virtual path, for example identified by a virtual path identifier (VPI) of 0.
• the ATM link may be viewed as a pipe, running from the interface to the next node of the ATM network.
• the CBR and ABR table approach provides constant bit rate service and available bit rate service, but the use of one VP or VPC for all such services limits the ability to provide such services to a large number of circuits through a single interface. All of the service is within the one pipe defined by the one VPC.
• the use of a single VPC limits the ability to segregate the bandwidth of the ATM pipe from the user network interface to the next node of the ATM network.
• the ATM pipe can carry cells from only a certain number of circuits and can support only so many CBR circuits. Also, the interface supports only the two types of services and cannot easily support those services in combination with other services, such as variable bit rate (VBR). Disclosure of the Invention
• the present invention solves the above discussed problem with the prior art by scheduling ATM cell transport over a link using both virtual path connections and virtual circuit connections.
• the hierarchical scheduler in accord with the invention facilitates CBR, VBR and ABR services, within logically separate virtual paths or pipes, carried over the same ATM link.
• the scheduler uses one static table for assigning cell transmit time slots to the virtual paths and for identifying virtual circuits that may use those slots for relatively high priority services, such as CBR and VBR.
• the scheduler uses and updates one or more dynamic tables for scheduling lower priority traffic, for example for ABR service.
• the present invention relates to a method of scheduling asynchronous transfer mode (ATM) cell traffic, for transmission over a link in a plurality of cell transmit times.
• ATM asynchronous transfer mode
• each virtual path connection may utilize bandwidth on the link.
• one virtual path connection is identified as having been assigned the respective cell transmit time as its cell transmit opportunity, from a line of the static scheduling table indexed by cell transmit time.
• Each virtual path connection supports high priority traffic, such as constant bit rate traffic or variable bit rate traffic, for a plurality of virtual circuit connections.
• the ATM processing device performing the scheduling also determines from the indexed line if there is a high priority service virtual circuit connection, from among those associated with the identified virtual path connection, that is assigned the respective cell transmit time. If the scheduling device identifies such a virtual circuit connection, then the scheduler provides the opportunity to transmit a cell for that high priority service via the virtual circuit on the link in the respective cell transmit time.
• the connection carries a transmitted cell over the link in the respective cell transmit time. If the service is a variable bit rate service, the scheduler checks whether the circuit is ready to send. If so, the scheduler enables transmission in this cell time.
• the ATM processing device performing the scheduling indexes a line of a dynamic scheduling table.
• the scheduler identifies at least one virtual circuit connection having available bit rate service.
• the scheduler preferably obtains a pointer from the line of the dynamic table.
• the scheduler uses the pointer to retrieve one of a number of link lists from memory.
• the link list identifies one or more virtual circuit connections having the ABR service.
• the indexing of the dynamic table associates the identified virtual circuit connection(s) with the respective cell transmit time.
• the preferred embodiment utilizes one dynamic table for each virtual path. For each cell transmit time, the scheduler uses the dynamic table for the virtual path indexed in the static table.
• the dynamic table points to link lists of available bit rate service type virtual circuit connections associated with the one virtual path connection.
• the ATM processing device performing the scheduling selects an ABR circuit identified in one of the link lists for transmission.
• the device accesses a link list
• the device adds one or more of the identified virtual circuit connection(s) to a work list.
• the scheduling device examines the work list. Specifically, the device accesses the work list to identify an available bit rate service type virtual circuit connection for which there is a cell to transmit, and the cell for that circuit is transmitted over the link in the respective cell transmit time.
• the present invention also encompasses ATM processing devices that incorporate elements for performing the scheduling operation described above.
• the invention encompasses an ATM processing device, including an ATM cell transmitter, a memory and a programmable cell transmission scheduler.
• the scheduler controls the scheduling of cells for transmission over a communication link.
• a static scheduling table is stored in memory, for use by the programmable cell transmission scheduler.
• the static scheduling table includes a plurality of lines, each of which contains an index identifying one of a plurality of virtual path connections that may utilize the link during a respective cell transmit time.
• a field in each line of the static scheduling table may contain an identifier of a virtual circuit connection having a high priority service (e.g., constant bit rate service).
• each line of this table also includes a field for an identifier of a virtual circuit connection having a somewhat lower priority service, e.g. variable bit rate service.
• the memory of the ATM device also stores link lists, each of which identifies one or more virtual circuit connections.
• the ATM device further comprises at least one dynamic table stored in memory. Each line of the dynamic table has a field containing a pointer. The pointer points to one of the virtual circuit connection link lists for one or more low priority services, e.g. connections having available bit rate service.
• FIGS. IA and IB together form a high level flow diagram of ATM cell transmission scheduling in accord with the present invention.
• FIG. 2 is a block diagram of a data communication system including and ATM segmentation and reassembly circuit, performing ATM cell transmission in accord with the present invention.
• Figure 3 is a high level block diagram of the ATM segmentation and reassembly circuit.
• FIG. 4 is a more detailed block diagram of the ATM segmentation and reassembly circuit.
• Figure 5 is an example of a first implementation of a scheduling table useful in the present invention.
• Figure 6 illustrates a static scheduling table used in a second embodiment of the invention.
• FIGs 7A to 7D depict simplified portions of dynamic scheduling tables used for scheduling ABR type ATM cell transmission in accord with the second embodiment of the present invention.
• Figure 8 is a process diagram useful in understanding work list operations for ABR service
• Figure 9 is a flow chart illustrating the process flow in accord with the second embodiment of the present invention.
• the present invention enables the scheduling of asynchronous transfer mode (ATM) cell traffic for transmission over a link.
• ATM transport devices operating in accord with the present invention incorporate a traffic scheduler which segregates traffic on the link into a plurality of virtual path connections, and within each virtual path, the scheduler segregates traffic into a plurality of virtual circuit connections.
• the scheduler utilizes one or more tables to assign traffic of a variety of types into respective cell transmit time slots.
• Figures 1 A and IB form a simplified flow chart illustration of the schedule processing of the present invention.
• the scheduler increments cell transmit time (step SI).
• a key feature of the present invention relates to use of multiple virtual path connections (VPCs).
• VPCs virtual path connections
• the scheduler For each respective cell transmit time, the scheduler therefore identifies one virtual path connection that is assigned to the cell transmit time (step S2).
• the division of the ATM link into separate virtual paths (VPs) using multiple virtual path identifiers (VPIs) and assigning time slots to the VPCs allows the division of traffic on the link into several logical paths or pipes.
• the overall (physical) link then can support CBR traffic and ABR traffic within each logical pipe.
• the new system also supports variable bit rate (VBR) traffic.
• VBR variable bit rate
• the scheduler supports high priority services, such as CBR service, for a number of virtual circuit connections (VCCs) within each virtual path connection (VPC).
• CBR service virtual circuit connections
• the scheduler determines if there is a high priority VCC, associated with the identified VPC, for which there is a cell to send (step S3). If there is no cell ready to send for this CBR, the opportunity is passed to low priority VCC associated with this VPC.
• VBR variable bit rate
• step S4 If there is a high priority cell to send, the scheduler registers the VCC identifier for that high priority circuit and sets an appropriate status bit (step S4), and processing flows to step S5. If there is no high priority circuit with a cell to send in the present transmit opportunity, then the schedule processing advances directly from step S3 to step S5. If steps S3, S4 identified a high priority VCC having a cell to transmit, then the scheduler will initiate transmission of the cell for that virtual circuit connection at the end of one cycle through the process flow (in step SI 6), as discussed more below.
• step S5 the scheduler accesses a link list.
• the link list is one associated with the VPC identified in step S2.
• the link list identifies one or more virtual circuit connections having available bit rate service (ABR) whose service time is due.
• ABR available bit rate service
• VPC virtual path connection
• VCCs virtual circuit connections
• the preferred embodiments utilize one or more tables to associate the ABR VCCs with their respective VPCs and with cell transmit time opportunities.
• the scheduler may transfer all of the VCCs from the one accessed link list to a work list, or the scheduler may check the status of the circuits on the link list and transfer only the VCC identifiers for those ABR circuits with a cell ready to send from the accessed link list to the work list (step S6). Over a series of cell transmit times, the scheduler will transfer individual VCC identifiers from a number of link lists associated with a number of VPCs to build up one or more work lists of ABR circuits awaiting an available slot in which to transmit a cell. Thus, during any cell transmit time for which the scheduler has no higher priority cell scheduled, it then fetches the ABR VCC from the head of the work list for the VPC.
• this is implemented through a check of the ready status for the high priority circuits (step S7) followed by work list processing (steps S8-S10).
• step S7 branches to step S 11.
• step S8 the scheduler checks the work list to set the ABR VCC from the head of the work list. If this VCC has a cell awaiting transmission, processing flows through step S9 to step S10, in which the scheduler registers the VCC identifier for that ABR service circuit and sets an appropriate status signal. If this VCC has no cell ready to transmit or the work list is empty, step S9 branches the process flow to bypass step S10.
• step SI 1 the scheduler determines which cell to send. If there is a high priority circuit for which there is a cell ready to send, processing branches to step S12 in which the scheduler loads the cell from the source to the ATM transmitter. If there is an ABR type circuit for which there is a cell ready to send, processing branches to step S13 in which the scheduler loads the cell from the particular ABR source to the ATM transmitter.
• step SI 4 the scheduler moves the identifier for the ABR type VCC granted the transmit opportunity from the work list. If a null cell is sent for this VCC, this VCC is not put back to the schedule table. Otherwise, this VCC is rescheduled to a new location for future processing, as will be discussed in more detail with regard to the preferred embodiments.
• step S15 the scheduler loads a null cell to the ATM transmitter.
• step SI 6 the scheduler causes the ATM transmitter to send the loaded cell.
• the scheduler loaded a cell for that CBR type VCC (SI 2).
• the ATM transmitter sends the cell over the VCC on the link having the high priority service in step SI 6.
• the scheduler loaded a cell from that ABR type VCC (S 13), and the ATM transmitter sends the ABR service cell over that VCC on the link in step S 16.
• the scheduler loaded a null cell (SI 5), and the transmitter sends the null cell over the link in step SI 6.
• the cells are transmitted on the identified virtual path connection (VPC) on the link.
• VPC virtual path connection
• step SI 7 After transmission, processing returns through step SI 7 to step SI, where the scheduler increments the cell transmit time.
• the scheduler will go through the process again, but in a typical sequence, the next pass through the scheduler process will identify a different VPC and a VCC within that VPC. In this manner, repeated flow through the process will allocate cell transmit time slots to a variety of high priority and available bit rate services within the different VPCs.
• the hierarchical scheduler therefore supports different types of traffic within each logical path or pipe identified as a VPC.
• the above-discussed operations are examples of typical operations.
• the traffic scheduling principles of the invention may facilitate other types of ABR processing. For example, if the scheduler selects a VCC from a link list only if the circuit has a cell to send, in a time slot in which there is no high priority service scheduled and the work list is otherwise empty, the scheduler can enable transmission over the circuit identified from the link list without moving the VCC to the work list.
• the ATM traffic scheduling of the present invention may apply in a variety of ATM processing devices, such as ATM edge devices and other ATM routers and/or switches.
• the preferred implementation of the present invention applies the scheduling principles in a segmentation and reassembly circuit, typically used in an ATM user network interface (UNI).
• UNI ATM user network interface
• FIG 2 illustrates a user network interface (UNI) 10 providing a two-way data communication connection between a local area network (LAN) 11 and a high speed ATM link 17.
• the ATM link 17 typically connects to a switch or router of an ATM network.
• the LAN 11 provides data communications between various data devices connected thereto.
• the LAN 11 connects to a plurality of PCs 13 and to one or more servers 15.
• the UNI 10 and the connection thereof through the LAN 11 enables the PCs 13 and/or the server 13 to send and receive data communications over assigned virtual circuits on the ATM link 17.
• the segmentation and reassembly circuit 23 assigns virtual channel connections (VCCs) to data communication services from the PCs 13 and the server 15 and schedules transmissions depending on the types of service and bandwidths allocated to each of those data devices.
• VCCs virtual channel connections
• the ATM segmentation and reassembly circuit controls the data flow between the cell based virtual circuits assigned on the ATM link and the packet based virtual circuits through the LAN 11 to the data devices 13, 15.
• the circuit 23 segments and adapts outgoing data for ATM transport and schedules transmission in assigned virtual paths and circuits.
• the circuit 23 inserts VPIs and VCIs in the cell headers to logically place cells in the virtual paths and circuits.
• the circuit 23 also reassembles payload data from ATM ells into packets for transport to the data devices.
• the circuit 23 performs all necessary address administration in both directions.
• the microprocessor 27 serves as the node control processor for the UNI 10, for example to administer service negotiation.
• the ATM segmentation and reassembly circuit 23 also connects to a memory 29, such as a static random access memory (SRAM).
• SRAM static random access memory
• the circuit 23 stores scheduling tables, link lists and work lists in the memory 29. Assembled outgoing cells containing segmented data and VPI VCI values are buffered and queued in the memory.
• the LAN 11 carries data communications in some standard type of packet data protocol, such as Ethernet.
• the packets include media access control layer addressing information, to facilitate two-way communication over the LAN.
• the UNI 21 includes a LAN interface 21 for physical connection to the LAN 11 and for conforming information going to and from the UNI 10 to the particular LAN protocol.
• the LAN interface provides a two-way MAC level connection or interface to the ATM segmentation and reassembly circuit 23.
• the link 17 carries ATM cells in some high speed transport format. For example, the link may be a DS3 communication channel on electrical cable or an OC-1 or OC-3 on optical fibers.
• the ATM segmentation and reassemble circuit 23 connects through its physical interface port to a link interface 25.
• the link interface 25 conforms the ATM cell information going to and from the UNI 10 to the signal type (electrical or optical) and the protocol (DS or SONET) of the link 17.
• the DS and OC protocols cited are examples only, and if other high speed protocol links are used, an appropriate interface 25 would couple the UNI to the particular link and perform the necessary interface of the UNI to the link.
• One example of a chip capable of serving as the circuit 23 is AToM4 manufactured by Digital Equipment Corporation and Toshiba Corporation.
• the ATM segmentation and reassemble circuit 23 adapts information from LAN packets for ATM cell transport.
• the circuit 23 also maps packet address information into virtual path and circuit identifiers, in order to transmit cells for particular devices or services in assigned virtual circuits over the ATM link l7.
• FIG. 3 is a high level functional block diagram of the ATM segmentation and reassembly circuit 23.
• the circuit 23 provides the functions required to implement a variety of high-performance ATM User Network Interfaces. This includes packet stream to circuit selection, ATM Adaptation Layer (AAL), segmentation and reassembly (SAR), and cyclic redundancy (CRC) generation and checking.
• the circuit 23 contains mechanisms to support traffic shaping, varieties of ATM flow control protocols, and Operations Administration and Maintenance (OAM) flows.
• the ATM segmentation and reassembly circuit 23 interfaces with a variety of physical layer chips by Utopia or specific interfaces to facilitate media interface connection to DS3, E3, and HSSI links .
• the circuit 21 receives packets from the LAN interface 21 or the like for transmission on the ATM link 17 via a byte-wide data interface with one parity bit (TxInData) that runs at 12.5 MHz or 25 MHz.
• the control interface (Txln Control) includes packet delineation and byte flow control. The flow control signal is used to hold off transmission of data during periods where no buffers are available for the data to be transmitted.
• the receive portion of the packet interface is also byte wide for data with one parity bit (RxOut Data), and runs at the same speed as the transmit interface. There is a separate control channel (RxOut Control), which indicates receive packet delineation and error status.
• the segmentation and reassembly circuit 23 connects to the actual link interface 25 through a physical link interface or port.
• the physical link interface consists of a byte-wide data path for both transmit (TxOut Data) and receive (Rxln Data). In all modes, the link interface is slaved from the link clock inputs. Speed matching FIFOs are used between clock boundaries. Byte transmission/reception to/from the link is controlled by either a gapped link clock or an overhead/valid indication signal on the control lines.
• the cell memory interface consists of a 64-bit data bus (Cell Memory Data), with two additional parity bits and a 20-bit address bus (Cell Memory Address). Write enable and output enable signals are provided separately.
• the preferred embodiment of the ATM segmentation and reassembly circuit 23 is capable of addressing up to 1 Meg word (8Mbytes) of memory.
• the external memory is used for storing ATM cells that are awaiting transmission or are being reassembled, records, traffic schedules and free buffer pools.
• the amount of memory required depends on the number of circuits being used in a particular application. Currently, 1 MB of memory is used to support 4096 circuits.
• the segmentation and reassembly circuit 23 connects to the microprocessor 27 through a node processor interface or port.
• the node processor interface uses a 16-bit data and 7-bit address configuration.
• This port uses a synchronous Motorola 68K style interface, running at 12.5 or 25 MHz. All of the chip control and status registers (CSRs) can be accessed directly through this interface.
• the external memory 29 also is accessed indirectly through this interface.
• the segmentation and reassembly circuit essentially comprises four processing engines, a segmentation engine 31 , a cell transmit engine
• the segmentation engine 31 receives packets from a transmit MAC interface 41.
• the segmentation engine 31 segments packets into either AAL3/4 or AAL5 cells according to the virtual circuit state that is set up for each packet.
• the segmentation engine 31 uses a region of the header to identify the particular ATM circuit that the cells should be queued on.
• Each ATM virtual circuit is identified with one of several virtual path connections (VPCs) and with a specific virtual circuit connection (VCC) within the particular VPC. Up to 4095 separate circuit queues are supported.
• the region of the header used is programmable and depends on the packet format, e.g., the format used on the LAN 11 in the example in Figure 2.
• the segmentation engine 31 supplies the cells to a memory controller and scheduler 43.
• the controller and scheduler 43 stores the cells resulting from the segmentation in external SRAM (memory 29) for transmission by the cell transmit engine 33.
• the transmit engine 33 includes a cell transmitter and scheduler 45 and transmit FIFO buffers 47 which connect to the transmit link portion 49 of the physical link interface port. Transmission of a cell segmented from a packet can occur while the rest of the packet is still being segmented and hence transmit "cut through" is supported.
• the cell transmit engine 33 services up to 4095 transmit queues for CBR, VBR, ABR and UBR traffic.
• CBR and VBR traffic is served according to a precomputed traffic schedule that is stored in external SRAM, using one or more schedule tables in accord with the invention.
• This schedule table(s) can be used for peak-rate traffic shaping on a per circuit basis.
• the manner in which this table is filled out can also allow prioritization of traffic and overbooking of bandwidth.
• the granularity of bandwidth assigned to circuits is programmable by appropriate programming ofthe table(s).
• a speed-matching FIFO 47 exists in the cell transmit engine 33 to account for the different clock speeds used for the core process (25 MHz) and the link process (0-25 MHz).
• the cells are simply output as a stream, e.g., for an STS-3c link.
• the byte stream output can be held off by either gapping the link clock or asserting the overhead indication signals.
• the reassembly engine 35 receives cells through a receive portion 51 of the physical link interface.
• This engine 35 includes a FIFO 53 and a reassembly section 55.
• the reassembly engine 35 receives cells in byte-wide format from the link.
• the FIFO 53 provides speed matching between the link clock domain (0-25 MHz) and the core process clock domain (25 MHz).
• Packet reassembly in section 55 begins by taking a cell from the FIFO 53 and looking up the receive circuit state that is stored in external SRAM (memory 29).
• the index to the receive circuit state table is based on individual lookups of the VPI field, the VCI field, and possibly, the MID field if AAL4 is being used. If the circuit lookup indicates that the cell should be accepted, the cell is written to a free cell buffer in external memory 29. If a packet reassembly is completed by the addition of this cell, the list of cells comprising the packet is moved to one of two packet lists, depending on priority bit setting for this circuit, and the circuit state is cleared. Otherwise, the circuit state is updated and written back to memory. Full AAL5 or AAL3/4 checking is done, including CRC checking, length field checking, segment type checking, and sequence number checking.
• the packet relay engine 37 comprises a packet dequeuer 57.
• the packet relay engine 37 services two prioritized queues each of which contains a list of cell buffers that represents reassembled packets.
• the reassembly engine places reassembled packets into this queue and indicates to the packet relay engine when a packet is ready for servicing.
• Each packet contains a pointer to the circuit that it was received on.
• the packet relay engine 37 provides the MAC destination address in the header of the reassembled packet.
• the packet header and the complete packet are passed to the MAC interface 37.
• the RxOut MAC interface 59 uses the MAC protocol to deliver packets. This protocol delineates the packets with start and end markers and it indicates the status of the packet, e.g., good or bad CRC. In the illustrated example ( Figure 2), the receive MAC interface 59 supplies the reassembled packet to the LAN interface 21 for transmission over the LAN 11 to the destination device 13 or 15.
• the scheduler associated with the cell transmitter 45 schedules a variety of different types of traffic on a hierarchical basis for a plurality of virtual paths within the ATM link. That scheduler implements a process similar to that of Figure 1 using one or more scheduling tables. Further discussions will concentrate on hierarchical scheduling using two implementations of the scheduling table(s).
• Figure 5 depicts a simplified example of a first table embodiment, i.e. a single scheduling table, used in the hierarchical scheduler.
• the scheduling table includes multiple lines indexed by cell transmit time.
• the first field in each line contains an identifier or index for one of the VPCs.
• the VPC index in a line effectively assigns the cell transmit time of that line to the indexed VPC.
• the next two fields in each line identify VCCs for different levels of service priority, and the succeeding two fields point to lists of additional VCCs having a different type or level of service.
• the VC or VCC identifiers used in this table may take the form of internal numbers or names arbitrarily assigned as the identifiers. In such a case, the segmentation and reassembly circuit 23 will translate those identifiers into actual ATM standard virtual circuit identifiers (VCIs) for insertion into the cells transmitted over the ATM link by the interface chip. Alternatively, the segmentation and reassembly chip 23 may utilize ATM VCIs as the internal virtual circuit identifiers.
• the next field in each line contains an identifier for a VCC having a high priority service.
• the high priority service may be a VBR service, but typically the high priority service is a CBR service.
• the next field in the table contains an identifier for a VCC having a low priority service.
• low priority means that the service is lower in priority than the service (if any) identified in the high priority field.
• the high priority service is CBR service
• the low priority service is VBR service.
• other services such as ABR traffic, actually have still lower priority than those identified in the 'low priority' field.
• the scheduler traverses the table as it increments the cell transmit time.
• the order of accessing the lines of the schedule table is a-b-c-d-e-f-g-h-a... which are stored in 'next serve time' in the field in each line.
• the scheduler accesses one line in the table to perform a variety of scheduling functions. If the scheduler finds a CBR VCC in the high priority column and it has a cell ready to transmit, the scheduler initiates transmission of a cell over that VCC. If not, the scheduler looks to the low-priority column. If the line identifies a VCC for low priority service, the scheduler checks the cell queue in memory 29 holds a cell that is ready for transmission over that VCC. If so, then the scheduler initiates transmission of a cell for that VCC. If not, the scheduler offers the cell transmit opportunity to VCCs having lower priority services.
• the scheduler For each cell transmit time, the scheduler also uses information from each line to schedule ABR services.
• each line specifies a pair of pointers for ABR service
• the head and tail pointers enable the scheduler to select a link list of VCCs associated with the VPC indexed in the particular line.
• the link list includes VCC identifiers for associated circuits carrying available bit rate service type traffic.
• the scheduler accesses the identified link list and appends VCCs from the link list to a work list.
• the scheduler may append all of the VCC identifiers from the link list to the work list. Alternatively, the scheduler may append VCC identifiers only for the circuits on the link list that have a cell ready to transmit.
• the scheduler uses a separate work list for the ABR traffic for each VPC.
• the scheduler will append the VCCs from a particular link list to the work list associated with the indexed VPC.
• the scheduler detects a cell transmit time for which there is no CBR or VBR service cell to transmit, the scheduler selects the VCC from the head of its work list.
• the scheduler accesses the first line in the table. Based on that line, the scheduler identifies VPI as the VPC assigned this time slot. The scheduler checks the high priority field of the first line. Different VPCs may use the same VCC identifiers, but each combination of a VPC identifier and a VCC identifier uniquely identifies one circuit.
• the high priority field of the line for time a includes a VCI identifier. This is a VCC associated with VPI having a high priority of service.
• the scheduler causes transmission of a cell for the VPI circuit VCI in the present time slot.
• the cell transmitted includes VPI and VCI values corresponding to VPI and VCI .
• the scheduler will also use head and tail pointers HI, TI to access a link list and move VCCs from that list to an ABR work list associated with VPI, as discussed above.
• each VPC has its identifier listed in one-fourth of the lines of the table.
• the scheduler will run through similar processes for VP2, VP3 and VPO for time slots b, c and d respectively.
• each VPC identifier appears in the line corresponding to every fourth cell transmit time, e.g. VPI appears in lines a and e.
• the scheduler accesses the corresponding line in the table. Based on that line, the scheduler identifies VPI as the VPC assigned this time slot.
• the scheduler checks the high priority field of the first line. In this example, there is no CBR service VCC listed.
• the scheduler next checks the low priority field.
• that field identifies VC2.
• VC2 is a different VCC associated with VPI.
• the low priority service preferably is a variable bit rate service.
• the scheduler checks to determine if this VC2 has a cell ready for transmission. If VC2 has a cell ready to transmit, the scheduler causes transmission of that cell in the time slot e.
• the header of the transmitted cell contains a VPI corresponding to VPI and a VCI corresponding to VC2.
• the scheduler will also use head and tail pointers H5, T5 to access a link list and move VCCs from that list to an ABR work list associated with VPI as in the earlier examples..
• the scheduler goes to the work list for VPI to find an ABR circuit with a cell to transmit. Assuming that the scheduler finds the VCC at the head of the work list with a cell that is ready to transmit, the scheduler causes transmission of a cell over that VCC in the time slot.
• the scheduler indexes the table at the cell rate of the link.
• the scheduler executes the hierarchical scheduling process for each line of the table.
• the execution order of all lines in the table is determined by the contents in the 'Next serve time' field of the table. For the example shown in Figure 5, the execution order is from time slot a to time slot b, from b to c, from c to d, from d to e, from e to f, from f to g, from g to h, from h back to a.
• the scheduler repeatedly cycles through the table to present transmit opportunities for specific circuits identified in the table and in the ABR work lists.
• the listing of the VCCs in the high and low priority columns of the tables allocate transmit opportunity and bandwidth to those services.
• Constant bit rate service is provided by entries in the high priority fields of the table, and the number of entries in those fields determines the bandwidth within the VPC allocated to the particular VCC for its CBR service.
• VCI for VPI appeared only in the high priority column. That VCC receives CBR service because the table guarantees that circuit an opportunity to transmit each time that cell transmit time a occurs.
• VCC2 for VPI appeared in the low priority column in a line which included no higher priority entry. That entry guarantees VC2 an opportunity to transmit each time that cell transmit time e occurs. If the VCC circuit uses the opportunity every time, it receives its maximum allowable cell transmission rate. However, at times this VCC may not have a cell that is ready to transmit. If the VCC does not transmit in that slot, its transmission rate decreases, and the transmit opportunity passes to the still lower priority ABR service VCCs.
• the table structure also supports a combination of CBR and VBR services for a given circuit, effectively to provide such a circuit with a variable rate service having a guaranteed minimum transmission rate. If a circuit, such as VC2 for VP3, has one or more entries in the high priority column, those entries guarantee a minimum bit rate, essentially as a CBR service (see the line for time slot g). The appearance of the same VCC in the low priority (e.g. in the line for cell time c) provides an added variable rate opportunity that the circuit need not always use.
• this ABR is then rescheduled to a future time slot belonging to its VPC.
• the scheduler inserts this VCC into a slot, which is down the table by the amount ⁇ t, and this slot must be associated with the same VPC. If the slot in the table indexed by ⁇ t does not belong to the same VPC, the scheduler will then keep on searching the table until the same VPC is found down the table. ' ⁇ t' is computed from this ABR current service cell rate.
• the second embodiment of the scheduling process uses separate tables for ABR traffic. Specifically, one static table indexes VPCs and identifies high and low priority VCCs for CBR and VBR traffic. There is a separate, dynamic ABR table associated with each respective VPC.
• the scheduler accesses a line of the static table for a given cell transmit time it first identifies a VPC assigned that slot for its use.
• the scheduler processes CBR and VBR traffic using VCC identifiers from the indexed line of the static table.
• the scheduler also access a dynamic ABR table for the indexed VPC to retrieve a link list and append that list to a work list associated with the VPC.
• Moving the pointers for that list down the respective ABR table reschedules service for a specific link list of VCCs by an appropriate number of lines. It should be noted, that with the second implementation, a reallocation of bandwidth between VPCs requires modification of the number of lines each VPC has in the static table. However, the ABR tables require no modification.
• Figure 6 illustrates one example of a static table
• Figures 7 A to 7D illustrate simplified portions of the dynamic tables, in accord with this second embodiment
• Figure 8 illustrates process flow for an ABR work list, in the second embodiment.
• the static scheduling table includes multiple lines indexed by cell transmit time.
• the scheduler traverses the static table at the cell slot time rate of the ATM link, i.e. the pointer for this table moves to the next line each time that the scheduler increments the cell transmit time.
• Each line of the table corresponds to one cell transmit time slot. Note that the 'next serve time' field does not exist any more.
• the scheduler traverses the static table by simply incrementing the cell time pointer.
• the first field in each line contains an identifier or index for one of the VPCs.
• the VPC index in a line effectively assigns the cell transmit time of that line to the indexed VPC.
• there are four virtual path connections (VPCs) and the static table includes virtual paths indexes VPI, VP2, VP3 and VPO for those virtual paths.
• Each row in the table represents an opportunity for transmission of a cell for the indexed VPC.
• each VPC receives a transmit opportunity every fourth time slot.
• each VPC may use up to 25% of the link bandwidth.
• the next field in each line contains an identifier for a VCC having a high priority service.
• the high priority service may be a VBR service, but again preferably relates to a CBR service.
• the next field in the table contains an identifier for a VCC having a low priority service.
• the term 'low priority' only means that the service is lower in priority than the service (if any) identified in the high priority field. Again, other services, such as ABR traffic, actually have lower priority than those identified in the 'low priority' field.
• the scheduler processes the high and low priority entries in essentially the same manner as in the earlier embodiment.
• the scheduler first presents the send opportunity to the VCC (if any) identified in the high priority field.
• High priority entries in the static table typically are used for CBR services.
• the high priority field were used for some service other than CBR, e.g. VBR, then the scheduler would determine if there is a cell buffered in the memory awaiting transmission over the high priority VCC.
• the high priority processing often does not cause scheduling of transmission in the respective cell time slot, typically because there is no VCC listed in the high priority field (for CBR), or possibly because a VCC in that field has no cell ready for transmission on that circuit.
• the scheduler passes the cell transmit opportunity to the VCC (if any) identified in the low priority field.
• the low priority entries typically are used for variable bit rate services.
• Each cell time that the scheduler hits a VCC for a VBR service in the low priority field of a line the scheduler offers the cell transmit opportunity to that specific VCC. If the scheduler determines that the identified VCC has a cell buffered in memory and ready to send at the present cell transmit time, then the scheduler will initiate transmission of the cell for that VCC. If not, then the scheduler looks to circuits having still lower priority service, such as available bit rate service, to identify a circuit and a cell to transmit.
• the scheduler actually provides a variable bit rate service with a guaranteed minimum bandwidth. If the scheduler finds the VCC in the high-priority field in one line of the table, the scheduler schedules the cell transmission for that VCC during each cell transmit time that indexes that line of the static table, just as if this were a CBR service.
• the number of lines in the table which include the VCC identifier in the high priority field, establishes the CBR-like minimum bandwidth. Appearances of the VCC identifier in the low priority field of a number of lines provides additional bandwidth in the form of a variable bit rate portion of the service for the particular VCC.
• the scheduler traverses each dynamic ABR table at the cell rate for the associated VPC. That is to say that the scheduler reads the next line of the ABR table, for a particular VPC, each time that the scheduler reads the index for that VPC from a line of the static table. As such, the speed of the movement of the pointer associated with each ABR is scaled as a function of the percentage of bandwidth or cell rate allocated to the respective VPC.
• the scheduler maintains a separate dynamic table for ABR services for each VPC that the scheduler supports. At any given time, each ABR VCC appears once and only once in a link list pointed to in the ABR table and the work list for that VPC.
• the bandwidth of an ABR VCC is represented by the ' ⁇ t', which is determined by the current cell rate of this VCC.
• the VCC can only transmit when a cell time slot is available for ABR transmission and the particular VCC identifier is at the top of the work list.
• Each time that an ABR VCC is presented an opportunity to transmit it is removed from the top of the work list by the scheduler and moved down the ABR table to a new location, if this time this VCC sends a data cell, not a null cell.
• the new distance down the table to the new location determines the time delay until the next retrieval and placement of the VCC on the work list and thus the next opportunity for this ABR VCC to send a cell.
• each ABR table has its own current pointer.
• the number of lines is the number of cell times assigned to the associated VPC in the static table.
• the static table shows assignment of times a and e to VPI .
• the dynamic ABR table for VPI ( Figure 7A) therefore has lines corresponding to a and e.
• Each line of an ABR table includes head and tail pointers H, T.
• the pointers identify a link list of VCCs associated with the particular VPC.
• Figure 8 shows the flow of the link list and work list processing.
• the scheduler reads HI , TI from the ABR table for VPI.
• the scheduler uses those pointers to retrieve a list of ABR VCCs whose service times are due at this time slot.
• the retrieved list contains identifiers for VC4, VC5 and VC7 associated with VPI.
• the scheduler appends those VCC identifiers to the work list.
• VC6 and VC8 are presently in the work list for VPI and VP6 is at the top (head) of the work list.
• the scheduler appends the new link list to the bottom of that work list.
• the scheduler picks up the VCC from the head (top) of the work list for VPI to serve.
• VC6 is picked to serve.
• the scheduler could go through the work list and find the first VCC that has a cell ready to send. But in reality, this design is not feasible for real-time processing.
• only the VCC at the top or head of the work list is examined. If the VCC picked has no cell to send, a null cell is sent instead, and this VCC will not be rescheduled to the dynamic table. Assume for this example that VC6 has a cell ready to send.
• the scheduler initiates transmission for the cell for that circuit and reschedules service for VC6.
• VC6 is either appended to the tail or added at the head of the linked list in the future time slot.
• the precise placement in the dynamic table depends on the applicable rescheduling algorithm.
• moving the pointers for an ABR link list down the ABR table by some distance ⁇ D reschedules service for the VCCs on that link list.
• the scheduler traverses the ABR table for a particular VPC at a fraction of the cell rate corresponding to the fraction of the link rate allocated to that VPC.
• the rescheduling therefore also must be scaled to the appropriate percentage of bandwidth or link rate allocated to the VPC.
• that distance ⁇ D equals the percentage bandwidth for the associated VPC multiplied by the reschedule time ( ⁇ T) for this ABR VCC.
• the reschedule time ( ⁇ T) equals the link rate divided by the allowed cell rate (ACR) for the ABR service to the particular VCC.
• the ACR value varies dynamically depending on traffic.
• the second embodiment greatly simplifies modifications of the schedule table.
• the scheduler stores two copies of the scheduling table ( Figure 5) or two copies of the static table ( Figure 6). One copy of the table is active, and the other is not.
• the microprocessor modifies the inactive copy of the table and transfers and changes the active/inactive status of the two tables.
• Figures 6 and 7 the dynamic tables need not be changed. It may be helpful to consider some examples on this point.
• tear-down or set-up of a real-time connection requires modification of the static schedule table.
• One control bit in a control and status register indicates which of the two static tables currently is in use.
• the microprocessor negotiates service with the appropriate data device 13 or 15 to define the circuit to be set up or torn down, and modifies the inactive static table to reflect this change. After completion of modification of this table, the microprocessor flips the control bit to activate usage of the new static table and to deactivate the other table.
• the current time pointer reaches the end of the old table and wraps around to the cell time for the top of the table, the base of the new static table is copied to the current time pointer, and the scheduler begins using the new static table.
• To set up or tear down a non-real time connection initiates a treatment of the circuit by modifying the rescheduling process in the appropriate dynamic, ABR table.
• the microprocessor modifies a status register associated with the circuit.
• the pointer pointing to the circuit is added to the work list for the appropriate VPC.
• the status register for the circuit is changed to inactive. After the next service opportunity is offered to the circuit, the scheduler will not reschedule service for that circuit in the ABR table.
• the number of appearances of a VPC identifier in the VP index of the static table determines the bandwidth allocation to the VPC.
• the microprocessor changes the inactive copy of the static table to include the VPC in the appropriate number of lines for the new level of bandwidth and then activates the modified copy of the table in the manner outlined above.
• the transmit opportunity passes down to one or more lower level service circuits.
• the segmentation and reassembly circuit supports a number of other types of flow control, such as quantum flow control.
• Quantum flow control (QFC) processing maintains a 'credit' for each VCC subscribing to the service.
• the scheduler For each VPC, the scheduler maintains a separate queue of VCCs for QFC based services. The scheduler identifies the VPC from the VP index in the static table and performs its processing for CBR, VBR and ABR, as discussed earlier. If the VPC assigned to a particular cell time has no cell ready to send for any VCC having those services, the scheduler looks to a queue of VCCs for QFC, associated with the currently identified VP, to fetch the VCC at the head of the queue.
• QFC Quantum flow control
• the scheduler When a QFC opportunity to transmit arises with respect to one VPC, the scheduler initiates transmission of the cell for that VCC. After transmission, if the VCC has more cells to send and it has more credits, it is appended to the tail of the QFC list for associated VPCs. Otherwise, it is simply removed from the QFC list. Next time, when it has traffic coming in and it also has credit updated, this VCC is appended to the tail of the QFC list. In this manner, all VCCs in a QFC list have both credits and a cell to send. When a transmission opportunity comes, all VCCs are ready to send a cell. To ensure detailed understanding, it may be helpful to go through a specific process flow, with emphasis on the processing of the second embodiment of the scheduling tables.
• FIG 9 is a flow chart illustrating this scheduling process.
• the scheduler indexes the cell transmit time (Si l l) and accesses the line in the static table corresponding to the indexed cell time. From the first field in the line of the static table for that time slot, the scheduler identifies the VPC assigned that time slot. The scheduler next checks the high priority field of that line (SI 12) and determines if there is a VCC listed (SI 13). If there is a VCC listed in that field and this VCC has a cell ready to send, the identified VCC has a CBR service allocated to use of that time slot. Under these circumstances, the scheduler sets a bit indicating CBR ready and assigns this cell transmit slot to the identified CBR VCC (SI 14).
• the scheduler next accesses the low priority field in the table (SI 14).
• the low priority field is used to identify VCCs for variable bit rate services. In any given line of the table, there may or may not be a low priority entry. If there is an entry in this field, the scheduler checks the circuit identified to determine if that circuit has a cell to send (S 115). Under these circumstances, the scheduler sets a bit indicating VBR ready and assigns this cell transmit slot to the identified VBR VCC (SI 16). If there is no VCC listed in the low priority field or if a VCC is listed but has no cell to send, then the scheduler will not set the ready bit for ABR transmission.
• the scheduler next reads the head and tail pointers from the indexed line of the ABR table for that VPC (SI 17).
• the head and tail pointers point to a link list of VCCs having ABR service.
• the scheduler retrieves the link list and may move one or more of the VCCs contained in the particular link list to the work list for the currently identified VPC (S 118).
• the scheduler may check to determine which circuits on the link list have a cell ready to transmit and transfer the VCC identifiers to the work list only for those circuits (if any) that have a cell to transmit. For simplicity of discussion here, assume that the scheduler appends all of each newly accessed link list of VCCs to the bottom of the work list as in the example of Figure 8.
• the scheduler now checks the ready status (S 119). If either the CBR ready bit or the VBR ready bit is set, the scheduler skips forward (to step SI 30), without performing any processing on the ABR work list for the indexed VPC. However, if neither the CBR ready bit nor the VBR ready bit is set, the scheduler looks to the VCC at the head of the work list.
• the scheduler checks to determine if the first VCC in this list has a cell ready to transmit. If the first VCC in the work list has a cell to transmit, the scheduler sets a bit indicating ABR ready, assigns this cell transmit slot to the identified ABR VCC and removes the VCC from the work list. If the first VCC identified on the work list does not have a cell ready to transmit, the scheduler removes the VCC from the work list, but it does not set the ABR-ready bit (SI 22) and SI 22 is skipped.
• SI 22 ABR-ready bit
• This process continues until the scheduler identifies an ABR VCC from the work list with a cell to transmit or until the scheduler completes traversal of the ABR work list for the indexed VPC without identifying a VCC that is ready to transmit (S121). If the scheduler finds a VCC having ABR service on this list with a cell to transmit, the scheduler sets the ABR-ready bit and assigns the slot to that VCC (S122). If the scheduler finds no VCC on the work list with a cell to send, the scheduler skips step SI 22.
• the scheduler reaches step SI 30 either upon recognition of a ready status set for CBR or VBR (from S 119) or upon completion of the ABR work list processing for the indexed VPC (from S121 or S122). At this point, the scheduler again checks ready status. If a ready bit is set for CBR, VBR or ABR, the scheduler jumps forward to its transmit process in step S200 and initiates transmission of the appropriate cell.
• the scheduler next considers QFC traffic for the indexed VPC (S131, SI 32). The scheduler checks if the QFC list for the indexed VPC is empty (S 131 , S 132) . If the QFC list is not empty, the scheduler initiates transmission of a cell for the VCC at the head of the list, and sets a bit indicating QFC ready (SI 33). The scheduler jumps forward to it's transmit process in step S200 and initiates transmission of the appropriate cell.
• step SI 32 the scheduler has found no VCC on the QFC queue, the scheduler skips step SI 33.
• the scheduler may go through tables and/or work lists for other types of traffic associated with the indexed VPC. For purposes of the present discussion, it is assumed that the QFC traffic is the lowest level service in the hierarchy associated with that VPC.
• the virtual path identified as VPO has special transmit privileges. It can transmit CBR, VBR and ABR traffic as scheduled by the tables and work list, in the same manner as the other VPCs. However, VPO may also transmit ABR or QFC traffic in cell transmit time slots designated for other VPCs, any time that the VPC identified in the VP index field of the static schedule table does not have a cell ready to transmit. In the illustrated example, it is assumed for discussion that the indexed VPC was for a connection other than VPO. After going through all of the processes for the indexed VPC (CBR, ABR and QFC in the present example), the scheduler offers the cell transmit opportunity to ABR traffic associated with VPO.
• CBR, ABR and QFC in the present example
• the scheduler checks the ABR work list (SI 34, SI 35) for VPO in the same manner as for other VPCs. If the VCC at the head of the ABR work list for VPO has a cell ready to transmit, the scheduler sets the ABR- ready bit during processing for VPO, the scheduler advances its processing to the transmission operation (S200) and sends the cell over the identified VCC for VPO.
• SI 34, SI 35 ABR work list
• the scheduler goes to the QFC queue for VPO (at SI 37 and SI 38). If the QFC queue for VPO is not empty, the scheduler sets the bit indicating QFC ready (SI 39), and proceeds to the transmission operations for the VCC at the top of the QFC list (S200).
• the scheduler may go to a work list or queue for another type of traffic, such as flow master or unspecified bit rate (UBR) (SI 40, S141). If the scheduler finds a UBR VCC ready for cell transmission in the appropriate list for VPO, the scheduler updates that work list. If the VCC was selected from an ABR list, the scheduler removes the pointer pointing to that VCC, that is the VCC itself, from the top of the work list and moves it down the ABR table for the particular VPC, to reschedule service for that VCC.
• UBR unspecified bit rate
• the scheduler initiates transmission of a null cell (SI 43).
• step 200 if the scheduler set any of the ready bits, the scheduler uses the appropriate identification for the VCC that caused the setting of the particular ready bit and initiates transmission of the cell for that VCC.
• the cell transmitted includes a VPI corresponding to the indexed VPC and a VCI corresponding to the identified VCC, to logically place the transmitted cell in the virtual path and in the virtual circuit within that path.
• the scheduler if the scheduler set the CBR-ready bit, the scheduler initiates transmission of the cell for the VCC identified as the CBR service VCC for this cell transmit time in the high priority field of the indexed line of the static table for the indexed VPC.
• the scheduler initiates transmission of the cell for the VCC identified as the ABR service VCC for this cell transmit time in the low priority field of the indexed line of the static table for the indexed VPC. If the scheduler set the ABR-ready bit during processing of the ABR work list for the indexed VPC, then the scheduler initiates transmission of the cell for the VCC from that list. If the scheduler set the QFC-ready bit during processing of the QFC queue for the indexed VPC, then the scheduler initiates transmission of the cell for the VCC from that list. If the scheduler set the ABR-ready bit during processing of the ABR work list for VPO, then the scheduler initiates transmission of the cell for the VCC from that list.
• the scheduler If the scheduler set the QFC-ready bit during processing of the QFC queue for VPO, then the scheduler initiates transmission of the cell for the VCC from that list. If the scheduler set the UBR-ready bit during UBR processing for VPO, then the scheduler initiates transmission of the cell for the VCC having the UBR service. If the cell transmission was for a VCC from one of the ABR or QFC lists, the scheduler updates that list. If the VCC was selected from an ABR list, the scheduler removes the link list containing that VCC from the particular work list and moves the head and tail pointers down the ABR table for the particular VPC, to reschedule service for that VCC.
• the scheduler similarly removes pointers and reschedules service for any link lists passed over in the work list processing because there were no cells ready to transmit for the identified circuits.
• the distance down the ABR table that the scheduler moves the pointers for each link list depends on the scheduling algorithm, traffic and/or the level of ABR service provided to the particular VCC. If the VCC was selected from a QFC list, then the scheduler moves the VCC down that queue and deducts one transmission from the credit assigned to the VCC. Periodically, the scheduler refreshes QFC credit for each VCC.
• the scheduler increments the cell transmit time (Si l l) and begins the scheduling process again.
• the scheduler will read the next line in the static table and begin processing for the VPC identified in that next line.
• the current pointer for the ABR table for that VPC also increments to the next line.
• VCCs identified in such a bottom-end process would receive service only after all CBR and VBR service checks for the indexed VPC and after offering the transmit opportunity to VCCs on the ABR work lists and QFC work lists for both the indexed VPC and VPO.
• Each CBR or VBR VCC has a 'ready bit' to indicate if the circuit has data cells ready. This 'ready bit' could be kept on external memory (e.g. memory 29), but preferably it is kept on the scheduler chip.
• the scheduler sets the 'ready bit' for that VCC to one. Every time a cell of a CBR or VBR VCC is transmitted, this VCCs 'ready bit' is cleared to zero.
• Each VP has a work list for its ABR VCCs.
• Each ABR VCC appears once and only once in either the work list or one of the linked lists identified in the ABR schedule table, if this VCC has a cell to send.
• cells for an ABR VCC are ready to send, if this VCC is not in any list, neither the work list nor a linked list, this VCC is appended to the tail of its VPCs work list. Otherwise, nothing happens.
• a cell of an ABR VC is transmitted, if this VCC still has cells to send, its service then is rescheduled to the future time. To do so, the VCC is put into a linked list whose head and tail pointer are in the future time slot in the ABR table. If this VCC has nothing more to send, it is not put into any list.
• the scheduler always checks the high priority VCC column in the static table first. If there is a VCC scheduled in the high priority column and this VCC has a cell to send, indicated by 'ready bit' for this circuit, the cell transmission time is given to this high priority VCC. Otherwise, the transmission opportunity is passed to the low priority column. For example, if the cell time pointer is pointing to cell time A, the static table ( Figure 6) lists VCI in the high priority column and VC4 in the low priority column. If the 'ready bit' for VCI is set, meaning that there is a cell ready for transmission, VCI is served. If 'ready bit' for VCI is not set, the transmission opportunity passes to VC4 in the same row.
• the scheduler checks the VCC in the low priority column. If there is a VCC in the low priority column and the 'ready bit' for that VCC is set, a cell is transmitted for that VCC. Otherwise, an ABR linked list from the ABR table for this VPC is checked. For example, if the cell time pointer is pointing to cell time B and VC3 has its 'ready bit' set, a cell for VC3 is sent.
• the ABR schedule table for VP2 is checked. At any cell time slot, the linked list in the current served VP's ABR table pointed by its current pointer is appended to this VP's work list. If there is no service request from either the high priority VCC or the low priority VCC from the static table, the VCC in the head of this VP's work list is served. The current pointer of the ABR table increments.
• the current served VP is VP2.
• the current pointer p2 is pointing to the linked list with head and ail H6 and T6, respectively.
• This linked list is appended to the work list of VP2.
• the rescheduled VCC could be inserted to the head of the linked list in the future time slot or the tail of that list.
• the current pointer p2 proceeds to the next line containing the linked list with head and tail H9 and T9, respectively. When the current pointer p2 reaches the end of this ABR table, it goes back to the beginning of the table.

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• 1998
  • 1998-11-17 AU AU15272/99A patent/AU732962B2/en not_active Ceased
  • 1998-11-17 CA CA002308350A patent/CA2308350A1/en not_active Abandoned
  • 1998-11-17 WO PCT/US1998/024541 patent/WO1999026378A2/en not_active Application Discontinuation
  • 1998-11-17 EP EP98959484A patent/EP1036451A2/de not_active Withdrawn

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