EP1033812B1 - Structure de suréchantillonnage ayant une réponse en fréquence du type sinc - Google Patents

Structure de suréchantillonnage ayant une réponse en fréquence du type sinc Download PDF

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Publication number
EP1033812B1
EP1033812B1 EP19990830112 EP99830112A EP1033812B1 EP 1033812 B1 EP1033812 B1 EP 1033812B1 EP 19990830112 EP19990830112 EP 19990830112 EP 99830112 A EP99830112 A EP 99830112A EP 1033812 B1 EP1033812 B1 EP 1033812B1
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EP
European Patent Office
Prior art keywords
bits
chain
derivator
derivators
integrator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19990830112
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German (de)
English (en)
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EP1033812A1 (fr
Inventor
Simone Ferri
Luca Molinari
Marco Bianchessi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
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STMicroelectronics SRL
SGS Thomson Microelectronics SRL
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Priority to EP19990830112 priority Critical patent/EP1033812B1/fr
Priority to DE69926601T priority patent/DE69926601D1/de
Publication of EP1033812A1 publication Critical patent/EP1033812A1/fr
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/0671—Cascaded integrator-comb [CIC] filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H03M3/508—Details relating to the interpolation process

Definitions

  • the oversampling operation is commonly effected by inserting N null samples between two successive samples of the input signal ( N th order oversampling), as depicted in Fig. 1.
  • the requirements of the filtering operation relate to the attenuation of the replicas. This attenuation should be as strong as possible, without adversely affecting the constancy of the frequency response of the filter in the signal band (ideally the gain variation of the filter throughout the signal band should be null). The more the above reported ideal conditions are complied with, the more the filter is considered "accurate".
  • the interpolators that are currently used for this purpose are complete FIR filters (often of the half-band type), linear interpolators and sample&hold structures.
  • FIR filters are filters with their own coefficients and require the use of RAM cells, ROM, adders and, often, multipliers.
  • the results obtained in terms of attenuation and precision of the frequency response are excellent, though the occupation of silicon area may become relatively large.
  • linear interpolators and “sample&hold” are much simpler to realize and, for the same oversampling order, occupy a smaller silicon area than FIR. This has a price in terms of a lesser attenuation of the spectrum replicas as well as of an undesired attenuation of the base band signal.
  • the US patent No. 5,835,390 discloses a digital filter for achieving substantial attenuation of aliasing or imaging bands of a signal to be filtered.
  • the purpose of the present invention is to provide an architecture of oversampling, filtering and reconstructing of a digital signal for any order of oversampling fulfilling the above mentioned requisites.
  • the structure of the present invention consists of a chain of derivators and integrators separated by a sampler, which holds the information.
  • the architecture of the invention presents an impulse response of limited duration and amplitude. Thanks to the use of a sample&hold stage rather than a zero insertion technique it is possible to realize the structure with a sinc k type transfer function, that is of a k order, by employing a k - 1 number of derivators and an equal number of integrators.
  • the effect of the derivators is to perform a low frequency filtering, while retaining in the output signal the necessary information to describe the filtered data.
  • the bit growth for the derivation part of the input signal occurs on a bit per stage basis by performing a subtraction at the output of each derivator stage such as to bring to a maximum growth of a single bit.
  • the digital signal is amplified by an N k factor (where N represents the clock frequency), which is equivalent to an increment of k*log2 (N) bits.
  • the integrators have a divergent gain at low frequencies and present limited and quantifiable output values.
  • the overflow may be averted and so the errors that may occur therefrom.
  • sample&hold stage broadens the band and effects a first filtering action of the spectrum replicas and a first reconditioning of the signal in base band. These operations are then repeated k-1 times by the integrator stages of the second chain that follows the sample&hold stage causing a filtering of the desired frequency response as final result.
  • the oversampling architecture of the invention also comprises auxiliary by-pass means, for the exceptional case for example in presence of metastability events, the maximum stage dynamics being exceeded, such as to provide for a momentary by-pass of the oversampling architecture of the invention and for the reset of all the stages.
  • G indicates the quantity log2(N) that may be defined as the growth or gain of interpolation, as it depends only on the oversampling factor N .
  • B is the number of bits of the input signal.
  • the operating frequency 1 / T and T / N (where T is the clock period) of the different blocks is indicated in the illustrations.
  • the integrators function at a frequency N times higher than that of the derivators and the task of the sample&hold block is to retain the input datum for N clock pulses.
  • the whole structure presents an impulse response of limited duration and amplitude.
  • the growth of the number of bits of the derivation portion of the circuit occurs on a bit per stage basis, in fact at the output of each derivator a subtraction is performed and this type of operation may bring to the maximum growth of one bit.
  • the net effect of the derivators is that of performing a low frequency filtering, ensuring retention in the output signal of the information required for describing the filtered data.
  • the signal between the input and the output is amplified by an N k factor (equal to H(0) ) equivalent to an increment of k * log2 (N) bits.
  • the new input-to-output gain has a maximum value of N k-1 (equal to H1(0) ) that in terms of increment of the number of bits is equivalent to (k-1)*G additional bits, thus from the N + 1 bits input to the second derivator we arrive at B + 1 +( k -1)* G bits output from the second last integrator.
  • the procedure is that of referring to the derivator associated to it and of incrementing the number of bits of the latter by an amount equal to (k-i) * G; where i is the position of the derivator (equal to 1 for the first, k-1 for the last): the whole number of bits output by any of the integrators of the chain is: (k-i) * G + B + i .
  • An advantage of the structure is that the integrators, having a divergent gain at low frequencies, present limited output values, quantifiable with the relationships described above. By suitably designing the integrators with these specifications, overflow may be avoided and so the errors that would derive from it.
  • the sample&hold stage broadens the band, performs a first filtering of the replicas of the spectrum of the signal and a first reconditioning of the signal in the base band. These two operations are repeated k-1 times by the integrators of the second chain and the final result is an effective filtering with a filter having a frequency response equal to the H(f) .
  • Fig. 4 illustrates the frequency response of a third order filter made according to the invention for oversampling from 44100*4Hz to 44100*128Hz.
  • an additional bit identifiable as "error bit”, may be purposely inserted in the position that precedes the sign bit, in each integrator.
  • the error bit of a stage is not passed to the following stage because it is not relevant to the processing but it only constitutes an updatable flag.
  • the "error bit" reveals this anomaly and commands the reset of the data stored in the filter.
  • the filter's output is no longer valid and thus the filter structure is by-passed and the input datum is reproduced on the output, multiplied by N k in order to bring back the output dynamics to the same number of bits of the correct operation.
  • the by-pass is effected along the parallel signal path through the multiplier stage and the multiplexer.
  • the reset and the multiplexer being controlled through a logic OR of the error bits, as shown in Fig. 5.
  • the by-pass condition is momentary, lasting a time equal to T*(k / N + k), which corresponds to the minimum time necessary for loading the data in the filter.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Claims (1)

  1. Architecture de suréchantillonnage pour interpoler, filtrer et reconstituer un signal numérique comprenant une première chaíne de dérivateurs recevant à une entrée d'un premier dérivateur de la chaíne le signal numérique qui est constitué d'un nombre k-1 de dérivateurs en cascade fonctionnant à une certaine fréquence d'horloge (1/T), le premier dérivateur ayant un certain nombre de bits (B) et chaque dérivateur suivant ayant un nombre de bits incrémenté d'une unité par rapport au nombre de bits du dérivateur précédant dans la chaíne ; une seconde chaíne du même nombre k-1 d'intégrateurs en cascade fonctionnant à une fréquence d'horloge (N/T) N fois supérieure à la fréquence d'horloge (1/T) desdits dérivateurs, le dernier intégrateur de la chaíne ayant un nombre de bits égal au nombre de bits (B) du premier dérivateur incrémenté d'un facteur équivalent à l'ordre (k) du filtre multiplié par le gain d'interpolation (G), et chaque intégrateur précédent ayant un nombre de bits décrémenté d'une quantité égale au gain d'interpolation (G) par rapport au nombre de bits de l'intégrateur suivant dans la chaíne ; un circuit d'échantillonnage ayant une entrée couplée à la sortie du dernier dérivateur de la première chaíne et une sortie couplée à l'entrée du premier intégrateur de la seconde chaíne, le dernier intégrateur de la seconde chaíne fournissant le signal suréchantillonné, filtré et reconstitué ;
       caractérisé en ce qu'il comprend des moyens dans chaque intégrateur dans la seconde chaíne contenant un bit d'erreur couplé aux entrées respectives d'une porte logique OU commandant la remise à zéro de tous les dérivateurs et intégrateurs quand l'un des bits d'erreur prend une certaine valeur logique et effectuant simultanément une dérivation momentanée de l'architecture selon un trajet de signal parallèle aux chaínes et comprenant un multiplieur du signal d'entrée par N* et un multiplexeur de sortie (MUX).
EP19990830112 1999-03-03 1999-03-03 Structure de suréchantillonnage ayant une réponse en fréquence du type sinc Expired - Lifetime EP1033812B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP19990830112 EP1033812B1 (fr) 1999-03-03 1999-03-03 Structure de suréchantillonnage ayant une réponse en fréquence du type sinc
DE69926601T DE69926601D1 (de) 1999-03-03 1999-03-03 Struktur zur Überabtastung mit sinc-förmigem Frequenzgang

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19990830112 EP1033812B1 (fr) 1999-03-03 1999-03-03 Structure de suréchantillonnage ayant une réponse en fréquence du type sinc

Publications (2)

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EP1033812A1 EP1033812A1 (fr) 2000-09-06
EP1033812B1 true EP1033812B1 (fr) 2005-08-10

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EP (1) EP1033812B1 (fr)
DE (1) DE69926601D1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107707259B (zh) * 2017-11-01 2020-11-03 兰州大学 一种模拟信号采样与重构的方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5835390A (en) * 1995-12-27 1998-11-10 Asahi Kasei Microsystems Co., Ltd Merged multi-stage comb filter with reduced operational requirements

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EP1033812A1 (fr) 2000-09-06
DE69926601D1 (de) 2005-09-15

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