EP1031074B1 - Processor configured to generate lookahead results from collapsed moves, compares, and simple arithmetic instructions - Google Patents
Processor configured to generate lookahead results from collapsed moves, compares, and simple arithmetic instructions Download PDFInfo
- Publication number
- EP1031074B1 EP1031074B1 EP98953695A EP98953695A EP1031074B1 EP 1031074 B1 EP1031074 B1 EP 1031074B1 EP 98953695 A EP98953695 A EP 98953695A EP 98953695 A EP98953695 A EP 98953695A EP 1031074 B1 EP1031074 B1 EP 1031074B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- instruction
- instructions
- lookahead
- operand
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
- G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US6587897P | 1997-11-17 | 1997-11-17 | |
US65878P | 1997-11-17 | ||
US115123 | 1998-07-14 | ||
US09/115,123 US6112293A (en) | 1997-11-17 | 1998-07-14 | Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result |
PCT/US1998/022030 WO1999026132A2 (en) | 1997-11-17 | 1998-10-19 | Processor configured to generate lookahead results from collapsed moves, compares and simple arithmetic instructions |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1031074A2 EP1031074A2 (en) | 2000-08-30 |
EP1031074B1 true EP1031074B1 (en) | 2006-06-28 |
Family
ID=26746120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP98953695A Expired - Lifetime EP1031074B1 (en) | 1997-11-17 | 1998-10-19 | Processor configured to generate lookahead results from collapsed moves, compares, and simple arithmetic instructions |
Country Status (5)
Country | Link |
---|---|
US (1) | US6112293A (ja) |
EP (1) | EP1031074B1 (ja) |
JP (1) | JP3866918B2 (ja) |
DE (1) | DE69835100T2 (ja) |
WO (1) | WO1999026132A2 (ja) |
Families Citing this family (41)
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US6363469B1 (en) * | 1998-07-13 | 2002-03-26 | Matsushita Electric Industrial Co., Ltd. | Address generation apparatus |
US6247146B1 (en) * | 1998-08-17 | 2001-06-12 | Advanced Micro Devices, Inc. | Method for verifying branch trace history buffer information |
US6480818B1 (en) | 1998-11-13 | 2002-11-12 | Cray Inc. | Debugging techniques in a multithreaded environment |
US6862635B1 (en) | 1998-11-13 | 2005-03-01 | Cray Inc. | Synchronization techniques in a multithreaded environment |
US6314471B1 (en) * | 1998-11-13 | 2001-11-06 | Cray Inc. | Techniques for an interrupt free operating system |
US6952827B1 (en) * | 1998-11-13 | 2005-10-04 | Cray Inc. | User program and operating system interface in a multithreaded environment |
US6189091B1 (en) * | 1998-12-02 | 2001-02-13 | Ip First, L.L.C. | Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection |
US6430676B1 (en) * | 1998-12-23 | 2002-08-06 | Cray Inc. | Method and system for calculating instruction lookahead |
US6321379B1 (en) | 1998-12-23 | 2001-11-20 | Cray Inc. | Method and system for target register allocation |
US6353829B1 (en) | 1998-12-23 | 2002-03-05 | Cray Inc. | Method and system for memory allocation in a multiprocessing environment |
US6665688B1 (en) | 1998-12-23 | 2003-12-16 | Cray Inc. | Method and system for automatically regenerating data on-demand |
US6230313B1 (en) * | 1998-12-23 | 2001-05-08 | Cray Inc. | Parallelism performance analysis based on execution trace information |
US6415433B1 (en) | 1998-12-23 | 2002-07-02 | Cray Inc. | Method and system for identifying locations to move portions of the computer program |
US6247097B1 (en) * | 1999-01-22 | 2001-06-12 | International Business Machines Corporation | Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions |
US6499101B1 (en) | 1999-03-18 | 2002-12-24 | I.P. First L.L.C. | Static branch prediction mechanism for conditional branch instructions |
US6343359B1 (en) | 1999-05-18 | 2002-01-29 | Ip-First, L.L.C. | Result forwarding cache |
US6546481B1 (en) | 1999-11-05 | 2003-04-08 | Ip - First Llc | Split history tables for branch prediction |
US6629234B1 (en) * | 2000-03-30 | 2003-09-30 | Ip. First, L.L.C. | Speculative generation at address generation stage of previous instruction result stored in forward cache for use by succeeding address dependent instruction |
US6782469B1 (en) * | 2000-09-29 | 2004-08-24 | Intel Corporation | Runtime critical load/data ordering |
US7185182B2 (en) * | 2003-02-04 | 2007-02-27 | Via Technologies, Inc. | Pipelined microprocessor, apparatus, and method for generating early instruction results |
US7107438B2 (en) * | 2003-02-04 | 2006-09-12 | Via Technologies, Inc. | Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictions |
US7100024B2 (en) | 2003-02-04 | 2006-08-29 | Via Technologies, Inc. | Pipelined microprocessor, apparatus, and method for generating early status flags |
US7290121B2 (en) * | 2003-06-12 | 2007-10-30 | Advanced Micro Devices, Inc. | Method and data processor with reduced stalling due to operand dependencies |
US20050216713A1 (en) * | 2004-03-25 | 2005-09-29 | International Business Machines Corporation | Instruction text controlled selectively stated branches for prediction via a branch target buffer |
CN100527099C (zh) * | 2005-02-15 | 2009-08-12 | 皇家飞利浦电子股份有限公司 | 用于提高数据处理设备的存储单元的性能的装置和方法 |
US7243210B2 (en) * | 2005-05-31 | 2007-07-10 | Atmel Corporation | Extracted-index addressing of byte-addressable memories |
US7734900B2 (en) * | 2008-01-11 | 2010-06-08 | International Business Machines Corporation | Computer configuration virtual topology discovery and instruction therefore |
US9280480B2 (en) | 2008-01-11 | 2016-03-08 | International Business Machines Corporation | Extract target cache attribute facility and instruction therefor |
US7895419B2 (en) | 2008-01-11 | 2011-02-22 | International Business Machines Corporation | Rotate then operate on selected bits facility and instructions therefore |
US7739434B2 (en) * | 2008-01-11 | 2010-06-15 | International Business Machines Corporation | Performing a configuration virtual topology change and instruction therefore |
US20090182985A1 (en) * | 2008-01-11 | 2009-07-16 | International Business Machines Corporation | Move Facility and Instructions Therefore |
US20090182992A1 (en) * | 2008-01-11 | 2009-07-16 | International Business Machines Corporation | Load Relative and Store Relative Facility and Instructions Therefore |
US20090182988A1 (en) * | 2008-01-11 | 2009-07-16 | International Business Machines Corporation | Compare Relative Long Facility and Instructions Therefore |
US7870339B2 (en) * | 2008-01-11 | 2011-01-11 | International Business Machines Corporation | Extract cache attribute facility and instruction therefore |
US20090182984A1 (en) * | 2008-01-11 | 2009-07-16 | International Business Machines Corporation | Execute Relative Long Facility and Instructions Therefore |
US9690591B2 (en) | 2008-10-30 | 2017-06-27 | Intel Corporation | System and method for fusing instructions queued during a time window defined by a delay counter |
US8966230B2 (en) * | 2009-09-30 | 2015-02-24 | Intel Corporation | Dynamic selection of execution stage |
JP2013131036A (ja) * | 2011-12-21 | 2013-07-04 | Fujitsu Ltd | 演算処理装置及び演算処理装置の制御方法 |
CN103984637A (zh) * | 2013-02-07 | 2014-08-13 | 上海芯豪微电子有限公司 | 一种指令处理系统及方法 |
GB2518613A (en) | 2013-09-25 | 2015-04-01 | Ibm | Multiple core processing with high throughput atomic memory operations |
CN106406820B (zh) * | 2015-07-29 | 2019-01-15 | 深圳市中兴微电子技术有限公司 | 一种网络处理器微引擎的多发射指令并行处理方法及装置 |
Family Cites Families (16)
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US5197137A (en) * | 1989-07-28 | 1993-03-23 | International Business Machines Corporation | Computer architecture for the concurrent execution of sequential programs |
US5630157A (en) * | 1991-06-13 | 1997-05-13 | International Business Machines Corporation | Computer organization for multiple and out-of-order execution of condition code testing and setting instructions |
US5539911A (en) * | 1991-07-08 | 1996-07-23 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
WO1993020505A2 (en) * | 1992-03-31 | 1993-10-14 | Seiko Epson Corporation | Superscalar risc instruction scheduling |
KR100248903B1 (ko) * | 1992-09-29 | 2000-03-15 | 야스카와 히데아키 | 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템 |
US5628021A (en) * | 1992-12-31 | 1997-05-06 | Seiko Epson Corporation | System and method for assigning tags to control instruction processing in a superscalar processor |
DE69429061T2 (de) * | 1993-10-29 | 2002-07-18 | Advanced Micro Devices Inc | Superskalarmikroprozessoren |
US5625789A (en) * | 1994-10-24 | 1997-04-29 | International Business Machines Corporation | Apparatus for source operand dependendency analyses register renaming and rapid pipeline recovery in a microprocessor that issues and executes multiple instructions out-of-order in a single cycle |
US5675758A (en) * | 1994-11-15 | 1997-10-07 | Advanced Micro Devices, Inc. | Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations |
US5878244A (en) * | 1995-01-25 | 1999-03-02 | Advanced Micro Devices, Inc. | Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received |
US5768610A (en) * | 1995-06-07 | 1998-06-16 | Advanced Micro Devices, Inc. | Lookahead register value generator and a superscalar microprocessor employing same |
US5835968A (en) * | 1996-04-17 | 1998-11-10 | Advanced Micro Devices, Inc. | Apparatus for providing memory and register operands concurrently to functional units |
US5872951A (en) * | 1996-07-26 | 1999-02-16 | Advanced Micro Design, Inc. | Reorder buffer having a future file for storing speculative instruction execution results |
US5961639A (en) * | 1996-12-16 | 1999-10-05 | International Business Machines Corporation | Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution |
US5913048A (en) * | 1997-03-31 | 1999-06-15 | International Business Machines Corporation | Dispatching instructions in a processor supporting out-of-order execution |
US5948098A (en) * | 1997-06-30 | 1999-09-07 | Sun Microsystems, Inc. | Execution unit and method for executing performance critical and non-performance critical arithmetic instructions in separate pipelines |
-
1998
- 1998-07-14 US US09/115,123 patent/US6112293A/en not_active Expired - Lifetime
- 1998-10-19 WO PCT/US1998/022030 patent/WO1999026132A2/en active IP Right Grant
- 1998-10-19 EP EP98953695A patent/EP1031074B1/en not_active Expired - Lifetime
- 1998-10-19 DE DE69835100T patent/DE69835100T2/de not_active Expired - Lifetime
- 1998-10-19 JP JP2000521433A patent/JP3866918B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2001523854A (ja) | 2001-11-27 |
DE69835100T2 (de) | 2007-02-01 |
US6112293A (en) | 2000-08-29 |
DE69835100D1 (de) | 2006-08-10 |
WO1999026132A2 (en) | 1999-05-27 |
JP3866918B2 (ja) | 2007-01-10 |
EP1031074A2 (en) | 2000-08-30 |
WO1999026132A3 (en) | 1999-09-16 |
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