EP1010081A1 - Schaltungsanordnung mit einem mikroprozessor und einem stapelspeicher - Google Patents

Schaltungsanordnung mit einem mikroprozessor und einem stapelspeicher

Info

Publication number
EP1010081A1
EP1010081A1 EP97910244A EP97910244A EP1010081A1 EP 1010081 A1 EP1010081 A1 EP 1010081A1 EP 97910244 A EP97910244 A EP 97910244A EP 97910244 A EP97910244 A EP 97910244A EP 1010081 A1 EP1010081 A1 EP 1010081A1
Authority
EP
European Patent Office
Prior art keywords
memory
register
stack
logical address
address space
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97910244A
Other languages
German (de)
English (en)
French (fr)
Inventor
Klaus Oberländer
Michael Baldischweiler
Stefan Pfab
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1010081A1 publication Critical patent/EP1010081A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules

Definitions

  • An interrupt can advantageously be triggered by the result signal of the detection means, whereby the processor interrupts the execution of the respective program at the current position and jumps to a predetermined other program address.
  • the program instructions to be processed there can then cause the stack memory to be emptied by forcibly terminating the last started subroutines.
  • this register 1111 1111 to 1111 0000, this registers a logic 60 and increments the content of the first register 6 by the value 1. Conversely, in the case of a return from a subroutine (Return), the corresponding return address is taken from the stack memory 4, and the last four bits XXXX of the stack pointer 7 are decremented by the value 1. If there is an underflow of the last four bits XXXX, this registers the logic 60 and decrements the content of the first register 6 by 1.
  • an increment or decrement value (for example 2) which deviates therefrom can also be provided. This depends on the scope of the data to be stored in the stack 4. In the exemplary embodiment described with reference to FIG. 1, in which the storage units have a size of one byte each, an increment or decrement of 2 each would have to be selected if the return addresses or variables to be stored have a size of two bytes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
EP97910244A 1996-09-30 1997-09-30 Schaltungsanordnung mit einem mikroprozessor und einem stapelspeicher Withdrawn EP1010081A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19640316A DE19640316A1 (de) 1996-09-30 1996-09-30 Schaltungsanordnung mit einem Mikroprozessor und einem Stapelspeicher
DE19640316 1996-09-30
PCT/DE1997/002253 WO1998014876A1 (de) 1996-09-30 1997-09-30 Schaltungsanordnung mit einem mikroprozessor und einem stapelspeicher

Publications (1)

Publication Number Publication Date
EP1010081A1 true EP1010081A1 (de) 2000-06-21

Family

ID=7807457

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97910244A Withdrawn EP1010081A1 (de) 1996-09-30 1997-09-30 Schaltungsanordnung mit einem mikroprozessor und einem stapelspeicher

Country Status (7)

Country Link
EP (1) EP1010081A1 (ko)
JP (1) JP2000503792A (ko)
KR (1) KR20000048754A (ko)
CN (1) CN1232564A (ko)
BR (1) BR9712154A (ko)
DE (1) DE19640316A1 (ko)
WO (1) WO1998014876A1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100353335C (zh) * 2003-03-28 2007-12-05 联发科技股份有限公司 增加处理器中存储器的方法
JP5391870B2 (ja) * 2009-06-26 2014-01-15 富士通株式会社 情報処理装置及びその方法
CN102193868B (zh) * 2010-03-10 2013-06-19 上海海尔集成电路有限公司 数据堆栈存储电路及微控制器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3726192A1 (de) * 1987-08-06 1989-02-16 Otto Mueller Stacksteuerung
JPH0215345A (ja) * 1988-07-04 1990-01-19 Hitachi Ltd データ処理装置
US5107457A (en) * 1989-04-03 1992-04-21 The Johns Hopkins University Stack data cache having a stack management hardware with internal and external stack pointers and buffers for handling underflow and overflow stack
US5032981A (en) * 1989-04-10 1991-07-16 Cirrus Logic, Inc. Method for increasing effective addressable data processing system memory space
US5255382A (en) * 1990-09-24 1993-10-19 Pawloski Martin B Program memory expander for 8051-based microcontrolled system
GB2282470B (en) * 1993-09-23 1997-12-24 Motorola Israel Ltd A processor arrangement with memory management
DE4340551A1 (de) * 1993-11-29 1995-06-01 Philips Patentverwaltung Programmspeichererweiterung für einen Mikroprozessor
US5666556A (en) * 1993-12-30 1997-09-09 Intel Corporation Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit
SG45399A1 (en) * 1994-01-12 1998-01-16 Sun Microsystems Inc Logically addressable physical memory for a virtual memory computer system that support multiple page sizes

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9814876A1 *

Also Published As

Publication number Publication date
DE19640316A1 (de) 1998-04-02
WO1998014876A1 (de) 1998-04-09
JP2000503792A (ja) 2000-03-28
BR9712154A (pt) 1999-08-31
CN1232564A (zh) 1999-10-20
KR20000048754A (ko) 2000-07-25

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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Effective date: 20030401