EP1004972B1 - Waveform generator - Google Patents

Description

The invention relates to a waveform generator for internal or external signals. Such waveform generators are used when signals not only the maximum, end or logic level but also the course in the signal transition area is observed. For example, it may be required that thresholds be reached at certain reference times, pulses broadened or narrowed, or unwanted side effects eliminated, such as interfering harmonics. Disturbing harmonics are caused above all by discontinuities in the signal curve in conjunction with steep signal edges. The harmonics caused by large current changes are particularly unpleasant, even in monolithically integrated circuits, when the associated voltage level is changed within a relatively small time interval with a relatively large capacitive load. This occurs in digitally-operating circuits which simultaneously change a plurality of switching states in synchronism with a common clock. The associated load currents accumulate on the clock and supply lines and generate electromagnetic interference via them. If external loads are switched via output stages, then these load currents are also found on the output lines of these output stages and generate additional electromagnetic interference there. The size of the interference depends on the output stage, the internal or external load and the type and length of the connecting cables. The contribution of the lines is relatively fixed by the geometry and subjected to only small tolerances. However, the contributions of the output stage and the load, which are dependent on the respective circuit technology, the manufacturing tolerance, the temperature, the number and size of the transistors and other variables, are different and can therefore be very scattered.

When using CMOS circuits, the load usually consists of the sum of the input capacitances of the transistor gates to be switched. Typical summation values for the input capacitances to be considered are between 5 pF and several 100 pF. Even if the entire range of values does not usually have to be covered, it is immediately apparent that the usual complementary driver circuits are not suitable as waveform generator for output signals because they are used in conjunction with the connected Load capacitances cause approximately an exponential charge or discharge. The main disadvantage of the resulting switching edge is that the signal during the transition has very different slopes. At the beginning, the pitch is very high, creating many harmonics, and at the end, the pitch is very low, making the final level very late. A simultaneous elimination of both disadvantages is not possible by known complementary circuits. In order to comply with the various tolerances for the maximum permissible transition time of the switching edge, the complementary driver circuit is designed for the most unfavorable tolerance combination, so that the signal edges at the beginning are much too steep and thus produce unwanted harmonics.

There are also other cases where the shape of the switching edges must be taken into account, for example, when rising and falling edges of digital signals, the respective switching thresholds should be reached at certain times. This is important, for example, in the demand for overlap or non-overlap. For other digital signals in which, for example, only one switching edge is important, only the shape and duration of this switching edge of interest. The shape and duration of the second switching edge is immaterial to the consideration of disturbances when it is flat relative to the first switching edge. Again, there are other signals whose edges should be as trapezoidal or symmetrical as possible.

The problem of high-frequency electromagnetic radiation of signal, supply and clock lines is increasingly coming to the fore with the complexity of monolithic integrated circuits, the increasing number of transistors and the increasing processing speed. Information about this, referring to interference from other devices or self-interference, often found under the abbreviation EMC (= E lektro m agnetic V tolerability). Self-interference can occur, for example, if apart from digital also analog circuit parts are present in the respective circuit and there occurs a signal corruption by the superimposition of the analog signals with interspersed digital signals.

It is therefore desirable to control the respective signal forms, in particular in the signal edge region.

From US 5,268,847 a waveform generator is known in which the waveform to be synthesized is approximated via a staircase curve. The staircase curve is achieved by switching on switching transistors according to a predetermined pattern of control signals obtained from a clock signal by means of a counter and a decoder coupled thereto. The pattern of the control signals is previously calculated according to the load capacitance to determine the wiring of the decoder and the switching transistors.

It is an object of the invention to provide a waveform generator which allows a more flexible adaptation to a capacitive load.

This object is achieved by a waveform generator having the features of claim 1.

The main advantage of the invention is that the switching edge is subdivided into different time ranges whose respective edge steepnesses are adjustable within limits independently of each other. Pointing the waveform to a center of the signal edge reduces frequencies at twice, four times, six times, etc. the frequency of the fundamental signal frequency. By a sinusoidal design of the switching edges can be on the reduced amplitude of the harmonics bring the electromagnetic radiation to a minimum. This applies to both pure clock signals and digital signals and relates to clock, control, data or supply lines. For the sake of simplicity, in the text which follows, instead of the clock, control or data signal, only "signal" is usually indicated.

A fine adjustment of the steepness without large area expenditure is achieved with the connection and / or disconnection of weighted switching transistors, when the weighted transistors are groupwise switchable. The weighting of the current yield takes place in the case of bipolar transistors via the emitter surface or, in the case of CMOS transistors, via the width-to-length ratio (= W / L) of the respective gate zone. The weight graduation over powers of two allows the digital selection of the group members or their control by means of binary numbers. Although the setting of the weighting via the parallel connection of the same transistors is more accurate, the area required is greater.

An increase in the flexibility of the waveform generator is achieved when the frequency of the clock signal is not fixed, but may change within limits or be adjustable. This causes a first control circuit which controls the delay times of the delayed clock signals. The regulation takes place with respect to the respective reference phase and frequency of the clock signal. Such control circuits are known, they use to form the individual delay times delay chains whose total or partial delay time is coupled by means of a phase locked loop to the respective clock signal. A detailed example of this is described in EP 0 116 669 A (internally: C-DIT-1179EP). The design which can be coupled to an arbitrary clock is advantageous if in the respective circuit the clock is not fixed as a system clock but is variable or not yet known. This design is also suitable as a general Auslegebaustein in a program library, because within wide limits in the circuit design no frequency adjustment is required.

Finally, by means of a second control circuit, which is independent of the first control circuit, a further improvement in the flexibility of the waveform generator can be achieved by making the current yield of the switching transistors dependent on the respective load. The change of the current yield is most easily done by switching on or off of switching transistors or by another group selection. The required control takes over a second control circuit which compares a current voltage value (= actual value) with a desired value by means of a voltage comparison circuit during the switching edge and forms the corresponding control signal from the comparison of the actual value with the desired value, which can also be a selection signal. With the selection signal, the weighting of the switched switching transistors is increased or decreased together, while maintaining the Stromergiebigkeitsverhältnisse, until the deviation of the setpoint and actual value has become sufficiently small again. As setpoints, for example, are the Center level of the positive and negative switching edge. Depending on the position of the deviation, an up-and-down counter is activated, whose respective counter content adapts the weighting value by means of a control logic.

With a sinusoidal curve of the switching edge, the lowest harmonic number is reached for clock, control or data signals. Such an edge profile can be simulated with a fairly good approximation, as an embodiment shows later. If, in the case of clock signals, the two sinusoidal edges correspond to half a clock period, then a sine signal has been formed from a rectangular signal which ideally contains no harmonics. A disadvantage can be the short residence time in the upper or lower level range. These times can be increased if the edges are set shorter than half a clock period by means of the waveform generator. For data signals, which typically include two or more clock periods, the sinusoidal edge duration is chosen to be longer than half a clock period. It is expedient not to go beyond one clock period, because then the additional effect with regard to the interference radiation is negligible, but the disadvantages due to the delayed data transfer increase. However, extending the edges of data signals over a few clock periods may be appropriate in those cases where the clock rate is significantly higher than the data rate for any reason.

By the waveform generator can be set even relatively complicated waveforms that can even correspond to a frequency doubling or frequency multiplication of a clock signal. In the frequency doubling, a double pulse with predetermined edges is generated within a single clock period via the control of the delayed clock signals by means of two rising and two falling edges.

For the formation of defined rising and falling switching edges complementary switching transistors are required whose output currents are summed in said output node. Such a waveform generator, the complementary switching transistors are driven by delayed clock signals, can replace a conventional, consisting of a complementary transistor pair driver circuit with advantage.

Fig. 1

zeigt im Zeitdiagramm ein übliches Takt- oder Datensignal,

Fig. 2

zeigt im Zeitdiagramm ein Takt- oder Datensignal mit sinusförmigen Flanken,

Fig. 3

gibt in Tabellenform ein Beispiel für eine zeitabhängige Gewichtung von n- und p-Kanal-Schalttransistoren bei sinusförmigem Flankenverlauf,

Fig. 4

zeigt schematisch die Schaltung eines bevorzugtes Ausführungsbeispiels des Kurvenformgenerators,

Fig. 5

zeigt schematisch ein Teil der zugehörigen Ansteuerlogik und

Fig. 6

zeigt in Tabellenform ein Beispiel für eine zeit- und lastabhängige Gewichtung über die Kanalweiten von n- und p-Kanal-Schalttransistoren.

The invention and advantageous embodiments will now be explained in more detail with reference to the figures of the drawing:

Fig. 1

shows in the time diagram a usual clock or data signal,

Fig. 2

shows in the time diagram a clock or data signal with sinusoidal edges,

Fig. 3

gives in table form an example of a time-dependent weighting of n- and p-channel switching transistors with sinusoidal edge characteristic,

Fig. 4

Fig. 12 schematically shows the circuit of a preferred embodiment of the waveform generator;

Fig. 5

schematically shows a part of the associated drive logic and

Fig. 6

shows in tabular form an example of a time and load dependent weighting across the channel widths of n- and p-channel switching transistors.

Fig. 1 shows in the timing diagram the input side course of a clock or data signal c 'or d' and the approximately exponential output side course of the clock or data signal c or d due to the load capacity to be driven. By means of a first and second switching threshold s1, s2 logic state areas for the signal c, d are defined. Below the threshold s1, the logical "0" and above the threshold s2 is the logical "1". The position of the switching thresholds s1, s2 and the associated switching times ts1, ts2, ts2 *, ts1 * are important for signal processing and interference immunity.

The schematic representation of Fig. 1 illustrates that with increasing clock rates and processing speeds, the duration of the signal transitions with respect to the period T are no longer negligible. From time t1, the positive signal edge begins with a fairly large slope. The first threshold s1 is exceeded at time ts1, after which the slope decreases significantly. The second threshold s2 is exceeded at time ts2. The associated signal levels are S1 and S2. Finally, the signal c, d approaches the maximum value max with an ever decreasing slope. The negative edge starts at time t2. The switching thresholds s2 and s1 are exceeded at the times ts2 * and ts1 *, respectively Signal values are S2 * or S1 *. Finally, at time t3, the positive edge starts again.

The steep signal edges at the times ts1, ts2 * generate high charging or discharging currents due to the connected, but not shown load capacity. If these flow via lines, they generate electromagnetic interference radiation. As disturbing lines here already supply lines, short connections to other circuits or even connections to blocking devices can be effective. The asymmetry within the switching edge also causes that already interference frequencies are formed at twice the clock or data rate. The coupled into analog circuit components disturbances are thus often close to the useful signal and can be eliminated later only by a high filter effort.

FIG. 2 shows a timing diagram of a clock signal c and a data signal d whose signal edges are imposed by a waveform generator according to the invention on a course that deviates from the exponential edge profile of FIG. The flanks correspond approximately to a sinusoidal course. In the case of the clock signal c, a clock period T is divided into ten equal individual steps. The division takes place via undelayed and delayed clock signals c0 and c1 to c9, with the time frame the course of the rising and falling signal edges is changed. The desired edge profile is formed approximately by the superimposition of different charge or discharge curves. The change of the charging or discharging operation is controlled by the undelayed and delayed clock signals c0 and c1 to c9, respectively, by a first or second inhibiting signal sp0, sp1 terminating the preceding charging or discharging operation. In FIG. 2, the preceding charging process is aborted by means of the first blocking signal sp0 because the negative signal edge starts at the instant t0. By means of the second blocking signal sp1 at the time t5, the preceding discharging process between the times t0 to t4 is ended because the positive clock edge begins at this time. This is terminated at time t10 or t0 by the first lock signal sp0 again. The finer the increment, the better the approximation to the desired signal curve.

As an example, FIG. 2 also shows the sinusoidal edge profile in the case of data signals d, which then maintain the respective logic state "1" or "0" for some time. The negative data edge of the example of FIG. 2 lies in the time interval t0 to t5, after which the data level remains stable until time t10, at which point the positive edge begins, which is completed at time t15. The data rate in this example is the same as the clock rate. If the data rate is less than or equal to the clock rate, then either the course of the data edges can be made flatter than the course of the clock edges or with the same edge formation, the dwell time in the upper or lower logic state is correspondingly larger.

The timing diagram of Fig. 2 shows a desired waveform under the assumption that at least in the signal values shown with small circles, the ideal signal values are achieved and the course therebetween is as uniform as possible. In the case of a sinusoidal flank formation this can be achieved by the temporal superimposition of discharge or charging curves. In CMOS circuits, the capacitive load is charged by means of p-channel transistors and the discharge by means of n-channel transistors, which are activated by the instantaneous and delayed clock signals c0 and c1 to c9. For a clock signal with sinusoidal clock edges whose duration corresponds to half a clock period, the table of FIG. 3 provides the associated transistor sizes. It is further assumed that the clock period T is divided into thirty time intervals defined by the equidistant timings t0 to t29. Via a circuit simulation program, for example, the variables of the switching transistors active at the individual times t0 to t29 can be determined empirically in a simple manner. Since the transistor and circuit models in the simulation programs are very accurate, the results can be easily incorporated into the layout.

The table of Fig. 3 shows the result of such a simulation. The size of the required switching transistors is given in the time interval from t0 to t15 for the falling edge and in the time interval t15 to t30 (= t0) for the rising edge in unit values "N" and "P", respectively, the size of the associated n and p -Channel transistors to achieve define a sinusoidal edge profile. For certain time intervals, the quantities remain constant. This is also apparent from the edge profile of Fig. 1. At the beginning of charging or discharging very small switching transistors are required because the voltage difference between the clock signal and the capacitor voltage is initially large. When the charging or discharging process is almost completed, the voltage difference is small, and the increase in the slew rate requires large switching transistors in this area. A very effective criterion for the simulation is the computationally determined signal spectrum, which can detect changes in the weighting in the fine range. The gross changes result from a simple comparison of the setpoint and actual voltages.

In Fig. 3, the initial sizes of the n- or p-channel transistors are shown at time t0 and t15, wherein as a unit value or reference quantities "N" or "P" for n-resp. p-channel unit transistors with the same Stromergiebigkeiten stand. At time t1, six of these unit transistors N are connected. At time t2 another nine unit transistors N and at time t3 another twelve. At the times t4 to t7, no further transistors are connected, this corresponds to the indication 0N. At time t8, the number of n-channel transistors turned on increases by ten unit transistors N, by another twelve at time t9, by fourteen at time t10, and by sixteen unit transistors N at time t11. This value no longer changes and remains constant for the times t12 to t14. At time t15, the end of the descent edge is reached and the rising edge begins. The end of the descent edge is enforced by disabling all n-channel transistors that have been activated between times t0 to t15. The shutdown is effected by the blocking signal sp1.

The positive rising edge between times t15 to t30 is enforced by adding the p-channel transistors shown in Table 3 at the respective times. The table refers to the unit transistors P. The positive signal edge is terminated at time t30 or t0 by the first blocking signal sp0, which blocks all previously activated p-channel transistors again.

The simulation of the transistor sizes of FIG. 3 is based on any load capacitance, which, however, may no longer be changed as a reference capacitance for the simulation. If the load capacitance is twice as large, then the unit transistors N, P should also be doubled, otherwise the approximation will not work. Of course, the unit transistors N and P may be made larger or smaller for a given load capacitance if the preceding factor is adjusted accordingly, so that the product (e.g., 12xN) of multiplication factor and reference value of the unit transistor N remains constant at the respective time ti.

An adaptation to different load capacities with fixed unit sizes N, P can thus also be achieved via the respective multiplication factors, which then serve as weighting factors. In any case, there is a direct proportionality between the respective weighting factor and the respective size of the capacitive load. If the capacitive loads are differentiated by a fixed factor G, the associated weighting factors also differ by the same factor G. The proportional control of all weighting factors by a single common factor G corresponds to the multiplication of the weighting factors given by the curve by the factor G. Multiplication is achieved in the usual binary systems by a shift function or by another grouping, cf. The weighting in the table of FIG. 3 is still somewhat coarse and corresponds to a first approximation of the desired current edges. The table values can be improved by the already mentioned simulation method. As far as possible, the approximation and simulation attempt to keep the number of required switching times as small as possible otherwise the circuit complexity increases. A good solution to this is shown in the table of FIG. 6.

FIG. 4 shows a block diagram of an exemplary embodiment of the waveform generator according to the invention. A delay device V generates from an input-side clock signal c 'undelayed and delayed clock signals c0 and ci and Blocking signals spi. These signals control a drive logic AL, which supplies control signals for p and n-channel switching transistors of a switching stage S in response to these signals. The output currents of the individual switching transistors are summed by means of an output node k and serve as a charging or discharging current + i or -i of an internal or external load capacitance CL.

The clock signal c 'is either coupled to a system clock or comes from a clock generator cg. The clock period T is divided into the delay device V in particular equidistant time intervals, each of which one of the delayed clock signals ci is assigned. In order to couple the delay times exactly to the clock period T, the delay times of the individual elements in the delay device V are coupled by means of a delay locked loop VL to the clock period T and the reference phase of the clock signal c '. If the waveform generator is to modify the course of data signals d, then the drive logic AL except the undelayed and delayed clock signals c0 to ci and the disable signals spi is fed on the input side with the data signal d 'from a data source D. Since the data signal d 'is coupled to the clock signal c', the switching edge is still controlled by the clock signal c ', wherein the data signal d' only causes the selection of a positive or negative edge or maintains the existing logic state of the output signal d.

The switching stage S contains a p-switching stage SP, in which the p-channel switching transistors between the positive voltage supply + U and the output node k are connected in parallel. Each switching transistor is controlled separately via its own control line of the control logic AL. Similarly, the switching stage S includes an n-switching stage SN with n-channel switching transistors, which are connected in parallel between the output node k and the ground reference point. Each n-channel switching transistor is connected via its own control line to the associated control area of the control logic AL. In the p- and n-switching stage SP and SN, a transistor group is present for each switching time ti, provided that the size of the resulting switching transistor is to be changed in this switching time. For the table example of Fig. 3, these are negative sinusoidal ones Switching edge eight transistor groups, which are successively switched on successively at the times t0, t1, t2, t3, t8, t9, t10 and t11.

An adaptation of the current yield of the switching transistors in the switching stage S to the load capacitance CL according to the embodiment of FIG. 4 allows a weighting control loop GR. For example, the assumption behind the weighting control loop GR is that the capacitive load CL has a value of 10 pF in the minimum case. This is called base load. From the discussed circuit simulation arise at the respective times ti, the sizes of the associated switching transistors, which are thus also referred to as base load transistors. If a capacitive load range, which ranges from 10 pF to 100 pF, is automatically covered by the weighting control loop GR, then the size of the respective switching transistors should be correspondingly adapted. It is completely sufficient if the adjustment is not continuous but in steps. If fifteen adjustment levels are available for the specified range of 10 pF to 100 pF, then the load capacity can be adjusted in increments of 6pF increments. This resolution is completely sufficient. For example, the fifteen levels can be achieved by combining four levels of weighting if these two powers are equal. The smallest weighting unit corresponds to a load capacity of 6 pF, the second weighting stage to a load capacity of 12 pF, the third weighting stage to a load capacity of 24 pF and the fourth weighting stage to a load capacity of 48 pF.

The weighting control loop GR contains a voltage comparator du, which compares the voltage sk of the output node k with a reference value r1, r2 at a specific edge instant. The reference level may be the center level of the output signal c, d. The voltage comparison can also take place at other times, which are defined by a first or second comparison clock cr1, cr2, which retrieve corresponding reference signals r1, r2 from a reference voltage generator q. For example, the taps of a voltage divider can serve as a reference voltage generator q. Whether the voltage comparison takes place at the rising or falling switching edge, is controlled by the comparison clocks cr1, cr2. The output signal of the voltage comparator du is an error signal fu fed to a weighting regulator rg. In the simplest case, this is a 4-bit counter which is switched up or down by one count level by the error signal fu. The 4-bit output of the counter is the weight value Gi, which sets the 15 adjustment stages in the shift stage S.

The delay locked loop VL compares the undelayed clock signal c0 with the one clock period delayed clock signal cT of the delay means V, for example, a delay string, and forms therefrom a phase error signal fp by means of a phase detector dp. This is in a phase controller rp, for example, a PID controller (= proportional, integral, differential), filtered, and forms a control signal vp, with which the delay times of the delay chain are adjusted.

In Fig. 5, the drive logic AL and the switching stage S is shown in more detail for a certain time. The switching time corresponds to t18 of Fig. 3. Except for the weighting controller rg, here a 4-bit counter Z (a count-up and down counter), there is such a step for each switching time in which the size of the switching transistors changes , The delayed clock signal c18 feeds the one input of a flip-flop f whose reset input R is supplied with the first blocking signal sp1. The Q output Q of the flip-flop f is in each case connected to an input of four NAND gates u0, u1, u2, u3 (= NAND gate). The other input of the four gates is connected to a binary digit output of the 4-bit counter Z. Gate u3 depends on the MSB location of the four-bit counter. The valency is followed by the gates u2, u1 and finally u0, which is finally dependent on the LSB position. Depending on the position, the four gates u3, u2, u1, u0 control associated switching transistors P3, P2, P1, P0. Independently of the weighting, the base load transistor Pg is activated by the flip-flop f. All p-channel switching transistors are connected in parallel between the positive supply terminal + U and the output node k, so that the currents summed there as a charging current + i. The delayed clock signal c18 sets the flip-flop f, whereby a logical "1" is applied to the Q output. If the corresponding position signal from the 4-bit binary counter also one logical "1", then the associated NAND gate turns on the connected p-channel switching transistor. The Q output of the flip-flop f remains in the logic "1" state until the reset input R, the blocking signal sp1 occurs, which resets the Q output in the logic "0" state, causing all NAND Doors u0 to u3 brought back into the blocking state and thus the associated switching transistors P0 to P3 are also disabled. The base load transistor pg is blocked by an inverter in whose input is also at the flip-flop output Q.

FIG. 6 shows in tabular form an example of the time- and load-dependent weighting of p-channel and n-channel switching transistors in the case of a sinusoidal edge characteristic, the clock period T being divided into equal-cycle increments in 20. For a given channel length L of 0.7 microns for the p- and n-channel switching transistors, the individual weighting values are set via the channel widths W. These channel widths W are given in the table of FIG. 6 in lines Pg and Ng for a base load of 10 pF. Of the 20 clock instants, changes in the switching transistors take place only at 10 clock instants. The corresponding times ti are indicated in the two table lines ti. For the p-channel switching transistors, these are the times t0, t1, t2, t4 and t7 and for the n-channel switching transistors, the times t10, t11, t12, t14 and t17. For the adaptation of the switching transistors to any capacitive load between 10 pF and 100 pF four weighted transistors are present for each clock time ti whose weighting factors the powers of two 2 ⁰ , 2 ¹ , 2 ² and 2 ³ and thus have a capacitive load step size of 6pF enable. The table of Fig. 6 shows the associated channel widths resulting from the predetermined weighting factors G0 to G3.

Claims (8)

1. A waveform generator for an output signal (c, d), comprising a switching stage (S) for forming a defined signal waveform, particularly in the presence of a capacitive load, using switching transistors which are turned on by a predetermined sequence of clock signals, with an output node (k) summing the output currents (+i, -i) of said switching transistors,
   characterized in that the sequence of clock signals comprises undelayed clock signals (c0) and delayed clock signals (ci) which are formed from an applied clock signal (c') by a delay device (V), with the respective delays and/or the selection of the switching transistors, which are controlled by the respective undelayed (c0) or delayed clock signals (ci), being determined by a control circuit (GR) which compares an actual value (sk) of the output signal (c, d) with a desired value (r1, r2) of the output signal (c, d) to form a control signal which corresponds to a weighting factor (Gi).
2. A waveform generator as claimed in claim 1, characterized in that the switching transistors are weighted in terms of their current yield.
3. A waveform generator as claimed in claim 1 or 2, characterized in that the switching transistors are controllable by the delayed clock signals (ci) and/or the undelayed clock signals (c0) individually or in groups.
4. A waveform generator as claimed in claim 1, characterized in that the delay device (V) is coupled to a control circuit (VL) which synchronizes the individual delays with respect to the respective reference phase and frequency of the applied clock signal (c').
5. A waveform generator as claimed in any one of claims 1 to 4, characterized in that the characteristic of the edges of the output signal (c, d) is approximately sinusoidal.
6. A waveform generator as claimed in claim 5, characterized in that the duration of the sinusoidal edges of the data output signals (d) is greater than half a clock period.
7. A waveform generator as claimed in any one of claims 1 to 6, characterized in that the predetermined edge characteristic of the output signal (c, d), particularly an essentially point-mirrored characteristic of the rising and falling edges, is caused by means of first and complementary second switching transistors, respectively, which are switched via a first and a second sequence of undelayed (c0) and delayed clock signals (ci), respectively, and whose output currents (+i, -i) are summed in the output node (k).
8. A waveform generator as claimed in any one of claims 1 to 7, characterized in that the switching transistors are turned off by associated blocking signals (spi) which are preferably formed synchronously with at least one of the undelayed (c0) and/or delayed clock signals (ci).

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