EP0999483A1 - Verfahren zum Einstellen des Takts eines Uhrenmoduls mittels Schmelzen von Schmelzsicherungen per Laser - Google Patents

Verfahren zum Einstellen des Takts eines Uhrenmoduls mittels Schmelzen von Schmelzsicherungen per Laser Download PDF

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Publication number
EP0999483A1
EP0999483A1 EP98121022A EP98121022A EP0999483A1 EP 0999483 A1 EP0999483 A1 EP 0999483A1 EP 98121022 A EP98121022 A EP 98121022A EP 98121022 A EP98121022 A EP 98121022A EP 0999483 A1 EP0999483 A1 EP 0999483A1
Authority
EP
European Patent Office
Prior art keywords
circuit
module
fuses
correction factor
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP98121022A
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English (en)
French (fr)
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EP0999483B1 (de
Inventor
Guenther Meusburger
Nicolas Jeannet
Rudolf Bugmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EM Microelectronic Marin SA
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EM Microelectronic Marin SA
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Publication date
Application filed by EM Microelectronic Marin SA filed Critical EM Microelectronic Marin SA
Priority to EP19980121022 priority Critical patent/EP0999483B1/de
Priority to DE69840506T priority patent/DE69840506D1/de
Publication of EP0999483A1 publication Critical patent/EP0999483A1/de
Application granted granted Critical
Publication of EP0999483B1 publication Critical patent/EP0999483B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/022—Circuits for deriving low frequency timing pulses from pulses of higher frequency the desired number of pulses per unit of time being obtained by adding to or substracting from a pulse train one or more pulses

Definitions

  • the present invention relates to a method allowing the adjustment of the running of a watch module, said watch module comprising in particular a quartz and a integrated circuit comprising an oscillator controlled by the quartz, a frequency divider circuit with several stages, an adjustment circuit allowing the introduction a correction factor for the division rate of said frequency divider circuit and memory circuit containing information representative of said factor correction.
  • step adjustment process is meant a method of introducing a factor of correction of the division rate of the divider circuit of frequency, so that the frequency of the pulses issued at the output of it is corrected so to be in a predetermined range.
  • module we will also mean a semi-finished system or intermediate, ready to be mounted in the product final.
  • watch module we mean in the following description, a printed circuit with different electronic components, in particular the quartz and the aforementioned integrated circuit.
  • Adjusting the frequency of the oscillator, particular of a quartz oscillator is an operation particularly complicated and delicate. Indeed, as this is set out in the disclosure of invention CH 534 913, this adjustment is carried out according to a first step coarse adjustment by mechanical operations of precision on quartz, then a second step fine adjustment on the encapsulated quartz, and finally according to a final stage of adjustment and compensation aging by an adjustment or trimmer system.
  • the frequency stability quartz is significantly deteriorated. Therefore, the patent CH 534 913 proposes a satisfactory solution and inexpensive, by acting directly on the rate of division of the frequency divider circuit by the introduction of a correction factor, this having effect of improving the stability of quartz and get rid of the use of a trimmer.
  • the frequency divider circuit proposed in the patent CH 534 913 has auxiliary electrical inputs whose logical state determines the division ratio of the frequency divider and a memory circuit, connected to these auxiliary inputs, to retain in coded form a information representative of the correction factor of the division ratio of the frequency divider circuit.
  • the circuit adjustment is typically connected to a memory circuit containing information representative of the factor of correction of the division rate.
  • the memorization of this information is preferably non-volatile so that it is not lost when the battery is changed or during a power interruption.
  • EPROM / EEPROM requires a significant investment in terms of circuit area integrated, because such a memory must not only understand a sufficient number of bits to code information representative of the correction factor, but also requires the implementation of a logic of programming to program it and a voltage multiplier circuit to produce the high voltages required for this programming. This what obviously translates into a substantial increase in the manufacturing cost of the integrated circuit due in particular to additional steps required to integrate the EPROM / EEPROM and affects the manufacturing cost of the watch module and the timepiece as such.
  • EPROM / EEPROM requires less surface than an additional contact area, but generates however a fixed investment due in particular to logic programming and voltage multiplier. So, the higher the number of bits the higher the solution EPROM / EEPROM is economical on the surface compared to the solution using contact pads additional. However, the manufacturing cost per unit area remains proportionally higher.
  • the patent application FR 2,238,280 describes an integrated oscillator and its method digital frequency adjustment including elements of memory programmable from outside the circuit integrated. These elements are diodes, some of which are short-circuited in order to change their state so permed. Each element is connected to a terminal of the integrated circuit.
  • An object of the present invention is thus to propose a method of adjusting the progress of a watch module which does not require complex implementation at the level of the integrated circuit, so the manufacturing cost of the latter, and therefore of the module as such, is not greatly affected.
  • Another object of the present invention is to provide a method of adjusting the progress of a watch module especially suitable for mass or automated production of watch modules, a simple adjustment process and fast.
  • An advantage of the present invention lies in the fact that memorizing representative information of the correction factor is carried out in a simple manner and above all fast, therefore particularly suitable for mass production of such modules.
  • the speed and simplicity of the adjustment method according to the present invention thus provides a substantial reduction in manufacturing costs.
  • the present invention has also the advantage of allowing the adjustment of the running of a watch module, either of a finished set or intermediate including other electronic components that the quartz, the oscillator, the divider circuit of frequency, the division rate adjustment circuit or the memory circuit. In this way, the adjustment can to be operated taking into account the influences of all electronic components of the module.
  • Another advantage of the present invention lies in the fact that the cost of the integrated circuit and the module watchmaker as such is not significantly affected.
  • the use of memory elements formed of destructible fuses by laser does not require a complex and costly implementation at the circuit level integrated.
  • FIG 1 is a schematic representation of a watch module comprising a printed circuit 1 comprising in particular a quartz 10 and an integrated circuit 20.
  • This integrated circuit 20 includes an oscillator 21 controlled by quartz 10 so as to typically deliver pulses at a frequency of 32768 Hz. This frequency is divided several times by a divider circuit of frequency 22 so as to deliver at its output pulses at a frequency of 1 Hz and thus allow the training and display of a time indication.
  • the circuit frequency divider 22 thus has a total number of 15 binary division stages 22.1 to 22.15. Both first stages 22.1 and 22.2 allow in particular to deliver a signal at a frequency of 8192 Hz which is used to allow correction of the division rate of the frequency divider circuit 22.
  • An adjustment circuit 23 allows for this purpose the introduction of a correction factor for the rate of division of the frequency divider circuit 22.
  • a circuit memory 24 thus contains information, generally in the form of a binary number N, representative of the circuit division correction factor frequency divider 22.
  • the adjustment method essentially consists in correcting the frequency difference existing between the frequency of the oscillator 21 and the frequency supplied by a standard oscillator, this frequency difference being measured in ppm (parts per million).
  • This frequency difference can be corrected, according to the inhibition technique, by the suppression of a number N of pulses of period T i during a determined period T h , called the inhibition period.
  • T i 122 ⁇ s
  • the number N will require at least 6 bits of memory. In practice, according to the application, this number may require between 4 and 9 bits.
  • the memory circuit 24 includes memory elements made up of fuses destructible by laser.
  • Figure 2a illustrates a first example of a 6-bit memory circuit comprising 6 elements memories 24.1 to 24.6 connected in parallel and comprising each a pair of fuses F1 and F2 destructible by laser. Fuses F1 and F2 of each memory element are connected in series between a potential line "high” Vdd and a potential line “low” Vss. The destruction of one of the F1 or F2 fuses thus allows set the intermediate point between the fuses F1, F2 at high potential Vdd or low Vss respectively.
  • the coding of information (number N) representative of the circuit division correction factor frequency divider 22 can thus easily be produced by means of a laser by destroying one or the other of the fuses F1 or F2.
  • Figure 2b shows a second example of a 6-bit memory circuit with 6 memory elements 24.1 to 24.6 each comprising a fuse F.1 to F.6 destructible by laser associated with an interface circuit L.1 to L.6.
  • the interface circuit L and fuse F are connected in series between a "high" potential line Vdd and a line of "low” potential Vss.
  • the interface circuit can be made by those skilled in the art in a way conventional in the form of a lock allowing to copy the input state defined by the fuse.
  • the lock further includes a CKP loading entry on activation of which a Lout output of the lock takes the corresponding state defined by the state of the associated fuse. In this case, the Lout output of the lock takes the state "high” if the fuse is destroyed and the state "low” if the fuse is intact.
  • Figure 2c presents yet another example of a 6-bit memory circuit.
  • This solution partially integrates frequency divider circuit inhibition logic 22.
  • Each transistor is controlled respectively by the clock signals of the six division stages of the frequency divider circuit 22 on which inhibition is carried out in accordance with this which has been described previously.
  • the transistor If the fuse is intact, the transistor is short-circuited and the clock signal at its input did not effect. If the fuse is destroyed, the transistor can then produce an effect on the inhibition of the circuit frequency divider 22. By the selective destruction of some fuses among fuses F.1 * to F.6 *, it is thus possible to adjust the inhibition rate of the circuit frequency divider 22.
  • destructible fuses by laser does not does not, however, directly impose itself as the solution more suitable for those skilled in the art. Indeed, the man of the profession faces various constraints and difficulties related to the use of destructible fuses by laser. In the following description, we will try to describe briefly these constraints and difficulties.
  • a first constraint resides in the fact that the use of a laser beam to destroy selectively the fuses on the integrated circuit involves that this operation must be carried out before the deposit of the protective resin on it. It is indeed not possible to destroy fuses at through the laser through the protective resin, which in this case should be transparent, as this would have the effect of completely annihilating the interest of such a deposit, in particular protection of the circuit integrated against ambient impurities and light.
  • the adjustment operation in particular the operation of measurement of the module's progress, is thus preferably performed under good lighting conditions determined.
  • the module's step adjustment process watchmaker requires a phase preparation before adjusting walking proper.
  • the preparation phase consists of beforehand implement the number of fuses necessary to allow information coding (number N) representative of the correction factor for the rate of division of the frequency divider circuit in accordance with which has been described previously.
  • This preparation phase also consists of mounting the various electronic components on the module, or in particular quartz and the integrated circuit without apply the protective resin on the integrated circuit (so-called "potting" operation).
  • the module is ready to undergo the actual adjustment operation.
  • the adjustment phase thus consists of measuring at by means of external equipment the operation of the module watchmaker, or to measure the difference in the frequency of the quartz oscillator with respect to the frequency of a standard oscillator as described above.
  • this measurement is preferably carried out under well-determined lighting conditions.
  • this correction factor is calculated. It will be recalled that this correction factor is determined by the calculation of a number N corresponding, in the case of an inhibition technique, to the number of pulses to be suppressed during a determined period T h .
  • the next step is to save information (number N) representative of the factor of calculated correction.
  • the watch module is aligned under a laser device.
  • the laser device is put into action to destroy selectively the fuses necessary for coding the information (number N) representative of the factor of correction.
  • the resin protective can then be deposited on the circuit integrated.
  • Stages subsequent to this adjustment phase, including a final step test step of the clock module are then executed.
  • the method of adjusting the rate of a module watchmaker according to the present invention thus turns out particularly suitable for mass production and the automation of such an operation.
  • the adjustment method according to the present invention allows thus a great simplification of the process of manufacturing and similarly a substantial gain in terms of manufacturing costs.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
EP19980121022 1998-11-05 1998-11-05 Verfahren zum Einstellen des Takts eines Uhrenmoduls mittels Schmelzen von Schmelzsicherungen per Laser Expired - Lifetime EP0999483B1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP19980121022 EP0999483B1 (de) 1998-11-05 1998-11-05 Verfahren zum Einstellen des Takts eines Uhrenmoduls mittels Schmelzen von Schmelzsicherungen per Laser
DE69840506T DE69840506D1 (de) 1998-11-05 1998-11-05 Verfahren zum Einstellen des Takts eines Uhrenmoduls mittels Schmelzen von Schmelzsicherungen per Laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19980121022 EP0999483B1 (de) 1998-11-05 1998-11-05 Verfahren zum Einstellen des Takts eines Uhrenmoduls mittels Schmelzen von Schmelzsicherungen per Laser

Publications (2)

Publication Number Publication Date
EP0999483A1 true EP0999483A1 (de) 2000-05-10
EP0999483B1 EP0999483B1 (de) 2009-01-21

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EP19980121022 Expired - Lifetime EP0999483B1 (de) 1998-11-05 1998-11-05 Verfahren zum Einstellen des Takts eines Uhrenmoduls mittels Schmelzen von Schmelzsicherungen per Laser

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EP (1) EP0999483B1 (de)
DE (1) DE69840506D1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2916193A1 (de) * 2014-03-06 2015-09-09 EM Microelectronic-Marin SA Zeitbasis, die einen Oszillator, eine Frequenzteilerschaltung und einen Schaltkreis zur Taktpulshemmung umfasst

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2349508A1 (de) * 1972-10-02 1974-04-18 Citizen Watch Co Ltd Elektronische uhr
US4345320A (en) * 1977-02-28 1982-08-17 Jean-Claude Berney Sa Integrated circuit for a time-piece
JPS5854705A (ja) * 1981-09-29 1983-03-31 Citizen Watch Co Ltd 調整端子の選択切断方法
JPS59138981A (ja) * 1983-01-28 1984-08-09 Seiko Epson Corp 電子腕時計用回路
EP0595629A1 (de) * 1992-10-28 1994-05-04 Kabushiki Kaisha Toshiba Abgleichschaltung
EP0645689A2 (de) 1993-09-29 1995-03-29 Seiko Epson Corporation Taktversorgungsystem, Echtzeittaktmodul und Taktgeber
WO1998034165A1 (en) * 1997-02-05 1998-08-06 Fox Enterprises, Inc. Worldwide marketing logistics network including strategically located centers for frequency programming crystal oscillators to customer specification

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2349508A1 (de) * 1972-10-02 1974-04-18 Citizen Watch Co Ltd Elektronische uhr
US4345320A (en) * 1977-02-28 1982-08-17 Jean-Claude Berney Sa Integrated circuit for a time-piece
JPS5854705A (ja) * 1981-09-29 1983-03-31 Citizen Watch Co Ltd 調整端子の選択切断方法
JPS59138981A (ja) * 1983-01-28 1984-08-09 Seiko Epson Corp 電子腕時計用回路
EP0595629A1 (de) * 1992-10-28 1994-05-04 Kabushiki Kaisha Toshiba Abgleichschaltung
EP0645689A2 (de) 1993-09-29 1995-03-29 Seiko Epson Corporation Taktversorgungsystem, Echtzeittaktmodul und Taktgeber
WO1998034165A1 (en) * 1997-02-05 1998-08-06 Fox Enterprises, Inc. Worldwide marketing logistics network including strategically located centers for frequency programming crystal oscillators to customer specification

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 007, no. 140 (E - 182) 18 June 1983 (1983-06-18) *
PATENT ABSTRACTS OF JAPAN vol. 008, no. 271 (P - 320) 12 December 1984 (1984-12-12) *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2916193A1 (de) * 2014-03-06 2015-09-09 EM Microelectronic-Marin SA Zeitbasis, die einen Oszillator, eine Frequenzteilerschaltung und einen Schaltkreis zur Taktpulshemmung umfasst
KR101731698B1 (ko) 2014-03-06 2017-04-28 이엠. 마이크로일레크트로닉-마린 쏘시에떼 아노님 발진기, 주파수 분주기 회로, 및 클록킹 펄스 억제 회로를 포함하는 타임 베이스
US9671759B2 (en) 2014-03-06 2017-06-06 Em Microelectronic-Marin Sa Time base including an oscillator, a frequency divider circuit and clocking pulse inhibition circuit

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Publication number Publication date
EP0999483B1 (de) 2009-01-21
DE69840506D1 (de) 2009-03-12

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