EP0978852A1

EP0978852A1 - Multilayer type chip inductor

Info

Publication number: EP0978852A1
Application number: EP99114703A
Authority: EP
Inventors: Nam Kee Kang; In Shig Park; Wook Lim; Chan Sei Yoo; Jong Dae Kim; Hyun Jong Ko; Sang Cheol Kim
Original assignee: Pilkor Electronics Ltd; Korea Electronics Technology Institute
Current assignee: Pilkor Electronics Ltd; Korea Electronics Technology Institute
Priority date: 1998-08-04
Filing date: 1999-07-27
Publication date: 2000-02-09
Also published as: KR20000013039A

Abstract

A multilayer type chip inductor includes a pair of outermost sheets having a terminal pattern, respectively, wherein the terminal patterns are, respectively, identical in shape, each terminal pattern including a via hole and being capable of providing various positions for the via hole for electrically connecting the terminal pattern to the various conductor patterns of the intermediate sheet.

Description

Field of the Invention

The present invention relates to a chip inductor; and, more particularly, to a multilayer type chip inductor employing a pair of outermost sheets having an identical terminal pattern in shape, respectively, the terminal pattern being capable of providing various positions for a via hole for electrically connecting the terminal pattern with conductor patterns of intermediate sheets.

Background of the Invention

In general, a multilayer type chip inductor is comprised of a stack of sheets made of a plurality of ferrite or dielectric materials, having respective coil patterned conductors formed thereon and connected electrically by the via holes in series with each other in substantially zigzag fashion. Such a multilayer type chip inductor is used, for example, for suppressing noise or making a LC resonance circuit.
Fig. 1 shows an exploded view of the conventional multilayer type chip inductor disclosed in Japanese Laid-open Utility Model Publication No. 57-100209.
As shown, the conventional multilayer type chip inductor includes a pair of generally rectangular outermost sheets 1, 1' made of the ferrite or the dielectric material and a plurality of intermediate sheets 2 made of the ferrite and dielectric material stacked one above the other and firmly sandwiched between the outermost sheets 1, 1'.
The outermost sheet 1 has a front surface formed with a generally L-shaped electric terminal pattern 6. The electric terminal pattern 6 has a lengthwise strip 6a extending along and adjacent to a longer side of the outermost sheet 1 and terminating at a generally intermediate portion of the longer side of the outermost sheet 1, and a lateral strip 6b continued to the lengthwise strip 6a and extending along a shorter side of the outermost sheet 1 for electric connection with an end cap or like terminal member (not shown).
Similarly, the outermost sheet 1' has at its front surface a generally L-shaped electric terminal pattern 6' composed of a lengthwise strip 6'a and a lateral strip 6'b, wherein, the terminal pattern 6' thereof is offset 180° with respect to the terminal pattern 6 on the outermost sheet 1 about an imaginary plane passing intermediately between the outermost sheets 1, 1' in a widthwise direction of the stack, and the lengthwise strip 6'a has at its end a via hole 4'. The via hole 4' is formed by perforating the outermost sheet 1' across the thickness thereof so as to leave a cylindrical wall (not shown).
Each of the intermediate sheets 2 has a front and a reverse surfaces opposite to each other. The front surface of each of the intermediate sheets 2 is, respectively, formed with a generally U-shaped electric conductor pattern 3. Each of the conductor patterns 3 has a perforated end 3a formed with a via hole 4 and a non-perforated end 3b. Similar to the above-mentioned via hole 4', the via hole 4 is formed by perforating the respective intermediate sheet 2 across the thickness thereof so as to leave a cylindrical wall (not shown). The above-mentioned cylindrical walls are plated with the conductive material.
When assembling the sheets 1, 2 and 1' together to provide a substantially complete multilayer type chip inductor, the intermediate sheets 2 are stacked one above the other in such a way that, when one intermediate sheet 2 is turned 180° on an imaginary plane parallel thereto, the perforated end 3a and the non-perforated end 3b thereof are, respectively, contacted with the non-perforated end 3b and the perforated end 3a of the neighboring intermediate sheet 2 thereabove or therebelow, whereby the intermediate sheets 2 can be electrically connected with each other through the via holes 4. With respect to the outermost sheets 1, 1', the outermost sheet 1 is positioned below the lowermost intermediate sheet 2 in such a way that the lengthwise strip 6a thereof comes into contact with the perforated end 3a of the lowermost intermediate sheet 2 through the via hole 4, and the outermost sheet 1' is positioned above the uppermost intermediate sheet 2 in such a way that the lengthwise strip 6'a thereof comes into contact with the non-perforated end 3b of the uppermost intermediate sheet 2 through the via hole 4' thereof, whereby the conductor patterns 3 on the intermediate sheets 2 and the terminal patterns 6, 6' on the outermost sheets 1, 1' are electrically connected with each other through the via holes 4, 4'.
In such a multilayer type chip conductor, since the outermost sheets are, respectively, formed with the terminal patterns requiring a different mask from each other, it results in a higher production cost and complicated manufacturing processes. Furthermore, when a different inductance is desired, the shape and/or the size of the conductor pattern of the intermediate sheet must also change, which, in turn, requires the shape and/or the size of the terminal pattern of the outermost sheets to be also changed so as to electrically connect the terminal pattern with the changed conductor pattern of the intermediate sheet, again necessitating a higher production cost and complicated manufacturing processes.

Summary of the Invention

It is, therefore, a primary object of the present invention to provide a multilayer type chip inductor which removes the need for forming different terminal patterns on its outermost sheets, when a different inductance is required therefrom.
In accordance with one aspect of the present invention, there is provided a pair of sheets having an identical terminal pattern, respectively, the terminal patterns being identical in shape, one of the terminal patterns being formed with a via hole filled with a conductive material for an electrical connection with the other thereof, wherein the sheets are arranged in such a way that when one of the sheets are turned 180° on an imaginary plane parallel thereto the terminal patterns of the sheets are allowed to be overlapped with each other, and the terminal patterns of the sheets are allowed to be electrically connected with each other through the via hole.
In accordance with another aspect of the present invention, there is provided a pair of outermost sheets having a terminal pattern, respectively, the terminal patterns being identical in shape, one of the terminal patterns being formed with a via hole filled with a conductive material, wherein the outermost sheets are arranged in such a way that, when one of the outermost sheets is turned 180° on an imaginary plane parallel thereto, the terminal patterns of the outermost sheets are allowed to be overlapped with each other, and a t least one intermediate sheets interposed between the outermost sheets and having a conductor pattern, respectively, the conductor patterns being identical in shape, each of the conductor patterns being formed with a via hole filled with a conductive material for an electrical connection with neighboring conductor patterns, wherein the intermediate sheets are stacked one above the other and sandwiched between the outermost sheets in such a way that, when one of the intermediate sheets is turned 180° on the imaginary plane the conductor patterns thereof are allowed to be overlapped with the conductor patterns of the neighboring intermediate sheets, and the terminal patterns of the outermost sheets and the conductor patterns of the intermediate sheets are allowed to be electrically connected with each other through their via holes.
In accordance with further another aspect of the present invention, there is provided a multilayer type chip inductor having at least one intermediate sheet formed with a conductor pattern thereon, comprising a pair of outermost sheets having a terminal pattern, respectively, wherein each of the terminal patterns includes a via hole for electrically connecting the terminal pattern to the conductor pattern of the intermediate sheet and is capable of providing various positions for the via hole so as to accommodate various conductor patterns of the intermediate sheet.

Brief Description of the Drawings

The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, wherein:
Fig. 1 shows an exploded perspective view of the conventional multilayer type chip inductor;
Fig. 2 illustrates an exploded perspective view of the multilayer type chip inductor in accordance with a first preferred embodiment of the present invention;
Fig. 3 displays an exploded perspective view of the multilayer type chip inductor in accordance with a second preferred embodiment of the present invention;
Fig. 4 provides an exploded perspective view of the multilayer type chip inductor employing an outermost sheet having a different terminal pattern in shape from that of the outermost sheet in Fig. 3;
Fig. 5 depicts an exploded perspective view illustrating a modified form of the chip inductor shown in Fig. 3; and
Fig. 6 presents an exploded perspective view setting forth a modified form of the chip inductor shown in Fig. 4.

Detailed Description of the Preferred Embodiments

There are provided in Figs. 2 to 6 a exploded perspective view of a multilayer type chip inductor in accordance with the present invention, respectively.
Referring to Fig. 2, a multilayer type chip inductor in accordance with a first preferred embodiment of the present invention includes a pair of sheets 10, 10' made of a ferrite and a dielectric material. Each of the sheets 10, 10' has a rectangular shape and a terminal pattern 12 having a substantially "T" shape thereon. Each of the terminal patterns 12 has a lateral strip 12a extending along a shorter side of the sheet 10 or 10', and a lengthwise strip 12b extending from a substantially intermediate portion of the length of the lateral strips 12a, along a longer side of the sheet 10 or 10', and terminating at a generally intermediate portion of the length of the sheet 10 or 10'. The sheet 10' has at its the lengthwise strip 12b a via hole 14 filled with a conductive material for an electrical connection with the sheet 10.
The sheets 10, 10' are assembled in such a way that, when one of the sheets 10, 10' are turned 180° on an imaginary plane parallel thereto, the terminal patterns 12 of the sheets 10, 10' are overlapped with each other. This allows the terminal patterns 12 of the sheets 10, 10' to be electrically connected with each other through the via hole 14.
Referring to Fig. 3, a multilayer type chip inductor in accordance with a second preferred embodiment of the present invention includes a pair of outermost sheets 20, 20' made of the ferrite and the dielectric material, and at least one intermediate sheets 30 made of the ferrite and the dielectric material and interposed between the outermost sheets 20, 20'.
Each of the outermost sheets 20, 20' has a rectangular shape and a terminal pattern 22 having a substantially "T" shape thereon. Similar to the terminal pattern 12 accordance with a first preferred embodiment of the present invention, the terminal pattern 22 of each of the outermost sheets 20, 20' has a lateral strip 22a and a lengthwise strip 22b. The outermost sheet 20' has at its the lengthwise strip 22b a via hole 24 filled with a conductive material for an electrical connection with the intermediate sheet 30 therebelow, as will be described in later.
The intermediate sheets 30 have a conductor pattern 32, respectively. The conductor patterns 32 are identical in shape, for example, ⊏-shape, respectively. The conductor pattern 32 of each of the intermediate sheets 30 has a perforated end 32a formed with a via hole 34 and a non-perforated end 32b. The via hole 34 is formed by perforating the respective intermediate sheet 30 across the thickness thereof and filled with a conductive material for an electrical connection with neighboring patterns, for example, the terminal pattern of the outermost sheet thereabove and the conductor pattern of the intermediate sheet therebelow, or the conductor patterns of the intermediate sheets thereabove and therebelow.
The outermost sheets 20, 20' are arranged in such a way that, when one of the outermost sheets 20, 20' is turned 180° on an imaginary plane parallel thereto, the terminal patterns 22 thereof are allowed to be overlapped with each other; and the intermediate sheets 30 are stacked one above the other and sandwiched between the outermost sheets 20, 20' in such a way that, when one of the intermediate sheets 30 is turned 180° on the imaginary plane, the conductor pattern 32 thereof is allowed to be overlapped with the conductor patterns of the neighboring intermediate sheets 30. To be more specific, when assembling the sheets 20, 20' and 30 together to provide a substantially complete multilayer type chip inductor, the intermediate sheets 30 are stacked in such a way that their perforated ends 32a and the non-perforated ends 32b are, respectively, contacted with the non-perforated ends 32b and the perforated ends 32a of the neighboring intermediate sheets 30 through the via holes 34. This allows the conductive patterns 32 of the intermediate sheets 30 to be electrically connected with each other. With respect to the outermost sheets 20, 20', the outermost sheet 20 is positioned below the lowermost intermediate sheet 30 in such a way that the lengthwise strip 22b thereof comes into contact with the perforated end 32a of the lowermost intermediate sheet 30 through the via hole 34 of the lowermost intermediate sheet 30, and the outermost sheet 20' is positioned above the uppermost intermediate sheet 30 in such a way that the lengthwise strip 22b thereof comes into contact with the non-perforated end 32b of the uppermost intermediate sheet 30 through the via hole 24 thereof. This allows the terminal patterns 22 on the outermost sheets 20, 20' and the conductor patterns 32 on the intermediate sheets 30 to be electrically connected with each other through the via holes 24, 34.
Although the above discussions were presented referring to a situation where the terminal pattern of the outermost sheet has the substantially "T" shape and the conductor pattern of the intermediate sheet has a ⊏-shape, their shapes and/or sizes can be changed depending on the desired inductance. For example, as shown in Fig. 4, the terminal patterns 22 of the outermost sheets 20, 20' may have a rectangular shape.
When a different inductance is required, the conductor pattern of the intermediate sheet must also change in the shape and/or the size. Unlike the prior art multilayer type chip inductor, the inventive multilayer type chip inductor can easily accommodate such a change. For example, as shown in Figs. 5 and 6, when the conductor pattern 32 of the intermediate sheet 30 increases in size in order to obtain an increased inductance, the location of the via hole 24 of the terminal pattern 22 can be changed suitably in such a way that the terminal pattern 22 of the outermost sheet 20' is electrically connected with the changed conductor pattern in the inventive multilayer type chip inductor. In other word, in the inventive multilayer type chip inductor, the terminal pattern of the outermost sheet can be electrically connected to various conductor patterns of an intermediate sheet by simply changing the position of the via hole, eliminating the need to change the shape and/or the size of the terminal pattern of the outermost sheet. Furthermore, in the inventive multilayer type chip inductor, since the outermost sheets include an identical terminal pattern in shape, respectively, it is possible to reduce a production cost and to facilitate manufacturing processes thereof.
While the present invention has been described with respect to certain preferred embodiments only, other modifications and variations may be made without departing from the scope of the present invention as set forth in the following claims.

Claims

A multilayer type chip inductor comprising :

a pair of sheets having an identical terminal pattern, respectively, the terminal patterns being identical in shape, one of the terminal patterns being formed with a via hole filled with a conductive material for an electrical connection with the other thereof, wherein the sheets are arranged in such a way that when one of the sheets are turned 180° on an imaginary plane parallel thereto the terminal patterns of the sheets are allowed to be overlapped with each other, and the terminal patterns of the sheets are allowed to be electrically connected with each other through the via hole.
The multilayer type chip inductor of claim 1, wherein each of the sheets has a rectangular shape and the terminal pattern thereof has a lateral strip extending along a shorter side of the sheet, and a lengthwise strip extending from an intermediate portion of the lateral strip, along a longer side of the sheet and terminating at a generally intermediate portion of the longer side of the sheet.
The multilayer type chip inductor comprising :

a pair of outermost sheets having a terminal pattern, respectively, the terminal patterns being identical in shape, one of the terminal patterns being formed with a via hole filled with a conductive material, wherein the outermost sheets are arranged in such a way that, when one of the outermost sheets is turned 180° on an imaginary plane parallel thereto, the terminal patterns of the outermost sheets are allowed to be overlapped with each other; and

at least one intermediate sheets interposed between the outermost sheets and having a conductor pattern, respectively, the conductor patterns being identical in shape, each of the conductor patterns being formed with a via hole filled with a conductive material for an electrical connection with neighboring conductor patterns, wherein the intermediate sheets are stacked one above the other and sandwiched between the outermost sheets in such a way that, when one of the intermediate sheets is turned 180° on the imaginary plane the conductor patterns thereof are allowed to be overlapped with the conductor patterns of the neighboring intermediate sheets, and the terminal patterns of the outermost sheets and the conductor patterns of the intermediate sheets are allowed to be electrically connected with each other through their via holes.
The multilayer type chip inductor of claim 3, wherein each of the outermost sheets has a rectangular shape and the terminal pattern thereof has a lateral strip extending along a shorter side of the sheet, and a lengthwise strip extending from an intermediate portion of the lateral strip, along a longer side of the outermost sheet and terminating at a generally intermediate portion of the longer side of the outermost sheet.
The multilayer type chip inductor of claim 3, wherein the terminal pattern of each of the outermost sheets has a substantially "T" shape.
The multilayer type chip inductor of claim 3, wherein the terminal pattern of each of the outermost sheets has a rectangular shape.
The multilayer type chip inductor of claim 3, wherein the conductor pattern of the intermediate sheet has a ⊏-shape.
A multilayer type chip inductor having at least one intermediate sheet formed with a conductor pattern thereon, comprising:

a pair of outermost sheets having a terminal pattern, respectively, wherein each of the terminal patterns includes a via hole for electrically connecting the terminal pattern to the conductor pattern of the intermediate sheet and is capable of providing various positions for the via hole so as to accommodate various conductor patterns of the intermediate sheet.
The multilayer type chip inductor of claim 8, wherein each of the outermost sheets has a rectangular shape and each of the terminal patterns has a lateral strip extending along a shorter side of the outermost sheet, and a lengthwise strip extending from an intermediate portion of the lateral strip, along a longer side of the sheet and terminating at a generally intermediate portion of the longer side of the sheet.
The multilayer type chip inductor of claim 9, wherein the terminal pattern has a substantially "T" shape.
The multilayer type chip inductor of claim 8, wherein each of the terminal pattern of the outermost sheets has a rectangular shape.