EP0973084A3 - Integrated circuit with a voltage regulator - Google Patents
Integrated circuit with a voltage regulator Download PDFInfo
- Publication number
- EP0973084A3 EP0973084A3 EP99113089A EP99113089A EP0973084A3 EP 0973084 A3 EP0973084 A3 EP 0973084A3 EP 99113089 A EP99113089 A EP 99113089A EP 99113089 A EP99113089 A EP 99113089A EP 0973084 A3 EP0973084 A3 EP 0973084A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- voltage
- voltage divider
- integrated circuit
- voltage regulator
- int
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000035945 sensitivity Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is DC characterised by reference voltage circuitry, e.g. soft start, remote shutdown
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Die integrierte Schaltung weist einen Spannungsregler (OP) zum Erzeugen einer internen Versorgungsspannung (VInt) auf, der einen Eingang zum Zuführen eines Istwertes und einen Eingang zum Zuführen einer Referenzspannung (VRef) als Sollwert aufweist. Der Istwert wird mittels eines ersten Spannungsteilers (R3, R4) aus der internen Versorgungsspannung (VInt) erzeugt. Die Empfindlichkeit des Spannungsreglers (OP) hängt vom Widerstandswert wenigstens eines Widerstandselementes (R3) des ersten Spannungsteilers ab. Dem ersten Spannungsteiler (R3, R4) ist ein zweiter Spannungsteiler (R1, R2) parallel geschaltet, der das gleiche Spannungsteilerverhältnis wie der erste Spannungsteiler aufweist und der durch wenigstens ein Schaltelement (S1, S2) aktivierbar und deaktivierbar ist. The integrated circuit has a voltage regulator (OP) for generating an internal supply voltage (V Int ), which has an input for supplying an actual value and an input for supplying a reference voltage (V Ref ) as a setpoint. The actual value is generated from the internal supply voltage (V Int ) by means of a first voltage divider (R3, R4). The sensitivity of the voltage regulator (OP) depends on the resistance value of at least one resistance element (R3) of the first voltage divider. A second voltage divider (R1, R2) is connected in parallel to the first voltage divider (R3, R4) and has the same voltage divider ratio as the first voltage divider and which can be activated and deactivated by at least one switching element (S1, S2).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19832309A DE19832309C1 (en) | 1998-07-17 | 1998-07-17 | Integrated circuit with voltage regulator |
| DE19832309 | 1998-07-17 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP0973084A2 EP0973084A2 (en) | 2000-01-19 |
| EP0973084A3 true EP0973084A3 (en) | 2000-04-05 |
| EP0973084B1 EP0973084B1 (en) | 2009-06-24 |
Family
ID=7874492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP99113089A Expired - Lifetime EP0973084B1 (en) | 1998-07-17 | 1999-07-06 | Integrated circuit with a voltage regulator |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6133779A (en) |
| EP (1) | EP0973084B1 (en) |
| DE (2) | DE19832309C1 (en) |
| TW (1) | TWM251161U (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2789190B1 (en) * | 1999-01-28 | 2001-06-01 | St Microelectronics Sa | POWER SUPPLY REGULATED AT A HIGH RATE OF NOISE REJECTION OF A SUPPLY VOLTAGE |
| US6300810B1 (en) * | 1999-02-05 | 2001-10-09 | United Microelectronics, Corp. | Voltage down converter with switched hysteresis |
| KR100351931B1 (en) * | 2000-05-30 | 2002-09-12 | 삼성전자 주식회사 | Voltage Detecting Circuit For Semiconductor Memory Device |
| US6351137B1 (en) * | 2000-08-15 | 2002-02-26 | Pulsecore, Inc. | Impedance emulator |
| US6479974B2 (en) | 2000-12-28 | 2002-11-12 | International Business Machines Corporation | Stacked voltage rails for low-voltage DC distribution |
| DE10354534A1 (en) | 2003-11-12 | 2005-07-14 | Atmel Germany Gmbh | Circuit arrangement for voltage detection |
| DE10360030A1 (en) * | 2003-12-19 | 2005-07-21 | Infineon Technologies Ag | Semiconductor memory with numerous memory cells addressable by word and bit lines, with at least two current generators, first generating preset current ono selected bit lines and/or preset word line with memory in active working mode |
| DE102004001577B4 (en) * | 2004-01-10 | 2007-08-02 | Infineon Technologies Ag | A semiconductor memory circuit and method of operating the same in a standby mode |
| KR100586545B1 (en) * | 2004-02-04 | 2006-06-07 | 주식회사 하이닉스반도체 | Oscillator power supply circuit of semiconductor memory device and voltage pumping device using same |
| US6956429B1 (en) * | 2004-02-09 | 2005-10-18 | Fairchild Semiconductor Corporation | Low dropout regulator using gate modulated diode |
| KR100596977B1 (en) * | 2004-08-20 | 2006-07-05 | 삼성전자주식회사 | A reference voltage generator circuit using both an external reference voltage and an internal reference voltage at the same time and a method of generating a reference voltage using the same |
| US9256239B2 (en) | 2011-03-17 | 2016-02-09 | Watlow Electric Manufacturing Company | Voltage controlling circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3105198A1 (en) * | 1981-02-13 | 1982-09-09 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Circuit arrangement for accurate setting of an electrical voltage |
| JPS60238915A (en) * | 1984-05-11 | 1985-11-27 | Ikegami Tsushinki Co Ltd | Constant current generation circuit |
| JPH0659413A (en) * | 1992-06-29 | 1994-03-04 | Eastman Kodak Co | Color photographic element and image forming method |
| US5467009A (en) * | 1994-05-16 | 1995-11-14 | Analog Devices, Inc. | Voltage regulator with multiple fixed plus user-selected outputs |
| EP0846996A1 (en) * | 1996-12-05 | 1998-06-10 | STMicroelectronics S.r.l. | Power transistor control circuit for a voltage regulator |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3516556B2 (en) * | 1996-08-02 | 2004-04-05 | 沖電気工業株式会社 | Internal power supply circuit |
| US6066979A (en) * | 1996-09-23 | 2000-05-23 | Eldec Corporation | Solid-state high voltage linear regulator circuit |
-
1998
- 1998-07-17 DE DE19832309A patent/DE19832309C1/en not_active Expired - Fee Related
-
1999
- 1999-06-30 TW TW092217352U patent/TWM251161U/en not_active IP Right Cessation
- 1999-07-06 EP EP99113089A patent/EP0973084B1/en not_active Expired - Lifetime
- 1999-07-06 DE DE59915043T patent/DE59915043D1/en not_active Expired - Lifetime
- 1999-07-19 US US09/356,811 patent/US6133779A/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3105198A1 (en) * | 1981-02-13 | 1982-09-09 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Circuit arrangement for accurate setting of an electrical voltage |
| JPS60238915A (en) * | 1984-05-11 | 1985-11-27 | Ikegami Tsushinki Co Ltd | Constant current generation circuit |
| JPH0659413A (en) * | 1992-06-29 | 1994-03-04 | Eastman Kodak Co | Color photographic element and image forming method |
| US5467009A (en) * | 1994-05-16 | 1995-11-14 | Analog Devices, Inc. | Voltage regulator with multiple fixed plus user-selected outputs |
| EP0846996A1 (en) * | 1996-12-05 | 1998-06-10 | STMicroelectronics S.r.l. | Power transistor control circuit for a voltage regulator |
Non-Patent Citations (2)
| Title |
|---|
| PATENT ABSTRACTS OF JAPAN vol. 010, no. 106 (P - 449) 22 April 1986 (1986-04-22) * |
| PATENT ABSTRACTS OF JAPAN vol. 1998, no. 07 31 March 1998 (1998-03-31) * |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0973084A2 (en) | 2000-01-19 |
| DE19832309C1 (en) | 1999-10-14 |
| US6133779A (en) | 2000-10-17 |
| TWM251161U (en) | 2004-11-21 |
| DE59915043D1 (en) | 2009-08-06 |
| EP0973084B1 (en) | 2009-06-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0973084A3 (en) | Integrated circuit with a voltage regulator | |
| DE2846675C3 (en) | Test device for displaying an electrical voltage and, if necessary, its polarity | |
| DE60022836T2 (en) | Speed control circuit for a DC motor | |
| DE102010045389A1 (en) | Power supply arrangement for driving electric load e.g. LED, has signal output that provides measurement signal used for measuring current value of driver signal and for adjustment of output voltage of load circuit | |
| DE202012103051U1 (en) | Circuit for driving light-emitting elements | |
| EP0901057A3 (en) | Current regulation circuit | |
| DE102006029190B4 (en) | Overcurrent detection device | |
| DE112005000986T5 (en) | DC Tester | |
| EP0401225B1 (en) | Circuit controlled flow probe | |
| EP1278402A1 (en) | Circuit for LED with temperature dependent current control | |
| DE3447002A1 (en) | CONSTANT CURRENT GENERATOR CIRCUIT | |
| DE3325044C2 (en) | Current regulator for an electromagnetic consumer in connection with internal combustion engines | |
| DE102019005029A1 (en) | LIGHT SOURCE DRIVER CIRCUIT, OPTICAL MEASURING DEVICE WITH THE LIGHT SOURCE DRIVER CIRCUIT, DEVICE FOR CHECKING VALUE DOCUMENTS, AND METHOD OF OPERATING A LIGHT SOURCE LOAD USING THE LIGHT SOURCE DRIVER CIRCUIT | |
| DE4401923B4 (en) | Energy supply system for scales | |
| DE102004007182B4 (en) | Charge pump circuit | |
| DE102013209670A1 (en) | A thermal flow sensor and method for generating a flow rate detection signal by the thermal flow sensor | |
| DE3036736C2 (en) | Circuit arrangement for the load-proportional setting of the control current of a single-ended output stage transistor of a transistor amplifier operated in an emitter circuit | |
| DE69507117T2 (en) | ADAPTABLE OUTPUT POWER DRIVER | |
| EP1433255B1 (en) | Control device | |
| DE102012100477C5 (en) | Shunt current measurement for multistring devices and interleaving converters | |
| DE1806375B2 (en) | IN THE FORM OF A TEST PIN DISPLAY DEVICE FOR SIGNAL LEVELS OF DIGITAL CIRCUITS | |
| DE4401728A1 (en) | Current balancing circuit | |
| DE3303945A1 (en) | Temperature-compensating circuit for a Hall generator power supply | |
| DE19621749A1 (en) | Circuit arrangement for generating a resistance behavior with adjustable positive temperature coefficient and use of this circuit arrangement | |
| DE4326282C2 (en) | Power source circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB IE IT |
|
| AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
| PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
| AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE |
|
| AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
| RIC1 | Information provided on ipc code assigned before grant |
Free format text: 7G 05F 1/575 A, 7G 05F 1/46 B |
|
| 17P | Request for examination filed |
Effective date: 20000818 |
|
| 17Q | First examination report despatched |
Effective date: 20001030 |
|
| AKX | Designation fees paid |
Free format text: DE FR GB IE IT |
|
| RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: INFINEON TECHNOLOGIES AG |
|
| GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
| GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
| GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
| AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB IE IT |
|
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
| REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: LANGUAGE OF EP DOCUMENT: GERMAN |
|
| REF | Corresponds to: |
Ref document number: 59915043 Country of ref document: DE Date of ref document: 20090806 Kind code of ref document: P |
|
| RAP2 | Party data changed (patent owner data changed or rights of a patent transferred) |
Owner name: QIMONDA AG |
|
| REG | Reference to a national code |
Ref country code: IE Ref legal event code: FD4D |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20090624 |
|
| PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
| GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20090924 |
|
| 26N | No opposition filed |
Effective date: 20100325 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20090924 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20090624 |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 17 |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R081 Ref document number: 59915043 Country of ref document: DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: TP Owner name: INFINEON TECHNOLOGIES AG, DE Effective date: 20160212 |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 18 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20160613 Year of fee payment: 18 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20160628 Year of fee payment: 18 |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 59915043 Country of ref document: DE |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST Effective date: 20180330 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20180201 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20170731 |
