EP0969512B1 - Inductive sensor - Google Patents

Inductive sensor Download PDF

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Publication number
EP0969512B1
EP0969512B1 EP98112052A EP98112052A EP0969512B1 EP 0969512 B1 EP0969512 B1 EP 0969512B1 EP 98112052 A EP98112052 A EP 98112052A EP 98112052 A EP98112052 A EP 98112052A EP 0969512 B1 EP0969512 B1 EP 0969512B1
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EP
European Patent Office
Prior art keywords
coil
transistors
transistor
collector
source
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EP98112052A
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German (de)
French (fr)
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EP0969512A1 (en
Inventor
Philippe Passeraub
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Asulab AG
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Asulab AG
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Priority to EP98112052A priority Critical patent/EP0969512B1/en
Priority to DE69840827T priority patent/DE69840827D1/en
Priority to TW088109838A priority patent/TW405250B/en
Priority to CNB991089251A priority patent/CN1169221C/en
Priority to US09/342,226 priority patent/US6194961B1/en
Priority to JP18334299A priority patent/JP4279409B2/en
Publication of EP0969512A1 publication Critical patent/EP0969512A1/en
Application granted granted Critical
Publication of EP0969512B1 publication Critical patent/EP0969512B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits

Definitions

  • the present invention relates generally to a microstructure comprising an integrated circuit in a substrate at a lower or upper face of which is arranged a planar coil, in particular a spirally wound coil galvanically deposited on a passivation layer provided on the surface of this coil. substrate. More particularly, the invention relates to an inductive sensor according to claim 1.
  • the document JP 08088324 shows a device comprising a coil and a field effect transistor (FET) which are arranged in such a way that the magnetic field generated by the coil is perpendicular to the source-drain direction of the FET and a Lorentz force acts on the electrons in the channel to confine the electrons in the channel and thus eliminate a short channel effect.
  • FET field effect transistor
  • the subject of the invention is an inductive sensor comprising an electronic circuit integrated in a semiconductor substrate and a planar coil formed by a conductive wire or a conductive track extending in a spiral. , this coil being arranged at an upper or lower face of this semiconductor substrate, said electronic circuit comprising a comparator having as input a first connection to a reference circuit and a second connection to said coil, said first and second connections being respectively connected to two control electrodes of two input transistors forming said comparator, these two input transistors being each formed by two regions respectively defining a source and a collector between which a current is generated as a function of the electrical state of the transistor in question, this inductive sensor being characterized in that at least the two input transistors are superimposed on the surface defined by said planar coil, and in that they are arranged so that said source and said collector of each of them are aligned in a direction substantially perpendicular to a portion of said conductive wire or conductive track which is located near the
  • the magnetic field generated by the plane coil is parallel to the alignment of the source and the collector of each of the two input transistors of the comparator which have a high sensitivity.
  • the electrons forming the electric currents flowing in these transistors between their sources and their collectors not undergoing a Lorentz force and, in the case of field effect transistors (FETs), the channel depth between the source and the collector is not affected by the presence of the coil superimposed on the electronic circuit integrated in the substrate serving to support this coil.
  • the inductive sensor 2 comprises a semiconductor substrate 4 in which is integrated an electronic circuit formed by a plurality of transistors 6. At an upper face of the substrate 4 is arranged a plane coil 10 and contact pads 12. A figure 2 the coil 14 is arranged on the upper surface 8 and is covered by a passivation or protection layer which has not been shown in FIG. figure 1 .
  • the coil 10 is formed by a conductive wire or track 14 which develops in a spiral. In the variant shown here, the coil 10 thus extends in a spiral on one and the same plane. However, it is possible to provide a planar coil arranged on several levels separated by passivation layers.
  • the coil may be obtained by various methods known to those skilled in the art, in particular by deposition of a metal layer under vacuum, as in the case of the figure 2 , or by a galvanic process, as for the embodiment variant shown in FIG. figure 3 .
  • the coil 10 defines a surface 16 (hatched surface of the figure 1 ).
  • the electronic circuit forming the sensor 2 is integrated in the substrate 4 inside the region 18 defined by a dashed line.
  • the surface 16 is located inside the region 18, in superposition according to a plan view from above ( figure 1 ). At least some transistors of the plurality of transistors forming the electronic circuit of the sensor 2 and the surface 16 defined by the coil 10 are superimposed on each other.
  • the transistors which have a high sensitivity by working at relatively low electric current, among the transistors superimposed on the surface 16, are arranged so that the source 20 and the collector 22 of each of them are aligned in a direction 24 corresponding to the direction of the electric current I generated in the transistor 6 between the source 20 and the collector 22 as a function of the electrical state of the transistor 6. This direction is perpendicular to the portion 26 of the conductive wire or track 14 located near this transistor 6.
  • the transistor 6 is a field effect transistor (FET) in which a channel 28 of variable depth is generated between the source 20 and the collector 22 as a function of the electrical state applied to the control electrode 30 defining the gate of this transistor 6.
  • FET field effect transistor
  • the source 20 and the collector 22 are respectively associated with two electrodes 32 and 34.
  • the current I flowing in the channel 28 is substantially parallel to the magnetic field B generated by the coil 10 at the channel 28.
  • the coil is spirally wound in rectilinear segments defining a square or rectangular profile at the winding of the coil.
  • four regions of the surface 16 can be defined in which the wire or metallized track 14 defines a set of linear segments parallel to each other.
  • the sensitive transistors of the integrated circuit are each superimposed on only one of these four regions, at a distance from the half-diagonals.
  • the direction of the magnetic field B passing through the transistor is thus well defined and substantially perpendicular to the direction of the linear segments of the wire or track 14. This ensures that the magnetic field B is substantially parallel to the electric current I in the transistor 6 of which the channel 28 is perpendicular to the portion 26 of the coil 10.
  • the electric wire 14 of the coil 10 is obtained in particular by a galvanic bath.
  • This wire 14 having a width L F of several micrometers ( ⁇ m).
  • the length L T of the transistor 6 is smaller than the width L F of the wire 14.
  • each transistor 6 of the set of transistors superimposed on the surface 26 defined by the coil 10 and having a large sensitivity are arranged so that each of them is located under the wire 14. Since the magnetic field produced by a single segment of the coil 10 is circular around this segment, the resulting magnetic field in the vicinity of this segment is substantially parallel to the direction defined by the channel 28 between the source 20 and the collector 22 of the transistor 6 located under the wire 14.
  • FIG. 4 represents the general electronic diagram of a differential relaxation oscillator comprising a reference circuit 40, a detection circuit 42 comprising the coil 10 electrically defined by an inductance L C and a resistor R C.
  • a comparator 44 has at its input a first connection 46 to the reference circuit 40 and a second connection 48 to the detection circuit 42.
  • the electronic circuit forming the comparator 44 which has cascaded current mirrors and cascaded amplification stages, is shown in greater detail.
  • the connections 46 and 48 are respectively connected to two control electrodes 50 and 52 of two input transistors 54 and 56.
  • These two input transistors 54 and 56 are particularly sensitive when working with electric currents. relatively weak.
  • at least these two transistors 54 and 56 are arranged in such a way that the direction of the electric current flowing in the channel between the source and the collector of these transistors is perpendicular to the direction of the wire of the coil located near the these transistors.
  • these two transistors 54 and 56 are arranged according to the preferred variant of the figure 3 .
  • the person skilled in the art can also arrange other transistors shown in FIG. figure 5 similarly to the input transistors 54 and 56, i.e. in an orientation defined by the present invention.

Description

La présente invention se rapporte d'une façon générale à une microstructure comprenant un circuit intégré dans un substrat à une face inférieure ou supérieure duquel est agencée une bobine plane, notamment une bobine en spirale déposée galvaniquement sur une couche de passivation prévue en surface de ce substrat. Plus particulièrement, l'invention concerne un capteur inductif selon la revendication 1.The present invention relates generally to a microstructure comprising an integrated circuit in a substrate at a lower or upper face of which is arranged a planar coil, in particular a spirally wound coil galvanically deposited on a passivation layer provided on the surface of this coil. substrate. More particularly, the invention relates to an inductive sensor according to claim 1.

Le document JP 08088324 montre un dispositif comprenant une bobine et un transistor à effet de champ (FET) qui sont disposés de manière à ce que le champ magnétique engendré par la bobine soit perpendiculaire à la direction source-drain du FET et une force de Lorentz agit sur les électrons dans le canal pour confiner les électrons dans le canal et ainsi éliminer un effet canal court.The document JP 08088324 shows a device comprising a coil and a field effect transistor (FET) which are arranged in such a way that the magnetic field generated by the coil is perpendicular to the source-drain direction of the FET and a Lorentz force acts on the electrons in the channel to confine the electrons in the channel and thus eliminate a short channel effect.

Dans le cadre de la présente invention, il a été prévu, afin de réduire au maximum les dimensions de la microstructure développée, de superposer au moins partiellement ladite bobine plane avec ledit circuit électronique susmentionné. Cependant, dans le cadre du développement de cette microstructure aux dimensions réduites, l'inventeur a observé que le champ magnétique engendré par la bobine plane avait une influence sur certains transistors sensibles du circuit électronique intégré sous la surface définie par la bobine plane. En particulier, les transistors sensibles sont ceux qui travaillent avec un courant relativement faible.In the context of the present invention, it has been provided, in order to minimize the dimensions of the developed microstructure, at least partially superimpose said planar coil with said aforementioned electronic circuit. However, in the context of the development of this microstructure with reduced dimensions, the inventor observed that the magnetic field generated by the plane coil had an influence on some sensitive transistors of the integrated electronic circuit under the surface defined by the plane coil. In particular, sensitive transistors are those that work with a relatively low current.

Pour répondre à ce problème détecté dans le cadre de la présente invention, l'invention a pour objet un capteur inductif comprenant un circuit électronique intégré dans un substrat semiconducteur et une bobine plane formée par un fil conducteur ou une piste conductrice s'étendant en spirale, cette bobine étant agencée à une face supérieure ou inférieure de ce substrat semiconducteur, ledit circuit électronique comprenant un comparateur ayant en entrée une première connexion à un circuit de référence et une deuxième connexion à ladite bobine, ces première et deuxième connexions étant reliées respectivement à deux électrodes de commande de deux transistors d'entrée formant ce comparateur, ces deux transistors d'entrée étant chacun formés par deux régions définissant respectivement une source et un collecteur entre lesquels un courant est engendré en fonction de l'état électrique du transistor considéré, ce capteur inductif étant caractérisé en ce qu'au moins les deux transistors d'entrée sont superposés à la surface définie par ladite bobine plane, et en ce qu'ils sont agencés de manière que ladite source et ledit collecteur de chacun d'eux sont alignés selon une direction sensiblement perpendiculaire à une partie dudit fil conducteur ou de ladite piste conductrice qui est située à proximité du transistor d'entrée considéré.In order to respond to this problem detected in the context of the present invention, the subject of the invention is an inductive sensor comprising an electronic circuit integrated in a semiconductor substrate and a planar coil formed by a conductive wire or a conductive track extending in a spiral. , this coil being arranged at an upper or lower face of this semiconductor substrate, said electronic circuit comprising a comparator having as input a first connection to a reference circuit and a second connection to said coil, said first and second connections being respectively connected to two control electrodes of two input transistors forming said comparator, these two input transistors being each formed by two regions respectively defining a source and a collector between which a current is generated as a function of the electrical state of the transistor in question, this inductive sensor being characterized in that at least the two input transistors are superimposed on the surface defined by said planar coil, and in that they are arranged so that said source and said collector of each of them are aligned in a direction substantially perpendicular to a portion of said conductive wire or conductive track which is located near the input transistor considered.

Grâce à ces caractéristiques, le champ magnétique engendré par la bobine plane est parallèle à l'alignement de la source et du collecteur de chacun des deux transistors d'entrée du comparateur qui présentent une grande sensibilité. Ainsi, les électrons formant les courants électriques circulant dans ces transistors entre leurs sources et leurs collecteurs ne subissant pas de force de Lorentz et, dans le cas de transistors à effet de champ (FET), la profondeur du canal entre la source et le collecteur n'est pas affectée par la présence de la bobine superposée au circuit électronique intégré dans le substrat servant de support à cette bobine.Thanks to these characteristics, the magnetic field generated by the plane coil is parallel to the alignment of the source and the collector of each of the two input transistors of the comparator which have a high sensitivity. Thus, the electrons forming the electric currents flowing in these transistors between their sources and their collectors not undergoing a Lorentz force and, in the case of field effect transistors (FETs), the channel depth between the source and the collector is not affected by the presence of the coil superimposed on the electronic circuit integrated in the substrate serving to support this coil.

La présente invention sera décrite ci-après plus en détail à l'aide des figures données à titre d'exemple nullement limitatif, dans lesquels :

  • la figure 1 est une vue en plan d'un capteur inductif selon l'invention;
  • la figure 2 est une vue en coupe selon la ligne II-II de la figure 1;
  • la figure 3 est une vue en coupe similaire à la figure 2 d'une variante préférée de réalisation de l'invention, et
  • les figures 4 et 5 sont deux schémas décrivant le circuit électronique d'un capteur inductif formé par un oscillateur à relaxation différentielle.
The present invention will be described hereinafter in more detail using the figures given by way of non-limiting example, in which:
  • the figure 1 is a plan view of an inductive sensor according to the invention;
  • the figure 2 is a sectional view along line II-II of the figure 1 ;
  • the figure 3 is a sectional view similar to the figure 2 a preferred embodiment of the invention, and
  • the Figures 4 and 5 are two diagrams describing the electronic circuit of an inductive sensor formed by a differential relaxation oscillator.

A l'aide des figures 1 et 2, on décrira ci-après un mode de réalisation général d'une microstructure selon l'invention. Le capteur inductif 2 comprend un substrat semiconducteur 4 dans lequel est intégré un circuit électronique formé par une pluralité de transistors 6. A une face supérieure du substrat 4 est agencée une bobine plane 10 et des plages de contact 12. A la figure 2, la bobine 14 est agencée sur la surface supérieure 8 et est recouverte par une couche de passivation ou de protection qui n'a pas été représentée à la figure 1.With the help of Figures 1 and 2 , hereinafter will be described a general embodiment of a microstructure according to the invention. The inductive sensor 2 comprises a semiconductor substrate 4 in which is integrated an electronic circuit formed by a plurality of transistors 6. At an upper face of the substrate 4 is arranged a plane coil 10 and contact pads 12. A figure 2 the coil 14 is arranged on the upper surface 8 and is covered by a passivation or protection layer which has not been shown in FIG. figure 1 .

La bobine 10 est formée par un fil conducteur ou une piste conductrice 14 qui se développe en spirale. Dans la variante représentée ici, la bobine 10 s'étend donc en spirale sur un seul et même plan. Toutefois, il est possible de prévoir une bobine plane agencée sur plusieurs niveaux séparés par des couches de passivation. La bobine peut être obtenue par divers procédés connus de l'homme du métier, notamment par dépôt d'une couche métallique sous vide, comme dans le cas de la figure 2, ou par un procédé galvanique, comme pour la variante de réalisation représentée à la figure 3.The coil 10 is formed by a conductive wire or track 14 which develops in a spiral. In the variant shown here, the coil 10 thus extends in a spiral on one and the same plane. However, it is possible to provide a planar coil arranged on several levels separated by passivation layers. The coil may be obtained by various methods known to those skilled in the art, in particular by deposition of a metal layer under vacuum, as in the case of the figure 2 , or by a galvanic process, as for the embodiment variant shown in FIG. figure 3 .

La bobine 10 définit une surface 16 (surface hachurée de la figure 1). Le circuit électronique formant le capteur 2 est intégré dans le substrat 4 à l'intérieur de la région 18 définie par un trait interrompu. La surface 16 est située à l'intérieur de la région 18, en superposition selon une vue en plan de dessus (figure 1). Au moins quelques transistors de la pluralité de transistors formant le circuit électronique du capteur 2 et la surface 16 définie par la bobine 10 sont superposés l'une aux autres. Selon l'invention, il est prévu qu'au moins l'ensemble des transistors (transistor 6 à la figure 2) qui présentent une grande sensibilité en travaillant à courant électrique relativement faible, parmi les transistors superposés à la surface 16, sont agencés de manière que la source 20 et le collecteur 22 de chacun d'eux sont alignés selon une direction 24 correspondant à la direction du courant électrique I engendré dans le transistor 6 entre la source 20 et le collecteur 22 en fonction de l'état électrique du transistor 6. Cette direction est perpendiculaire à la partie 26 du fil conducteur ou de la piste conductrice 14 située à proximité de ce transistor 6.The coil 10 defines a surface 16 (hatched surface of the figure 1 ). The electronic circuit forming the sensor 2 is integrated in the substrate 4 inside the region 18 defined by a dashed line. The surface 16 is located inside the region 18, in superposition according to a plan view from above ( figure 1 ). At least some transistors of the plurality of transistors forming the electronic circuit of the sensor 2 and the surface 16 defined by the coil 10 are superimposed on each other. According to the invention, it is provided that at least all of the transistors (transistor 6 at the figure 2 ) which have a high sensitivity by working at relatively low electric current, among the transistors superimposed on the surface 16, are arranged so that the source 20 and the collector 22 of each of them are aligned in a direction 24 corresponding to the direction of the electric current I generated in the transistor 6 between the source 20 and the collector 22 as a function of the electrical state of the transistor 6. This direction is perpendicular to the portion 26 of the conductive wire or track 14 located near this transistor 6.

Le transistor 6 est un transistor à effet de champ (FET) dans lequel un canal 28 d'une profondeur variable est engendré entre la source 20 et le collecteur 22 en fonction de l'état électrique appliqué à l'électrode de commande 30 définissant la grille de ce transistor 6. On remarquera que la source 20 et le collecteur 22 sont associés respectivement à deux électrodes 32 et 34. Selon l'invention, le courant I circulant dans le canal 28 est sensiblement parallèle au champ magnétique B engendré par la bobine 10 au niveau du canal 28. Ainsi, il n'y a quasi aucune force de Lorentz sur les électrons qui se déplacent entre la source et le collecteur du transistor.The transistor 6 is a field effect transistor (FET) in which a channel 28 of variable depth is generated between the source 20 and the collector 22 as a function of the electrical state applied to the control electrode 30 defining the gate of this transistor 6. It will be noted that the source 20 and the collector 22 are respectively associated with two electrodes 32 and 34. According to the invention, the current I flowing in the channel 28 is substantially parallel to the magnetic field B generated by the coil 10 at the channel 28. Thus, there is almost no Lorentz force on the electrons that move between the source and the collector of the transistor.

On remarquera à la figure 1 que la bobine est enroulée en spirale selon des segments rectilignes définissant un profil carré ou rectangulaire à l'enroulement de la bobine. Entre les quatre demi-diagonales 36, 37, 38 et 39, on peut définir quatre régions de la surface 16 dans lesquelles le fil ou la piste métallisée 14 définit un ensemble de segments linéaires parallèles entre eux. Ainsi, dans chacune de ces quatre régions, la direction perpendiculaire à celle du fil ou de la piste 14 est univoque. De préférence, les transistors sensibles du circuit intégré sont superposés chacun à l'une seulement de ces quatre régions, à une certaine distance des demi-diagonales. La direction du champ magnétique B traversant le transistor est donc bien définie et sensiblement perpendiculaire à la direction des segments linéaires du fil ou de la piste 14. On garantit ainsi que le champ magnétique B soit sensiblement parallèle au courant électrique I dans le transistor 6 dont le canal 28 est perpendiculaire à la partie 26 de la bobine 10.We will notice at the figure 1 that the coil is spirally wound in rectilinear segments defining a square or rectangular profile at the winding of the coil. Between the four half-diagonals 36, 37, 38 and 39, four regions of the surface 16 can be defined in which the wire or metallized track 14 defines a set of linear segments parallel to each other. Thus, in each of these four regions, the direction perpendicular to that of the wire or the track 14 is unambiguous. Preferably, the sensitive transistors of the integrated circuit are each superimposed on only one of these four regions, at a distance from the half-diagonals. The direction of the magnetic field B passing through the transistor is thus well defined and substantially perpendicular to the direction of the linear segments of the wire or track 14. This ensures that the magnetic field B is substantially parallel to the electric current I in the transistor 6 of which the channel 28 is perpendicular to the portion 26 of the coil 10.

A la figure 3 est représenté une variante de réalisation de l'invention formant un perfectionnement du premier mode décrit ci-avant. Le fil électrique 14 de la bobine 10 est obtenu notamment par un bain galvanique. Ce fil 14 présentant une largeur LF de plusieurs micromètres (µm). La longueur LT du transistor 6 est inférieure à la largeur LF du fil 14. Selon l'invention, il est prévu que chaque transistor 6 de l'ensemble des transistors superposés à la surface 26 définie par la bobine 10 et présentant une grande sensibilité sont agencés de manière que chacun d'eux est situé sous le fil 14. Etant donné que le champ magnétique produit par un seul segment de la bobine 10 est circulaire autour de ce segment, le champ magnétique résultant à proximité de ce segment est sensiblement parallèle à la direction définie par le canal 28 entre la source 20 et le collecteur 22 du transistor 6 situé sous le fil 14.To the figure 3 is shown an alternative embodiment of the invention forming an improvement of the first mode described above. The electric wire 14 of the coil 10 is obtained in particular by a galvanic bath. This wire 14 having a width L F of several micrometers (μm). The length L T of the transistor 6 is smaller than the width L F of the wire 14. According to the invention, it is provided that each transistor 6 of the set of transistors superimposed on the surface 26 defined by the coil 10 and having a large sensitivity are arranged so that each of them is located under the wire 14. Since the magnetic field produced by a single segment of the coil 10 is circular around this segment, the resulting magnetic field in the vicinity of this segment is substantially parallel to the direction defined by the channel 28 between the source 20 and the collector 22 of the transistor 6 located under the wire 14.

Aux figures 2 et 3, le courant électrique J circulant dans le fil 14 a été symbolisé par une croix dans un cercle.To the Figures 2 and 3 , the electric current J flowing in the wire 14 has been symbolized by a cross in a circle.

Aux figures 4 et 5 est représenté un schéma électronique correspondant à un mode de réalisation du circuit intégré du capteur 2. La figure 4 représente le schéma électronique général d'un oscillateur à relaxation différentiel comprenant un circuit de référence 40, un circuit de détection 42 comprenant la bobine 10 définie électriquement par une inductance LC et une résistance RC. Un comparateur 44 a en entrée une première connexion 46 au circuit de référence 40 et une deuxième connexion 48 au circuit de détection 42.To the Figures 4 and 5 there is shown an electronic diagram corresponding to an embodiment of the integrated circuit of the sensor 2. figure 4 represents the general electronic diagram of a differential relaxation oscillator comprising a reference circuit 40, a detection circuit 42 comprising the coil 10 electrically defined by an inductance L C and a resistor R C. A comparator 44 has at its input a first connection 46 to the reference circuit 40 and a second connection 48 to the detection circuit 42.

A la figure 5 est représenté plus en détail le circuit électronique formant le comparateur 44, lequel présente des miroirs de courant en cascade et des étages d'amplification en cascade. Les connexions 46 et 48 sont reliées respectivement à deux électrodes de commande 50 et 52 de deux transistors d'entrée 54 et 56. Ces deux transistors d'entrée 54 et 56 sont particulièrement sensibles en travaillant avec des courants électriques relativement faibles. Selon l'invention, au moins ces deux transistors 54 et 56 sont agencés de manière que la direction du courant électrique circulant dans le canal entre la source et le collecteur de ces transistors est perpendiculaire à la direction du fil de la bobine situé à proximité de ces transistors. De préférence, ces deux transistors 54 et 56 sont agencés selon la variante préférée de la figure 3.To the figure 5 The electronic circuit forming the comparator 44, which has cascaded current mirrors and cascaded amplification stages, is shown in greater detail. The connections 46 and 48 are respectively connected to two control electrodes 50 and 52 of two input transistors 54 and 56. These two input transistors 54 and 56 are particularly sensitive when working with electric currents. relatively weak. According to the invention, at least these two transistors 54 and 56 are arranged in such a way that the direction of the electric current flowing in the channel between the source and the collector of these transistors is perpendicular to the direction of the wire of the coil located near the these transistors. Preferably, these two transistors 54 and 56 are arranged according to the preferred variant of the figure 3 .

Lors de l'établissement du plan du circuit intégré, l'homme du métier peut également agencer d'autres transistors représentés à la figure 5 de manière similaire aux transistors d'entrée 54 et 56, c'est-à-dire selon une orientation définie par la présente invention.When establishing the integrated circuit plan, the person skilled in the art can also arrange other transistors shown in FIG. figure 5 similarly to the input transistors 54 and 56, i.e. in an orientation defined by the present invention.

Claims (3)

  1. Inductive sensor (2) including an electronic circuit integrated in a semiconductor substrate (4) and a flat coil (10) formed by a conductive wire (14) or a conductive path (14) extending in a spiral, this coil being arranged on an upper (8) or lower face of said semiconductor substrate, said electronic circuit including a comparator (44) having at its inputs a first connection (46) to a reference circuit (40) and a second connection (48) to said coil (10), these first and second connections being respectively connected to two control electrodes (50, 52) of two input transistors (54, 56) of said comparator, each of these two input transistors being formed by two regions defining respectively a source (20) and a collector (22) between which a current (I) is generated as a function of the electric state of the transistor, this inductive sensor being characterised in that at least the two input transistors and the surface (26) defined by said flat coil (10) are superposed, and in that they are arranged so that said source and said collector of each of them are aligned along a direction approximately perpendicular to a portion of said conductive wire or said conductive path situated in proximity to the respective input transistor so that the magnetic field (B) generated by said flat coil (10) is substantially parallel to the direction defined by the source (20) and the collector (22) of this respective input transistor.
  2. Sensor according to claim 1, characterised in that said input transistors are formed by field effect transistors (FET).
  3. Sensor according to claim 1 or 2, characterised in that each input transistor is substantially arranged under a portion of said wire (14) or said path of said coil (10).
EP98112052A 1998-06-30 1998-06-30 Inductive sensor Expired - Lifetime EP0969512B1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP98112052A EP0969512B1 (en) 1998-06-30 1998-06-30 Inductive sensor
DE69840827T DE69840827D1 (en) 1998-06-30 1998-06-30 Inductive sensor
TW088109838A TW405250B (en) 1998-06-30 1999-06-11 Microstructure including a circuit integrated in a substrate on one surface of which is arranged a flat coil
CNB991089251A CN1169221C (en) 1998-06-30 1999-06-29 Microstructure including circuit integrated in substrate on one surface of which is arranged flat coil
US09/342,226 US6194961B1 (en) 1998-06-30 1999-06-29 Microstructure including a circuit integrated in a substrate on one surface of which is arranged a flat coil
JP18334299A JP4279409B2 (en) 1998-06-30 1999-06-29 Microstructure containing circuitry integrated on a substrate with a flat coil on the surface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP98112052A EP0969512B1 (en) 1998-06-30 1998-06-30 Inductive sensor

Publications (2)

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EP0969512A1 EP0969512A1 (en) 2000-01-05
EP0969512B1 true EP0969512B1 (en) 2009-05-13

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EP (1) EP0969512B1 (en)
JP (1) JP4279409B2 (en)
CN (1) CN1169221C (en)
DE (1) DE69840827D1 (en)
TW (1) TW405250B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759746B1 (en) * 2000-03-17 2004-07-06 Robert Bruce Davies Die attachment and method
US6864558B2 (en) * 2001-05-17 2005-03-08 Broadcom Corporation Layout technique for C3MOS inductive broadbanding
US7148553B1 (en) 2001-08-01 2006-12-12 Davies Robert B Semiconductor device with inductive component and method of making
US6999339B2 (en) * 2003-04-22 2006-02-14 Micron Technology, Inc. Integrated circuit including sensor to sense environmental data, method of compensating an MRAM integrated circuit for the effects of an external magnetic field, MRAM integrated circuit, and method of testing
WO2004102665A1 (en) * 2003-05-14 2004-11-25 Ericsson Technology Licensing Ab High-density circuits that include inductors
JP2005006153A (en) * 2003-06-13 2005-01-06 Nec Electronics Corp Voltage controlled oscillator
US7268409B2 (en) * 2004-05-21 2007-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Spiral inductor with electrically controllable resistivity of silicon substrate layer
DE102005050484B4 (en) * 2005-10-21 2010-01-28 Atmel Automotive Gmbh Monolithically integrated circuit arrangement
US7622910B2 (en) * 2006-10-06 2009-11-24 Honeywell International Inc. Method and apparatus for AC integrated current sensor
JP5442950B2 (en) 2008-01-29 2014-03-19 ルネサスエレクトロニクス株式会社 Semiconductor device, manufacturing method thereof, signal transmission / reception method using the semiconductor device, and tester device
CN111430372B (en) * 2020-03-31 2022-08-02 厦门天马微电子有限公司 Array substrate, display panel and display device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4157563A (en) * 1971-07-02 1979-06-05 U.S. Philips Corporation Semiconductor device
JPS60182175A (en) * 1984-02-28 1985-09-17 Matsushita Electronics Corp Semiconductor device for signal switching
DE3727142C2 (en) * 1987-08-14 1994-02-24 Kernforschungsz Karlsruhe Process for the production of microsensors with integrated signal processing
JPH0377360A (en) * 1989-08-18 1991-04-02 Mitsubishi Electric Corp Semiconductor device
WO1994017558A1 (en) * 1993-01-29 1994-08-04 The Regents Of The University Of California Monolithic passive component
US5416356A (en) * 1993-09-03 1995-05-16 Motorola, Inc. Integrated circuit having passive circuit elements
JP3400853B2 (en) * 1994-04-27 2003-04-28 三菱電機株式会社 Semiconductor device
JPH0888324A (en) * 1994-09-19 1996-04-02 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
WO1996013859A1 (en) * 1994-10-28 1996-05-09 Siemens Aktiengesellschaft Solid-state switching element with two source electrodes and solid-state switch with such an element
US5483207A (en) * 1994-12-30 1996-01-09 At&T Corp. Adiabatic MOS oscillators
JPH09200031A (en) * 1996-01-19 1997-07-31 Canon Inc Complementary transistor output circuit
US5952893A (en) * 1998-03-06 1999-09-14 International Business Machines Corporation Integrated circuit inductors for use with electronic oscillators

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TW405250B (en) 2000-09-11
JP4279409B2 (en) 2009-06-17
US6194961B1 (en) 2001-02-27
CN1169221C (en) 2004-09-29
JP2000031384A (en) 2000-01-28
DE69840827D1 (en) 2009-06-25
CN1242605A (en) 2000-01-26
EP0969512A1 (en) 2000-01-05

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