Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/35—Switches specially adapted for specific applications
  • H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/20—Support for services
  • H04L49/201—Multicast operation; Broadcast operation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/25—Routing or path finding in a switch fabric
  • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
  • H04L49/254—Centralised controller, i.e. arbitration or scheduling
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L49/00—Packet switching elements
  • H04L49/50—Overload detection or protection within a single switching element
  • H04L49/505—Corrective measures
  • H04L49/506—Backpressure

Definitions

• This invention relates generally to forwarding data packets in a computer network device, and more particularly to limiting forwarded packets to desired packets.
• MAC Medium Attachment Unit
• Ethernet type network devices such as repeaters, bridges, and routers offer different degrees of sophistication in their handling of incoming data packets. Repeaters typically receive a
• Bridges and routers typically have memory, store
• Bridges typically receive data packets having a the lower level data link layer address of an
• Routers typically receive data packets having the lower level data link layer address of the
• the router then forwards the data packet based upon interpreting the higher level address
• a repeater which forwards data packets from a first Ethernet collision domain to a second
• Ethernet collision domain while filtering packets so as to eliminate unnecessary packets from
• the repeater asserts a signal line informing the other ports that the data packet may be ignored by them, and the addressed po ⁇ receives the data packet for transmission onto the Ethemet collision domain connected thereto.
• a switch to transfer data packets between a plurality of Ethemet collision domains has a
• Each po ⁇ of the plurahty of po ⁇ s is connected to an Ethemet collision domain
• a first po ⁇ of the plurality of ports is a means for a first po ⁇ of the plurality of ports to receive a data packet from the Ethemet collision domain connected thereto, and for the first po ⁇ to write a destination address from a
• the switch also has a means for the second po ⁇ to maintain a valid bit in association with
• the register the valid bit being either set or clear; a means for placing the valid bit in the set
• the switch has a means for mamtaining a flood bit, the flood bit having a set
• Fig. 1 is a sketch of a building having a computer network using hubs installed therein.
• Fig. 2 is a block diagram of a hub.
• Fig. 3 is a the block diagram of a computer network using hubs.
• Fig. 4 is a field diagram of an Ethemet packet.
• Fig. 5 is a field diagram of a control packet of the invention.
• Fig. 6 is a Table.
• Fig. 7 A is an introductory bit sequence for a standard data packet.
• Fig. 7B - Fig. 7G are introductory bit sequences for a control packet.
• Fig. 8A is a block of a switched repeater having multiple segments in a bus and using BREP chips.
• Fig. 8B is a block diagram of a repeater having one segment bus hardwired to a plurahty of BREP
• Fig. 9 is a block diagram of a switched repeater system using BREP chips.
• Fig. 10 is a block diagram of signal pathways in a switched repeater using BREP chips.
• Fig. 11 is a block diagram of a BREP chip showing off-chip signal pathways.
• Fig. 12 is a block diagram of a BREP chip.
• Fig. 13 is a flow cha ⁇ for internal address filtering.
• Fig. 14 a block diagram for connection of an extemal CAM to a system using BREP chips for the purpose of address filtering.
• Fig. 15 is a block diagram showing flow control counters.
• Fig. 16 is flow control diagram for establishing half duplex flow control for a link that is capable
• Fig. 17 is a flow control diagram for establishing full duplex flow control for a link that is capable
• Fig. 18 is a flow control diagram for establishing full duplex flow control for a link that is not
• Fig. 19 is the management code flow diagram for establishing full-duplex flow control when the
• Fig. 20 is a timing diagram for the transmit buffer ready signal.
• FIG. 1 there is shown a building 100 having a computer network 101
• the building 100 is shown in a three dimensional transparent representation, with network components visible through transparent walls, with landscaping 150, and with
• the network is interconnected by
• a hub is made up of one or more Semiconductor Buffered Repeater
• BREP chips each having a buffered repeater architecture, and interconnected by a switch
• a hub can suppo ⁇ several local area networks, LAN.
• each LAN is a separate Ethemet collision domain. Traffic is switched between LANs by the hub.
• a wide area network connection enters the building as a cable 110, illustrated as a cable 110 strung on poles 112. Cable 110 attaches to router 114. Cable 110 can
• optical fibers can be, for example, a bundle of several optical fibers, can be coaxial cables, can be telephone wires,
• Router 114 connects to a po ⁇ of hub 108.
• a second wide area network connection enters the building through an antenna 120
• Antenna 120 connects to router 124. Antenna 120 can
• a satellite can be in communication with a satellite, can be a link in a microwave transmission path, can be a link
• Router 124 connects to a po ⁇ of hub 102.
• the building computer network 101 includes routers 114, 124, hubs 102, 104, 106, 108,
• the building network is connected to repeater 140.
• the building network is connected to wide area networks through, for example, antenna 120 and cable 110. Additionally, for example, building
• network 101 may include bridges, ATM switches, and so forth. And the network includes the
• Repeater 140 is shown connected to a po ⁇ of hub 104.
• Workstations 141, 142, 143, 144 are shown connected to a po ⁇ of hub 104.
• FIG. 2. there is shown a block diagram of the internal architecture of hub 202.
• the hub is a switched repeater, refe ⁇ ed to as a SREP repeater.
• the SREP repeater uses
• each BREP chip provides four (4) Ethemet po ⁇ s.
• chip 204A has Ethemet po ⁇ s 204A-1, 204 A-2, 204 A-3, 204A-4. Each of these Ethemet po ⁇ s
• each of the BREP chips 204A, 204B...204N in hub 202 has four Ethemet po ⁇ s, as shown in Fig. 2.
• BREP chips 204A is an independent collision domain operating in accordance with the
• CSMA/CD carrier sense multiple access with collision detection
• each port provides an independent collision domain.
• BREP chip 204A there is a workstation connected to Ethemet ports 204A-1, 204A-2,
• Ethemet port 204A-2 is connected to Ethemet repeater 205, and Ethemet repeater 205 is in tum connected to a plurality of workstations indicated as PCI ... PCN.
• 204B is illustrated by having the ports 204B-1, 204B-3, and 204B-4 connected to workstations,
• PCI - PCN workstations
• BREP chip 204C is indicated as connected to workstations at Ethemet po ⁇ s 204C-1,
• router 207 connects to
• BREP chip 204(N-1) connects to four workstations. And finally, by way of example, BREP chip 204N is shown
• Ethemet Repeater 208 at port 254. Ethemet Repeater 208 is then connected to a plurality of
• hub 202 connects to an independent collision domain as illustrated above: sometimes to a single
• Ethemet repeaters 205 206 208 workstation; sometimes to an Ethemet repeater illustrated as Ethemet repeaters 205 206 208, and
• router 207 a router 207
• network cloud 207-1 connecting to a wide area network as illustrated by network cloud 207-1.
• the BREP chip has a Media Independent Interface (MLT) ports or symbol ports that
• Physical Layer (Phy) device for example, for operation at either 10
• the BREP chip can be connected to, for example, a Symbol Phy device for operation at 100 mega-bits per second.
• the PHY device is connected to the physical media using one bit datapath for receive operation, and one bit datapath for transmit operation.
• the BREP chip may be connected to a variety of physical layer devices as
• each Ethemet port has a transmit buffer and a receive
• transmit buffer rectangle will be referred to as a transmit buffer.
• receive buffers are the individual "transmit and receive" buffers.
• Data associated with Ethemet port 204A-1 is stored in "transmit and receive" buffer 210.
• Data associated with Ethemet port 204A-2 is stored in "transmit and receive" buffer 212.
• Ethemet port 204A-4 is stored in "transmit and receive" buffer 216.
• Data stored in a “transmit and receive” buffer may be waiting to be transmitted out through its associated Ethemet port, or it may have been received from the Ethemet port.
• Each Ethemet po ⁇ of a BREP chip can be associated to any one of the 4 segment ports,
• Ethemet port 204A-1 has the associated segment port 220.
• Ethemet po ⁇ 204A-2 has associated
• Ethemet port 204A-3 has associated segment port 224.
• Each of the segment ports may be eight (8) bits
• Each segment po ⁇ of a BREP chip is independent of the other segment po ⁇ s.
• the hub 202 contains, for example, four (4) segment busses 230, 232, 234, 236. Each of
• segment busses has, for example, an eight-bit wide data path.
• a segment bus may have any number of BREP segment po ⁇ s attached thereto. Each BREP chip po ⁇ may be associated with
• any one of the segment busses through control within the BREP chip, and in response to
• Access to the segment bus 230, 232, 234, 236 is controlled by an arbitration mechanism
• arbitration lines (not shown) for operating the arbitration mechanism, and clock lines
• buffers 210, 212, 214, 216 in BREP chip 204A are
• each buffer has both a transmit
• receive" buffer 210 is drained by the data being transmitted through Ethemet port 204A-1 onto
• segment bus 230 is shown attached to: the segment ports of BREP chip 204A at segment po ⁇ 222 and segment po ⁇ 224; to BREP chip 204B at segment port 204B- Sl; to BREP chip 204C at segment po ⁇ 204C-S1 and segment port 204C-S3; and, to BREP chip
• segment bus 230 is connected to BREP chip 204N at its segment port 204N-3.
• Segment buses 232, 234, and 236 are shown by way of example, connected to various ports of BREP chip 204A through BREP chip 204N.
• segment bus 230 connects, through the BREP chips, to LANs which are
• the messages are transmitted from a first collision domain by being received at
• receive buffer is then drained onto the corresponding segment bus and is broadcast to all BREP
• the data is loaded into a segment port transmit buffer after
• Filtering may permit loading of the packet by one or more BREP chip segment po ⁇ s.
• the packet may be a multicast packet; or for example, the packet may be a broadcast packet.
• Reception of the packet is based on address filtering by the BREP chips.
• the transmit buffers receiving the packet are then drained by the packet being transmitted through the associated
• Each Ethemet port 204A-1, 204 A-2, 204A-3, 204A-4 operates with its associated
• Ethemet port 204A-1 connects to "transmit and receive” buffer 210, and "transmit and receive”
• buffer 210 connects to segment port 220;
• Ethemet port 204A-2 connects to "transmit and receive” buffer 212, and "transmit and receive”
• buffer 212 connects to segment port 222;
• Ethemet port 204A-3 connects to "transmit and receive” buffer 214, and "transmit and receive”
• buffer 214 connects to segment port 224;
• Ethemet port 204A-4 connects to "transmit and receive” buffer 216, and "transmit and receive”
• buffer 216 connects to segment port 226.
• segment ports then connect, by way of example, to the segment busses 230, 232, 234, 236 as follows:
• segment port 220 connects to segment bus 236;
• segment port 222 connects to segment bus 230;
• segment port 224 connects to segment bus 230;
• segment po ⁇ 226 connects to segment bus 232.
• segment bus 234 does not connect to any segment port of BREP chip
• segment busses 230, 232, 234, 236 are labeled by the mega-bits per second (10 or 100) which their associated Ethemet ports, and also extemal Ethemet collision domains 235
• segment bus is done by switch engine 240.
• Switch engine 240 by way of example, is shown
• Segment bus 230 is shown connecting to switch engine
• Segment bus 232 is shown connecting to switch engine port 250.
• segment bus 232 connects: to BREP chip 204A at segment port 226; to BREP chip 204B at segment port 204B-S4; to BREP chip 204C at segment port 204C-S4; and, to BREP chip 204N at segment po ⁇ 204N-S4.
• switch engine 240 to switch engine port 250, and then onto segment bus 232. From segment bus 232 the Ethemet packet is broadcast to all of the segment ports of the BREP
• segment bus 232 including for example, segment port 204N-4 of BREP chip
• Ethemet repeater 208 From Ethemet repeater 208 the packet is broadcast to PCI, PC2, ... PCN.
• PCI PC2, ... PCN.
• segment bus 230 is shown in Fig. 2 to be operating at 10 megabits per
• Segment bus 230 connects to: BREP chip 204A at segment port 222 and segment port 224; BREP chip 204B at segment port 204B-1; BREP chip 204C at segment port 204C-1 and
• each local area network which is an Ethemet collision domain, attached to an Ethemet po ⁇ co ⁇ esponding to one of these segmen t
• po ⁇ s is operated at 10 megabits per second, including the aforementioned LAN attached to
• Switch engine port 250 is shown operating at 100 megabits per second, as
• segment bus 232 Accordingly, all LANs attached to Ethemet ports having their co ⁇ esponding segment port attached to segment bus 232 operate at 100 megabits per second, including the
• Ethemet packets to be transferred between LANs having different operating bit rates.
• a packet will next be traced from the Ethemet LAN of BREP chip 204A at Ethemet port 204A-2 to
• the receive buffer 212 is filled at a 10 megabit per second rate.
• the packet is drained from the receive buffer 212 at the segment bus rate, and the packet enters switch engine
• switch engine 240 at switch engine port 246.
• the packet is switched by switch engine 240 from switch engine
• transmit buffer 252 of BREP chip 204N at the segment bus clock rate.
• the complete packet is stored in transmit buffer 252.
• Transmit buffer 252 is then drained at 100 megabits per second by transmission through Ethemet port 254 onto the 100 megabit per second LAN where it
• repeater 208 goes to repeater 208.
• the packet is repeated by repeater 208 at the 100 megabits per second bit rate to the workstations PCI - PCN attached to repeater 208.
• the packet is stored into receive buffer 252 of BREP chip 204N at a 100 megabit per second
• Switch engine 240 then provides a connection from its port 250 to its port 246 for the
• Ethemet packet having a destination address on Ethemet port 204A-2 The data is broadcasted at the bus clock rate from BREP chip 204N to transmit buffer 212 of BREP chip 204A.
• transmit buffer 212 is then drained at the lower 10 megabit per second rate as the packet is
• switched repeater 202 a packet entering switch repeater 202 and having a destination address which can be reached by
• switch engine 240 need not be switched by switch engine 240. That is, a single segment bus is connected to the
• switch engine 240 will switch the Ethemet packet to a segment bus having an apparatus with the
• FIG. 3 there is shown a more complex network 300 including four (4) hubs.
• the network shown in Fig. 3 could serve as the building network 101 of Fig.
• hub 302 is connected by link 303 to hub 304, and also hub 302 is connected by link
• Hub 306 is connected by link 307 to hub 308.
• Link 303, 305, and 307 may be
• link 303, 305, 307 could be twisted
• the networks connected to each hub are complex, as is illustrated by the connection of
• Ethemet repeater 312 is connected to port 314 of hub 302.
• Ethemet repeater 312 is connected to a
• repeater 320 is connected to port 322 of hub 302. Repeater 320 is in tum connected to a plurality
• port 326 is connected to router 328.
• Router 328 is in
• repeater 332 is connected to port 324 of hub 304. Repeater
• 332 is in tum connected to a plurality of workstations 334 ... 336.
• hub 306 at Ethemet port 341 connects to repeater 340.
• Repeater 340 is connected to a plurality of workstations 342 ... 344.
• Hub 308 is connected at port 346 to repeater 348.
• Repeater 348 is then connected to a plurality of workstations 349 ... 350.
• Hub 308 is connected at port 352 to repeater 354.
• Repeater 354 is connected to a plurality of workstations 374 ...375. Also, by way of example,
• router 360 is connected to router 360.
• router 360 is in tum connected to a
• FIG. 3 by way of example, illustrates hub 302, 304, 306, 308, having ports connected to a wide variety of apparatus.
• hub 302 is connected to a plurality of independent
• Reference numeral 370 is used to designate independent workstations attached to various of the hubs 302, 304, 306 and 308. Each independent workstation 370 is on a different
• hubs 302, 304, 306, 308 are
• routers 328, 360 are connected to other hubs: for example, hub 302 connects to hub
• hub 302 connects to hub 306 through link 305; and, hub 306 connects
• a data packet will be traced from a source
• workstation 316 connected through
• repeater 312 to hub 302, transmits a message having the destination address of workstation 374, connected through repeater 354 at port 352 to hub 308.
• Workstation 316 transmits the data
• 320, 332, 340, 348, and 354 operates as follows: a repeater receives a packet on one port
• repeater 312 broadcasts the
• Receive buffer 376 of BREP chip 378 receive buffer 376 of BREP chip 378. Receive buffer 376 is then drained through segment bus
• Segment bus 379 connects to switch engine port 380 of switch engine 382.
• Switch engine 382 interprets the destination address of the packet, and accordingly, switches the packet to its port 384.
• BREP chip 385 loads the packet at its segment port 386.
• Transmit buffer 387 is drained by
• Receive buffer 390 is drained by the packet being broadcast onto
• engine 394 interprets the destination address of the packet and switches the packet to its po ⁇ 395.
• Transmit buffer 399 is
• Link 307 conducts the packet to BREP chip 402, where the packet is written into receive buffer 404 of BREP chip 402.
• Receive buffer 404 is drained by broadcast of the packet onto segment bus 406. Segment bus 406
• BREP chip 410 connects, in turn, to segment port 408 of BREP chip 410.
• BREP chip 410 loads the packet, in response to the destination address of the packet, at its segment port 408, and the packet is written into transmit buffer 412 of BREP chip 410.
• Transmit buffer 412 of BREP chip 410 is
• Repeater 354 transmits the packet to all of the workstations connected to repeater
• FIG. 4 there is illustrated a standard Ethemet packet of the type described in the Ethemet Standard ANSI/IEEE Standard
• Preamble 450 is a seven (7) byte field.
• Field SFD 452 is a one (1) byte field.
• Field DA 454 is the destination address field of the packet and is a six (6) byte field, where
• the field holds the address of the destination workstation.
• Field SA 456 is the source address field of the packet and is a six (6) byte field, where the
• Field “Length” 458 gives the length of the data field of the packet and is a two (2) byte field in LEEE 802.3 packet format indicating length from 0 to 1500 decimal.
• LeEE 802.3 packet format indicating length from 0 to 1500 decimal.
• LeEE 802.3 packet format indicating length from 0 to 1500 decimal.
• LeEE 802.3 packet format indicating length from 0 to 1500 decimal.
• LeEE 802.3 packet format indicating length from 0 to 1500 decimal.
• “Ethernet format” length field 458 is a protocol type field having a "value" > 1500 decimal.
• Data field 460 is a field having variable length, where the length is specified by the number in field 458 in IEEE 802.3 format.
• PAD field 459 is all zeros and forces the packet length to be 64 bytes, and is present when the data is insufficient to make the packet 64 bytes long. Accordingly, the PAD field may be of
• the length field 458 specifies the length of the data exclusive of
• FCS 462 is the frame control sequence field and is four (4) bytes in length.
• Apparatus constructed in accordance with the Ethemet standard is normally designed to
• a control packet 500 for use in automatic detection of the type of apparatus attached to a po ⁇ of a BREP chip.
• Fields of the control packet include the preamble field 502 which is a seven (7) byte field.
• Field SFZ 504 is a one (1) byte field. Details of field SFZ 504 will be discussed
• the invention permits a BREP chip to recognize that a received packet came from a device having the capabilities of a BREP chip.
• the destination address field 454 is labeled with the same reference numeral as
• Source address field 456 is labeled with the same
• Length/Type field 506 in a preferred embodiment of the invention, is used as a TYPE
• the TYPE field is programmable, so a special TYPE value
• OpCode field 510 carries an operations code recognized by a receiving port of a BREP
• the op-code field is programmable, and for an exemplary embodiment of the invention the op-codes of the following table may be used.
• Credit field 512 carries credit for use in a credit based flow control mechanism which may be established between a first hub having a BREP chip and a second hub connected to a port of
• Padding field 514 contains sufficient bytes to make the control packet 64 bytes in length.
• padding field 514 contains forty-two (42) bytes.
• FCS field 462 the frame control
• Fig. 6 is a table giving the fields of control packet 500. In the control packet, the total
• the padding of 42 bytes is used to ensure that the length of the control packet is sufficient so that it is not a mnt packet.
• Fig. 7A through Fig. 7G there is shown: the content of preamble field
• a standard preamble 702 is shown in Fig. 7A. Also, in Fig. 7A, a standard SFD 452 byte is shown in field 704. It is noted that the standard preamble 702 is made up of seven (7) identical
• the apparatus recognizes that the destination address field 454 immediately follows the "11"
• control packet 708 is identical with the standard preamble 702 shown in Fig. 7A. However, the
• SFZ byte 504 shown in Fig. 7B as field 710, is as follows:
• the BREP chip is designed to recognize the SFZ byte 710 after receipt of at least fifty-six (56) bits of repeating " 10" of the standard preamble 702. Upon detection by the Ethemet port of
• the BREP chip interprets the packet as a control packet.
• BREP chip port is connected in turn to another BREP chip port. This guarantee flows from the
• ports of a BREP chip may have any number
• a repeater 312, 320, 340, 332, 348 for example: a repeater 312, 320, 340, 332, 348,
• a router 328, 360 is illustrated as attached to a port of a BREP chip; a router 328, 360 is illustrated as
• BREP chip attached to a port of a BREP chip; and two BREP chips are illustrated as being connected
• No forwarding apparatus such as a bridge, router or switching hub, etc. will forward a packet having a SFZ field, and no workstation will transmit a packet having a SFZ field.
• po ⁇ has determined that it is connected to another BREP chip po ⁇ , as for example by link 303, 305, or 307.
• Advanced repeater designs may check a packet for a SFD pattem before forwarding the packet.
• a repeater functionality is described in the Standard LEEE 802.3u Chap 27,
• Chap. 27 repeater In the event that the Chap. 27 repeater always looks for a SFD sequence before repeating a packet, then the Chap. 27 repeater will not repeat a packet having a SFZ byte in the
• repeater must be excluded from a network using BREP chips, as such a simple repeater will
• the BREP chip interprets the fields of the packet containing the SFZ
• the receiving port of the BREP chip then interprets field 510 as an operations code, and interprets field 512 as a credit containing field for operation of credit based flow control
• the receiving chip can take action based upon that determination.
• Examples of action that can be taken include: establishment of full duplex transmission between
• Fig. 7C there is a standard preamble 712. However, a
• BREP receiving chip detects a control packet 500 by detecting the presence of a standard
• preamble followed by an SFZ byte 714.
• a standard preamble 716 there is a standard preamble 716.
• a different SFZ byte is used, where the SFZ byte 718 is 10001010.
• the receiving port of the BREP receiving chip detects a control packet 500 by detecting the presence of a standard preamble, followed by an SFZ byte 718.
• the preamble 720 is non-standard and the SFD byte is the standard SFD byte.
• the SFD byte is the standard SFD byte.
• the seventh byte 774 is non-standard.
• Byte 774 is 10100010.
• the receiving port of the BREP receiving chip detects a control packet 500 by detecting the presence of a non-standard preamble having byte 774, followed by a standard SFD byte 772.
• the receiving port of the BREP receiving chip detects a control packet 500 by detecting
• non-standard preamble 780 and SFZ byte 784 avoid using bit combinations which place two "1" symbols together, as "11" because a receiving apparatus could inte ⁇ ret a " 11" pair
• receiving device would begin receiving a packet, starting with the destination address, which in
• the introductory bit sequence comprising the preamble 450 and Start Frame Delimiter
• the ⁇ introductory-bit-sequence> is the two sequences: ⁇ preamblexsfd>.
• the frame format is:
• the preamble is at least seven (7) bytes of " 10101010".
• the sfd byte is the pattem: " 10101011 ".
• the sfz byte which replaces the sfd byte.
• the sfz byte which replaces the sfd byte.
• a large number of non-standard bit patterns in the ⁇ introductory-bit-sequence> may be
• non standard sequences replacing the sfd sequence may be used, such as, replace the sfd with any one of the following:
• a non-standard preamble may be
• the number of preamble bits sourced ensures an adequate number of bits are provided to each system component to correctly implement its function.
• the introductory bit sequence is needed for the receiving apparatus to initialize to the incoming packet.
• the preamble is defined by the standard at paragraphs 4.2.5, and 7.2.3.3, and 22.2.3.2.1 is
• standard preambles may include the any of the following altemative patterns for any one of the seven (7) bytes of the preamble:
• a control packet length was chosen as the minimum allowed packet length of 64 bytes, so
• the fragment will be a mnt packet.
• a runt packet is rejected by any apparatus receiving it. Accordingly, the random occurrence of the control packet introductory bit sequence in a data field of a control
• a repeater chip having both a receive buffer and a transmit buffer is described. Because of
• the chip is referred to as a Buffered Repeater chip, or
• a BREP chip An example of a chip which inco ⁇ orates the invention described herein is the Digital Equipment Co ⁇ oration product, Digital Semiconductor 21340 10/100-Mb/s Ethemet
• REO 2] is the REQ signal for the fast Ethemet po ⁇ number 2 of the BREP chip.
• Angled brackets denote the bit subscripts for a bus of more than one signal. For example,
• DATA ⁇ 7> is the most significant bit in the DATA ⁇ 7:0> bus.
• a packet is received from the physical media into one of the BREP MACs.
• a packet is transmitted by one of the BREP MACs to the Fast Ethemet physical side.
• One of the BREP MACs broadcasts a received packet towards the other MACs onto the local bus.
• Other MACs load this broadcasted packet from the local bus into their TX FIFO.
• LPG - inter packet gap A time gap between packets.
• the LPG may be 0.96
• Preamble - a stream of bits preceding the start of a frame transmission, and usually
• the preamble is defined as 7 consecutive
• SFD - start frame delimiter a sequence of bits following the preamble and which marks
• a packet is loaded to the sender TX_FIFO.
• a BREP based repeater eliminates network length restrictions, by transforming each of the connected segments into a distinct collision domain handled on the repeater side by a fully
• Each collision domain is an Ethemet local area
• the BREP MACs implement a smart backpressure
• the BREP provides support for network segmentation, where any combination
• the BREP is PHY media independent, and thus allows building repeaters for 100BASE-TX, 100BASE-T4, Fiber or any mix of the above media.
• the appropriate MAC chip is used for the desired PHY.
• Each BREP port can be programmed to support various levels of interconnect. It can be
• NM media independent interface
• lOOBase-X lOOBase-X
• PCS physical coding sublayer
• each BREP port can be programmed to work in either data
• Goals of the design which are accomplished in the within disclosure include the following:
• the design for example, does not necessarily
• One expansion port to cascade up to 16 BREP chips, summing up to 64 po ⁇ s in one box ;
• FIG. 8A there is shown a Switched Repeater SREP using a plurality of
• BREP chips Multiple segment busses are shown.
• a switch engine having a plurahty of ports is
• the switch engine shown has three 100 megabit per second ports and one
• BREP ports 10 megabit per second ports.
• a variety of BREP ports are shown attached to each segment bus. The attachment of BREP ports to a segment bus can be changed dynamically by the SREP
• Fig. 8B there is shown a repeater having a plurality of BREP chips with
• Ethemet LANs must operate at the same data rate, for example either at 10 megabits per second
• the segment bus then operates at the chosen megabit per
• Fig. 8B The repeater arrangement of Fig. 8B may be conveniently employed when it is
• FIG. 9 there is shown a system overview giving the signal connections in a switched repeater, SREP, using BREP chips.
• a plurality of BREP chips are shown, designated
• Each BREP chip has four ports, indicated as MH Port 0, M ⁇
• Port 1 Mil Port 2, and Mil Port 3.
• Each port is connected to a PHY device. Examples of a
• PHY device include National Semiconductors product DP8340, and also ICS product PHY 1890.
• each BREP chip has the following signal lines connected thereto: GNT for grant, REQ for request, TX_FLFO_RDY to indicate that the transmit FIFO
• a management unit is
• each BREP chip has connected thereto the following signal lines: MGMNT PDATA,
• Fig. 10 there are shown signaling pathways in a switched repeater, SREP,
• Parallel bus 1010 carries the segment busses. Each segment
• bus has an eight line data bus PDATA ⁇ 7:0>, a four line control bus CNTL ⁇ 1:0>, a strobe STRB,
• the parallel bus 1010 connects to the switch
• Switch engine 1012 performs the function of bridging a packet from a first segment
• FIG. 11 there is shown a block diagram of the intemal structure of a BREP chip 1102.
• Control unit 1110 in response to signals received over the extemal busses, controls
• the segment bus connects through the segment bus
• Management signals connect through the management interface 1124.
• Po ⁇ 1112 is shown, in block diagram form, having a receive FIFO buffer 1130 and a receive machine 1134.
• a packet is received on line 1136 the packet is first processed by
• receive machine 1134 From receive machine 1134 the packet is loaded into the buffer of receive
• receive FIFO 1130 is broadcast onto the eight bit wide bus of segment bus 1122.
• po ⁇ 1112 has a a transmit FIFO buffer 1140; and a transmit machine 1142.
• control unit 1110 permits, the buffer in transmit FLFO 1140 is loaded from the eight bit segment
• transmit FIFO 1140 is transmitted by transmit machine 1142 onto line 1144 of the associated
• each of the other Ethemet ports 1113, 1114, and 1115 have intemal
• the transmit machine 1 144 and receive machines 1134, and their counte ⁇ a ⁇ s implement the Medium Access Control (MAC) function for their respective po ⁇ s.
• MAC Medium Access Control
• FIG. 12 there is shown a block diagram of the intemal structure of a
• Fig. 12 gives, in addition to the structures shown in Fig. 11, signal designations
• Segment bus 1122 brings in the lines: strobe STRB 1220 signal; the eight bit data pathway PDATA ⁇ 7:0>; the four line control CNTL ⁇ 3:0>
• the Arbitration Interface 1120 brings in the lines: four request lines REQ[0:3]; four
• the Management Interface 1124 brings in the lines: MDOUT; MDLN; MCLX; and MCS.
• the interfaces implemented may include the Medium Independent Interface (Mil) for use with, for example, 10 mega-bit per second Ethemet or with 100 mega-bit per
• the port 1112 may implement a Symbol interface for
• each port of the BREP chip 1102 implements standard MAC functions for the port's Ethemet collision domain.
• the column marked # gives the number of signal pins used in the chip.
• Port[i] request signal to an external arbiter. Asserted when RX FIFO[i] indicates that a packet is received from the media. Tri-State signal, driven when ARB_ENA is asserted
• Tri-State signal driven when ARB_ENA is asserted
• Tri-State signal driven when ARB_ENA is asserted.
• ARB ENA BREP-Arbiter enable signal When asserted, the BREP drives RE [3:0],
• Used for packet broadcasts including starting/ending packet delimiter information.
• the PData bus is shared among all
• a preamble pattern is transmitted on the data lines as default.
• the granted port drives preamble and SFD patterns onto PDATA ⁇ 7:0>.
• the data packet is driven on the data bus by the broadcasting port
• the granted port drives the following data: chip_id, port_id, receive status
• the CNTL lines are common to all the connected BREPs and the arbiter. When not driven, the CNTL lines are pulled up to (idle) .
• PKT_ABORT_L 1/ Packet abort bit [3:0] O Enabled only when enable_packet_abort control bit is set (OPM[i]16>) Determines if the current loaded packet should be aborted before transmission. When working in internal address filtering mode, it is shared among all ports segments. When not driven it is pulled up.
• STRB [3:0] 1/ STRB signal is 12.5 MHZ clock sourced
• the STRB signal is pull-down to '0'.
• the MDIN signal is common for all connected BREPs .
• the MDOUT signal is common for all the connected BREPs.
• the MCLK Management clock is between 0 to 12 . 5 MHZ .
• MII_CS_RXD/SYM_ Receive Data are driven by the PHY[i], 16 RXD[3 :0] ⁇ 3:0> synchronous with MII_CS_RCLK [i ⁇
• MII_DV[3:0]/ 1/ In Mil mode Input pin - Receive Data LINK_ACTIVITY O Valid; Driven by the PHY[i ⁇ [3:0]
• In PCS mode Output pin - A status pin that provides a LED that indicates either receive, or transmit activity.
• MII_CS_RCLK/ Receive Clock Provides the timing SYM_RCLK [3:0] reference for the transfer of MII_DV[i], Ml ' l_CS_RXD[i] and MII_CS_ERR[i] signals
• MII_CS_ERR[3:0] Receive Error; Is driven by the PHY[i] ; Indicating that an error has occurred
• MII_TX_ER[3:0] O RESERVED at this stage of the design. Transmit Coding Error,
• MII_CS_TCLK/ Transmit Clock - Provides the timing SYM_TCLK [3:0] reference for the MII_TXEN[i], MII_CS_TXD[i] , and TX_ER[i] signals
• MII_CS_TCLK/SYM I Transmit Clock - Provides the timing _TCLK [3:0] reference for the MII_TXEN[i], MII_CS_TXD[i] , and TX_ER[i] signals
• MII_TXEN/SYM_ 0 In Mil mode: Indicates that nibbles on TXD ⁇ 4>[3:0] the Mil are presented for transmission.
• PCS Mode Transmit data together with the four transmit lines MII ⁇ SYM_TXD ⁇ 3 : 0> provide five parallel lines of data in symbol form. This data is synchronized to the MIL/SYM_TCLK signal.
• MII_CLSN/SYM_ In Mil mode Collision Detected.
• PCS mode Receive data, together with MIL/SYM_RXD ⁇ 3 :0> provide five parallel lines of data in symbol form.
• Output pin - A status pin that provides a LED that indicates a signal detection activity and that the port's scrambler has been locked. When this pin is not supported by the PHY device, it should connect to VSS.
• Port isolation indicators When set, indicates that the appropriate port is isolated. (Either partitioning, Jabber, False carrier isolation, or isolation during remote node identification process) .
• the mode of operation is controlled by
• Each of the four BREP MACs comprises a 4KB Rx FIFO.
• a BREP port is able to receive a new packet, when one of the foUowing conditions are met: At least 1664 bytes are free;
• the remote sender uses the BREP's flow control scheme and has enough credits to send a new packet.
• the BREP port filters incoming packets that are shorter then 6 bytes.
• the port w ⁇ l request the opportunity to start broadcasting this packet, when polled by
• the BREP port In store & forward operation, the BREP port will request the opportunity to start
• the BREP port receives and broadcasts legal packets, corrupted packets, mnt packets and
• the BREP port only broadcasts runt frames generated by other devices transmission
• the receiving port flushes the remaining bytes and terminates the packet with a 'packet-long' indication.
• Each of the four BREP MACs comprises a 2KB Transmit FIFO. Loaded runt packets with length smaller then 11 bytes are filtered and are not transmitted to the
• BREP ⁇ ort[i] indicates its ability to load a new packet by asserting TX_FIFO_RDY[i].
• a BREP po ⁇ is able to load a new packet in store & forward operation or in cut-through operation if at least 1664 bytes are free. In cut-though operation the port can load a packet if
• the loaded packet is being transmitted and has passed the collision window (64 Bytes were already transmitted without incurring a collision).
• a special (programmable) back off limit is used whenever the BREP po ⁇ 's RX FIFO is
• the broadcasting po ⁇ drives the chip_id, po ⁇ id, receive_packet_ status and receive_packet_ length on the PDATA[i] ⁇ 7:0> lines, while driving the End_Frame code on the CNTL ⁇ 1:0> lines.
• the granted po ⁇ drives its 12.5 MHZ clock on the STRB[i] line for the whole
• the destination po ⁇ s latch the PDATA and CNTL lines at the assertion of STRB.
• the PDATA, CNTL and STRB lines are propagated outside the BREP chip, such that packets can be broadcast both "from” and “to” other BREP chips.
• a BREP port is able to filter out
• the BREP port uses a simple
• the BREP port stores the last valid source address received from its remote node in a
• the BREP port notifies other BREP ports sharing the same segment to abort the currently broadcasted packet by pulling down the
• Broadcast and Multicast packets are always forward to remote end nodes, unless
• PKT_ABORT_L signal deasse ⁇ ion is detected.
• V_bit V_bit
• F_bit Flood_bit
• Table 5 gives the values of the V-bit and the F-bit, and the action which the values lead to.
• each BREP port In order to verify that the source address stored in its uni_address_register is still valid, each BREP port maintains Tl timer and Valid-bit (V-bit).
• Tl timer is set
• V-bit is set
• uni_address_register stores the packet's source
• Each BREP port needs to identify if it is connected to a single end station or to multiple
• Each port maintains in addition to the Valid_bit, T2 timer and Flood_bit
• valid_packet_received Ethemet or 802.3 packet with vahd length and correct FCS.
• Fig. 13 there is shown a flow chart for setting the valid bit V_bit, the flood bit F_bit, the timer Tl, and timer T2.
• the system is initialized.
• block 1302 the system is initialized.
• V_bit is cleared and the F_bit is set. In the event that a valid address is detected on a
• timer Tl is set, and the system goes to block 1322.
• the system goes to block 1322.
• source address field of die packet detected at block 1312 is compared with the contents of
• register uni_address_reg, mat is with the source address of the packet received at block 1306.
• T2 is checked. In the event that T2 has expired, the system returns along path 1330 to block 1312. In the event that T2 has not expired, the system goes to block 1332. At block 1332 the F bit F_bit is cleared. The system then returns along path 1330 to block 1312.
• V_bit defines if the address stored
• F_bit is set to "1", meaning the port is assumed to be connected to more than one
• the port tries to identify if it is connected to one or more end-stations (through a repeater or
• the port sets F_bit to "0" when it detects that it is connected only to one station, otherwise the value of F_bit remains “1".
• F_bit is set to "0" in order to indicate that the port is connected to only one station, then the value of the V_bit must be at "1" to
• the port having its F_bit set to "0" is the only port having the destination station attached to its Ethemet local area network.
• FIG. 14 a blcck diagram of operation with an external Content
• PKT_ABORT_L[i] is an output from the extemal CAM logic to each of the BREP segment
• the CAM after initialized by the management agent, detects the destination address field while the packet is being broadcasted onto a segment bus and compares it to its CAM content
• the BR P's management agent performs: learning; address table management operations like addition and removal of addresses; and, aging.
• the BREP port When less then 1664 byte transfer of RX_FIFO are free and the remote node is unable to use the BREP's flow control data transfer scheme, the BREP port enters backpressure mode.
• the backpressure idea is to deliberately generate a carrier activity on the physical link in
• the BREP implements two different algorithms for backpressuring the physical link-.
• this packet is used for backpressuring. Otherwise, if the TX FIFO is empty, the BREP
• the BREP port defers, waits for the minimal IPG (0.96 sec) and retries transmission. However, during the whole
• the BREP port maintains a backoff limit of 0. This ensures that the remote node delays the successful transmission it is trying to achieve.
• a TX packet may be loaded into the port.
• the port should start backpressuring with this TX packet instead of a BP packet as soon as
• Tne port therefore strips the currently transmitted BP packet (but not less than 64
• Destination Address Programmable value (As programmed in DAI [TJ, DA2[i] registers)
• Source Address My_Source_ Address (As programmed in SA1 [I].
• SA2[i] registers Type BP (Programmable value)
• BP packets contain no real information. They are used only to keep the media busy.
• a BREP port receiving such packets from a remote BREP port filters them out
• the packet filtering is done based on the BP packet
• a BREP port uses a unique
• the BREP's flow control scheme is a "credit based" scheme. Credits are sent in a
• the local receiver Upon receiving a new legal credit packet from the remote node, the local receiver extracts the credit information,
• the sender keeps the remote receiver credit value in its "byte count” counter.
• the sender is allowed to transmit a new packet when either:
• the sender decrements its Byte_Count for every byte it sends.
• the sender updates
• a valid credit packet is a packet which format is described below in the section " Flow Control Packet Format", with a
• the receiver traces the remote sender Byte_Count in order to determine when to
• Value_ sent counter traces the remote sender byte_ count.
• the value_ sent counter is loaded with the updated (RX_FIFO_size counter - FCTL _ Delay) value which is the credit
• FCTL-Delay takes into account the following delays: Round trip delay;
• the receiver generates new credit packets in the following cases:
• the generated credit packet has priority in transmission over loaded TX packets.
• the BREP port When the BREP port receives a flow control packet from a remote node, it extracts its
• the BREP port then filters out these packets and does not broadcast them
• BREP port 1 1502 transmits packets to BREP port 2 1504 under the control of "flow control".
• BREP port 1 1502 may be in an end station, may be in a SREP repeater, or may be in
• receiving port 1504 receives packets from the transmit FIFO 1510 of transmitting port 1502, and
• the receive FIFO 1508 is drained by broadcast of the packets it receives onto the segment bus
• the value sent block 1520 keeps track of the size of the receive FIFO 1508, the number of bytes contained in receive FIFO 1508, the number of bytes authorized in previously sent credit
• value sent block 1504 determines that another "flow control packet" 1506 can be sent with an authorization for transmit FIFO 1510 to send a determined number of bytes to receive FIFO 1508, then a "flow control packet" 1506 is sent from the receiving port 1504 to the transmitting port 1502. The determined number of bytes which can be sent by transmit FIFO 1510 is included
• control packet is given in the foUowing table.
• the Flow Control Packet has a length of 64 bytes, and so the padding is set at 42 bytes to
• Source Address My_Source_Address (Programmable value)
• Type Programmable value
• the Flow control initialization process is controUed by the management unit.
• the flow control auto detection idea is to check if the remote node is able to perform the BREP's flow control scheme.
• the BREP port requires from its PHY device the foUowing capabilities: ML! TX PHY:
• Mil PHY Physical interface
• the management unit finds out, through the
• the management unit sets the BREP's mode of
• FCTL FCTL
• the BREP port notifies the management unit and the BREP port halts its flow control initialization process
• the management unit When the management unit detects FCTL failure, the management unit re-estabhshes the
• FIG. 16 there is shown a flow chart giving the steps required to identify
• the remote node capabilities in the case that the local PHY device is MJJ T4 PHY.
• the management code in the BREP chip or the SREP repeater tests to determine if the
• remote port is a T4 port, and if not the system goes to block 1604 where the system indicates that
• blocks 1602, 1604, and 1606 are operated by management code.
• the po ⁇ periodically transmits flow control packets.
• po ⁇ sets up a half duplex flow control session with the remote po ⁇ . Also, at block 1622 the
• block 1620 does not detect a BREP chip flow control packet
• the system enters block 1640.
• St block 1640 the management code initializes the BREP po ⁇ , and then the system goes to block 1642.
• the management unit establishes a session without flow control with the remote po ⁇ . The system then goes to block
• Fig. 17 there is shown a flow cha ⁇ giving the steps required to identify the remote port capabilities, in the case that the local PHY device is MTJ TX FDX PHY.
• the BREP chip po ⁇ interrogates the remote po ⁇ in order to determine if the remote po ⁇ is NWay capable. In the event that the remote po ⁇ is not NWay capable, the system goes to block 1704, where the system then goes to the process of Fig. 18. In the event that the remote
• blocks 1702, 1704, 1706, and 1710 are operated by management code.
• blocks 1714, 1716, 1720, 1722, and 1734 are operated by logic in the
• the remote po ⁇ is inte ⁇ ogated in order to determine if it is TX capable.
• the system goes to block 1714.
• the BREP po ⁇ periodically transmits flow control

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Compression Or Coding Systems Of Tv Signals (AREA)
• Filters That Use Time-Delay Elements (AREA)

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• 1998
  • 1998-01-05 AU AU58140/98A patent/AU716101B2/en not_active Ceased
  • 1998-01-05 WO PCT/US1998/000079 patent/WO1998031126A1/en not_active Application Discontinuation
  • 1998-01-05 CA CA002277101A patent/CA2277101A1/en not_active Abandoned
  • 1998-01-05 EP EP98901675A patent/EP0962075A1/de not_active Withdrawn

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