Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/02—Details
  • H01L31/0224—Electrodes
  • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
  • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/547—Monocrystalline silicon PV cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• the achievement of high efficiencies for solar cells on large area substrates is dependent upon achieving narrow line widths and high aspect ratios (ratio of height to width) for the metallization on the surface exposed to sunlight.
• the buried contact solar cell [S.R. Wenham and M.A. Green. US Patents 4.726,850 and 4,748,130] provides a design for the metallization that achieves both fine line widths and high aspect ratios for the metallization while simultaneously being well suited to commercial production.
• previous implementations of the buried contact solar cell metallization scheme have required the deposition or growth of a dielectric or equivalent layer across the top surface of the substrate early in the processing sequence so as to provide masking of the top surface against diffusions, chemical etching, and metal plating.
• this dielectric masking layer has had to be able to withstand the chemical etching and the high temperature processing without deterioration or excessive thinning. This has greatly limited the available choice for such dielectrics, particularly when the dielectric is then required to also act as an anti-reflection coating at the end of the process.
• a typical implementation previously reported in the literature involves the formation of the dielectric layer across the top surface prior to laser scribing. The laser scribing then forms grooves through the dielectric layer and into the silicon material. A chemical etch is then used to clean and etch the grooves while the masking dielectric layer across the top surface prevents the etching solution having any impact on the top surface.
• a high temperature process is then used during which dopants are diffused into the exposed silicon groove walls during which again the dielectric layer masks the top surface to prevent unwanted dopants from penetrating into the silicon.
• the dielectric masking layer must not only be able to withstand the high temperatures involved, but also be able to block the diffusion of dopants through the layer without significant degradation in thickness, chemical resistance, or optical properties.
• further high temperature treatments are isually required associated with the design of the rear metal contact, following which metal plating of the front surface grooves and the rear surface metal contact are effected.
• many of the limitations and requirements for the top surface dielectric masking layer are relaxed, while the overall processing sequence is simultaneously simplified.
• the invention provides a method of processing a semiconductor substrate including the steps of forming one or more grooves in a surface of the substrate, applying dielectric coating to said one surface by a technique which preferentially coats said one surface such that the coating is thicker on said one surface than in the grooves and etching the dielectric coating until some regions of the groove walls are exposed.
• the present invention provides a method of processing a semiconductor substrate including the steps of forming one or more grooves in a surface of the substrate, fo ⁇ ning undercut regions of the groove walls, applying a dielectric coating by a line of sight deposition technique and etching the dielectric coating until some regions of t-he groove walls are exposed.
• the invention provides a method of processing a semiconductor substrate including the steps of forming one or more grooves in a surface of the substrate, the grooves having walls which slope more steeply than a steepest feature of the surface, applying a dielectric coating by a line of sight deposition technique and etching the dielectric coating until some regions of the groove walls are exposed.
• the invention provides a device manufactured using the method of the invention.
• the invention is applicable to the manufacture of silicon solar cells in which the grooves are used to form buried contacts in the cell top surface.
• the top surface and the groove walls will be doped to form a rectifying junction after the grooves are formed but before the dielectric coating is formed.
• the doping will be achieved in such a way that the doping level in the grooves is higher than over the remainder of the top surface. This can be achieved for example by thinning a spin on dopant with a volatile solvent such that a larger volume of the thinned dopant collects in the grooves and then gently heating the dopant to drive off the solvent before heating the substrate more strongly to drive the dopant into the surface.
• the metallization is applied to the grooves in the preferred embodiment after the dielectric has been etched back to expose at least part of the groove walls.
• the thinner dielectric layer in the grooves can be achieved by use of a chemical deposition or reaction process in which the layer thickness in the grooves is limited by depletion of the source material in the groove.
• a line of sight technique such as a spray on source, vacuum evaporation or an ion beam deposition technique is appropriate.
• Figure 1 illustrates a groove in cross section showing undercutting caused by pyramid formations in the groove
• Figure 2 illustrates a groove in cross section showing re-entrant upper wall portions
• Figure 3 illustrates deposition of a dielectric layer by an angled directional deposition technique
• Figure 4 illustrates deposition of a dielectric by Chemical Vapour Deposition (CVD) with depletion of the source in the grooves;
• Figure 5 illustrates deposition of a dielectric layer by another angled deposition technique
• Figure 6 is a top view of an embodiment employing holes instead of trenches.
• Figure 7 illustrates a cell after metallization of the groove showing partial removal of the dielectric layer in the groove:
• Figure 8 illustrates a variation on the arrangement of Figure 5 in which the direction of deposition is perpendicular to the surface of the substrate.
• Embodiments of the present invention make use of the geometry of the groove to allow a dielectric layer to be deposited after the groove formation in a way that ensures that at least some regions of the grooves have a substantially thinner layer deposited than the entire top surface. These regions of reduced thickness dielectric within the grooves are then prematurely etched by an appropriate chemical (or other) etchant capable of controllable etching away the dielectric layer. The result is that in these regions the silicon surface can be exposed and able to be plated by the metallization while the top surface of the solar cell remains protected by the dielectric material.
• the entire groove wall and base does not need to be exposed as only localised areas are sufficient to nucleate plating that will then subsequently facilitate filling the majority of the grooves with the metal.
• nucleating the plating only from isolated regions within the groove minimises the overall metal/silicon contact area and therefore reduces the corresponding recombination.
• the underneath faces 16 of the horizontal pyramids 11 are then effectively shaded by any line of sight deposition technique for the dielectric layer such as spraying or vacuum evaporation etc.
• This approach can be used to controllably determine the regions for thinnest dielectric deposition and hence subsequent metal plating.
• FIG 2 another example of achieving a similar effect, is to form the grooves 9 into the surface so that the grooves are aligned to the ciystal axis. Additional etching of the original groove walls can then be used (using an anisotropic etch) to expose the 1-1-1 crystallographic planes 17. 18 of the silicon wafer 13 within the groove 19. The re-entrant exposed planes 18 near the mouth of the grooves 19 are equivalent to the underneath faces 16 of the horizontal pyramids 11 in the Figure 1 example.
• a third example as shown in Figure 3 is the use of angular deposition 21 (at an angle ⁇ ) of the dielectric layer 27 from the dielectric source to ensure that one side 22 of the groove 23 would be shaded from the deposition, or equivalently grooves can be formed at an angle to the front surface.
• a fourth approach to achieving the selectivity in the groove region would be to use a dielectric deposition technique whereby the species associated with the dielectric growth or deposition would be naturally depleted within the grooves 24 due to the large surface area relative to the dimensions of the mouth of the grooves.
• An example would be the chemical vapour deposition of material in which the gas composition, concentration and flow rate are such as to establish a process limited by the diffusion rate of species in the gas thereby determining the deposition rate by the arrival rate at the surface as shown in Figure 4. where gas flow 25 across the surface 26 limits entry of the gas into the groove 24 thereby causing lower deposition of the dielectric layer 27 on the groove walls 28.
• FIG. 5 Another method of applying a thinner dielectric layer in at least part of the grooves is illustrated in Figure 5 where the slope ⁇ of at least part of the groove walls 51 is steeper than the steepest slope ⁇ of the surface texturing 52 (note texturing within the groove has been omitted from Figure 5 for clarity).
• the directional source 53 in the dielectric deposition process is directed at an angle ⁇ such that ⁇ then parts 54 of the groove walls 51 will be shaded and have a thinner dielectric layer deposited.
• Figure 8 a variation on the arrangement of Figure 5 is illustrated in which the line of sight deposition angle 53 is perpendicular to the surface of the substrate (ie, ⁇ > ⁇ , ⁇ ).
• both walls of the groove will have a thicker dielectric layer than the wall 54 of Fig ire 5 but the dielectric layer in the groove will still be thinner than on the top surface by virtue of the greater slope of the groove walls 51. than the top surface features 52.
• the grooves are illustrated in cross-section with no illustration of their length.
• these grooves will be a series of long parallel trenches, however, it is not necessary that the grooves be continuous across the surface of the cell and for example in Figure 6, the grooves could equally be formed as a series of approximately circular holes 61 having width and length of similar dimensions or they could be slots having a length only a few times their width. In the case of discontinuous holes or slots, these would be interconnected by the surface conductors 62 deposited over the surface dielectric layer 63 by screen printing for example.
• the dielectric layer need not withstand high temperatures nor act as a diffusion mask against unwanted dopants or contaminants increasing both the range of suitable candidates and the range of possible deposition processes.
• the dielectric layer need not be as clean since the risk of contamination of the silicon surface during high temperature processes is removed.
• the dielectric layer need not withstand the chemical etches used for the groove cleaning and etching.
• the number of high temperature processes is reduced since the grooves can now be diffused at the same time as the top surface since a dielectric layer across the top surface is no longer required at this stage of the process for subsequent selectivity of the metal plating.
• the "as-cut” or “as-lapped” wafers 31 are grooved 32 on the top surface 33 using a Q-switched neodynium YAG laser operating at 1.06 microns wavelength.
• the laser power and speed are selected to facilitate the formation of grooves of depth approximately 50 microns, with the pattern formed representing the final design required for the top surface metallization.
• the standard texturing etch comprising 2% sodium hydroxide and 5% propanol can be used at 90°C to simultaneously clean the grooves, remove minor saw damage from the top surface, texture the top surface with upright pyramids 34, and form horizontal pyramids 35 on the groove walls 36.
• Thorough rinsing of the wafers in deionised water is then followed by immersion in diluted hydrochloric acid prior to additional rinsing and immersion in hydrofluoric acid. Wafers are then again thoroughly rinsed prior to spin drying. 3.
• Phosphorus diffusion of the top surface is carried out either from a liquid source (with carrier gas canying the phosphorus compounds into the heated furnace) or solid source.
• the dopant source or phosphorus glass is deposited at a temperature sufficiently low to prevent significant diffusion of phosphorus into the silicon from taking place. This requires keeping temperatures below 800°C until a sufficiently thick phosphorus glass layer has been formed on all of the top surface and groove walls to simulate an infinite source ( ie, make the subsequent diffusion independent of the thickness of the phosphorus glass layers in all regions. Heating of solid source material (P 2 O s ) to high temperature at the end of the furnace tube while maintaining the wafers at a temperature below 800°C is one veiy effective way of achieving this result.
• Liquid spin-on sources can also be used to achieve similar effects and can actually be used to give heavier diffusions within the grooves. This is achieved by diluting the standard commercially available sources with a suitable high purity solvent/liquid such as isopropyl alcohol and then coating, dipping, and/or spinning the wafers so as to leave thicker deposits within the grooves. After drying, a thicker layer with higher phosphorus concentration resides within the regions of the grooves than across the top surface, therefore facilitating heavier phosphorus diffusions in these regions. In this instance the phosphorus glass (if too thick) may have to be removed following the diffusion process to allow a new thin passivating oxide to form during firing of the aluminium contact (the conditions for which can be easily varied accordingly).
• a suitable high purity solvent/liquid such as isopropyl alcohol
• the furnace temperature is ramped upwards to increase the cell temperature to approximately 850°C for 15 minutes, during which time sufficient phosphorus diffuses into the silicon surface to produce an n- type layer 37 with a sheet resistivity in the vicinity of 80 ohms per square.
• Most diffusion processes will simultaneously lead to the formation of an n- type layer across the rear of the surface 45. This rear junction is later destroyed provided the rear metal contact contains a aluminium or an equivalent material capable of destroying the unwanted junction.
• the rear metal contact 38 can be applied by screen printing a metallic paste comprising primarily silver powder but with the inclusion of a small percentage of aluminium.
• the aluminium when sintered at high temperature facilitates good ohmic contact onto the p-type substrate material and will act to simultaneously destroy any unwanted rear junctions.
• screen printing pastes are readily available commercially.
• the wafer is dried for a period of time at about 250°C prior to being "fired” at 850°C in a infra ⁇ red belt furnace for approximately 30 seconds.
• the anti-reflection coating can be applied directly onto the wafer top surface while retaining the good surface passivation properties provided by the diffusion oxide
• the anti-reflection coating can be titanium dioxide with its formation from liquid isopropyl titanate being well documented in the literature.
• the isopropyl titanate can be sprayed through the use of a compressor and carrier gas onto the heated wafer so that the source is oxidised therefore forming the titanium dioxide layer 41.
• the chemical resistance and chemical composition of the deposited layer is somewhat dependent on the temperature of the hot plate and the rate of spraying. Hot plate temperatures in the vicinity of 200°C are commonly used.
• the wafer Prior to electroless plating, the wafer is immersed in concentrated hydrofluoric acid which gradually etches the titanium dioxide. The length of such etching is determined by the time necessary to expose a sufficient area 42 of silicon within the grooves that corresponds to the area required for the metal/silicon contact. Following rinsing, the wafers are electrolessly plated in nickel in commercially available solutions heated to about 90°C. After 2 minutes of plating the wafers are rinsed and dried prior to being sintered at between 350°C and 400°C for approximately 10 minutes to enable nickel silicide to be formed. Wafers are then again plated in electroless nickel for 2 minutes prior to plating in electroless copper at approx 50°C until the grooves are substantially filled with copper 43.
• the electroless plating solutions are readily available commercially.
• the wafers are again rinsed prior to immersion in a solution that deposits a very thin layer of silver 44 on the surface of the copper. This silver is used to improve solderability and protect the copper surface from oxidation and reaction with encapsulants.
• the final step in the process is for wafers to be edge junction isolated.

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• 1995
  • 1995-10-19 AU AUPN6063A patent/AUPN606395A0/en not_active Abandoned
• 1996
  • 1996-10-14 WO PCT/AU1996/000647 patent/WO1997015075A1/en not_active Application Discontinuation
  • 1996-10-14 JP JP9515350A patent/JPH11514498A/ja not_active Ceased
  • 1996-10-14 EP EP96933268A patent/EP0958597A1/de not_active Withdrawn

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